1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/sparc64/mm/init.c 4 * 5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 */ 8 9 #include <linux/extable.h> 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <linux/string.h> 13 #include <linux/init.h> 14 #include <linux/memblock.h> 15 #include <linux/mm.h> 16 #include <linux/hugetlb.h> 17 #include <linux/initrd.h> 18 #include <linux/swap.h> 19 #include <linux/pagemap.h> 20 #include <linux/poison.h> 21 #include <linux/fs.h> 22 #include <linux/seq_file.h> 23 #include <linux/kprobes.h> 24 #include <linux/cache.h> 25 #include <linux/sort.h> 26 #include <linux/ioport.h> 27 #include <linux/percpu.h> 28 #include <linux/mmzone.h> 29 #include <linux/gfp.h> 30 31 #include <asm/head.h> 32 #include <asm/page.h> 33 #include <asm/pgalloc.h> 34 #include <asm/oplib.h> 35 #include <asm/iommu.h> 36 #include <asm/io.h> 37 #include <linux/uaccess.h> 38 #include <asm/mmu_context.h> 39 #include <asm/tlbflush.h> 40 #include <asm/dma.h> 41 #include <asm/starfire.h> 42 #include <asm/tlb.h> 43 #include <asm/spitfire.h> 44 #include <asm/sections.h> 45 #include <asm/tsb.h> 46 #include <asm/hypervisor.h> 47 #include <asm/prom.h> 48 #include <asm/mdesc.h> 49 #include <asm/cpudata.h> 50 #include <asm/setup.h> 51 #include <asm/irq.h> 52 53 #include "init_64.h" 54 55 unsigned long kern_linear_pte_xor[4] __read_mostly; 56 static unsigned long page_cache4v_flag; 57 58 /* A bitmap, two bits for every 256MB of physical memory. These two 59 * bits determine what page size we use for kernel linear 60 * translations. They form an index into kern_linear_pte_xor[]. The 61 * value in the indexed slot is XOR'd with the TLB miss virtual 62 * address to form the resulting TTE. The mapping is: 63 * 64 * 0 ==> 4MB 65 * 1 ==> 256MB 66 * 2 ==> 2GB 67 * 3 ==> 16GB 68 * 69 * All sun4v chips support 256MB pages. Only SPARC-T4 and later 70 * support 2GB pages, and hopefully future cpus will support the 16GB 71 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there 72 * if these larger page sizes are not supported by the cpu. 73 * 74 * It would be nice to determine this from the machine description 75 * 'cpu' properties, but we need to have this table setup before the 76 * MDESC is initialized. 77 */ 78 79 #ifndef CONFIG_DEBUG_PAGEALLOC 80 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. 81 * Space is allocated for this right after the trap table in 82 * arch/sparc64/kernel/head.S 83 */ 84 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; 85 #endif 86 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; 87 88 static unsigned long cpu_pgsz_mask; 89 90 #define MAX_BANKS 1024 91 92 static struct linux_prom64_registers pavail[MAX_BANKS]; 93 static int pavail_ents; 94 95 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES]; 96 97 static int cmp_p64(const void *a, const void *b) 98 { 99 const struct linux_prom64_registers *x = a, *y = b; 100 101 if (x->phys_addr > y->phys_addr) 102 return 1; 103 if (x->phys_addr < y->phys_addr) 104 return -1; 105 return 0; 106 } 107 108 static void __init read_obp_memory(const char *property, 109 struct linux_prom64_registers *regs, 110 int *num_ents) 111 { 112 phandle node = prom_finddevice("/memory"); 113 int prop_size = prom_getproplen(node, property); 114 int ents, ret, i; 115 116 ents = prop_size / sizeof(struct linux_prom64_registers); 117 if (ents > MAX_BANKS) { 118 prom_printf("The machine has more %s property entries than " 119 "this kernel can support (%d).\n", 120 property, MAX_BANKS); 121 prom_halt(); 122 } 123 124 ret = prom_getproperty(node, property, (char *) regs, prop_size); 125 if (ret == -1) { 126 prom_printf("Couldn't get %s property from /memory.\n", 127 property); 128 prom_halt(); 129 } 130 131 /* Sanitize what we got from the firmware, by page aligning 132 * everything. 133 */ 134 for (i = 0; i < ents; i++) { 135 unsigned long base, size; 136 137 base = regs[i].phys_addr; 138 size = regs[i].reg_size; 139 140 size &= PAGE_MASK; 141 if (base & ~PAGE_MASK) { 142 unsigned long new_base = PAGE_ALIGN(base); 143 144 size -= new_base - base; 145 if ((long) size < 0L) 146 size = 0UL; 147 base = new_base; 148 } 149 if (size == 0UL) { 150 /* If it is empty, simply get rid of it. 151 * This simplifies the logic of the other 152 * functions that process these arrays. 153 */ 154 memmove(®s[i], ®s[i + 1], 155 (ents - i - 1) * sizeof(regs[0])); 156 i--; 157 ents--; 158 continue; 159 } 160 regs[i].phys_addr = base; 161 regs[i].reg_size = size; 162 } 163 164 *num_ents = ents; 165 166 sort(regs, ents, sizeof(struct linux_prom64_registers), 167 cmp_p64, NULL); 168 } 169 170 /* Kernel physical address base and size in bytes. */ 171 unsigned long kern_base __read_mostly; 172 unsigned long kern_size __read_mostly; 173 174 /* Initial ramdisk setup */ 175 extern unsigned long sparc_ramdisk_image64; 176 extern unsigned int sparc_ramdisk_image; 177 extern unsigned int sparc_ramdisk_size; 178 179 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; 180 181 unsigned long sparc64_kern_pri_context __read_mostly; 182 unsigned long sparc64_kern_pri_nuc_bits __read_mostly; 183 unsigned long sparc64_kern_sec_context __read_mostly; 184 185 int num_kernel_image_mappings; 186 187 #ifdef CONFIG_DEBUG_DCFLUSH 188 atomic_t dcpage_flushes = ATOMIC_INIT(0); 189 #ifdef CONFIG_SMP 190 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); 191 #endif 192 #endif 193 194 inline void flush_dcache_folio_impl(struct folio *folio) 195 { 196 unsigned int i, nr = folio_nr_pages(folio); 197 198 BUG_ON(tlb_type == hypervisor); 199 #ifdef CONFIG_DEBUG_DCFLUSH 200 atomic_inc(&dcpage_flushes); 201 #endif 202 203 #ifdef DCACHE_ALIASING_POSSIBLE 204 for (i = 0; i < nr; i++) 205 __flush_dcache_page(folio_address(folio) + i * PAGE_SIZE, 206 ((tlb_type == spitfire) && 207 folio_flush_mapping(folio) != NULL)); 208 #else 209 if (folio_flush_mapping(folio) != NULL && 210 tlb_type == spitfire) { 211 for (i = 0; i < nr; i++) 212 __flush_icache_page((pfn + i) * PAGE_SIZE); 213 } 214 #endif 215 } 216 217 #define PG_dcache_dirty PG_arch_1 218 #define PG_dcache_cpu_shift 32UL 219 #define PG_dcache_cpu_mask \ 220 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) 221 222 #define dcache_dirty_cpu(folio) \ 223 (((folio)->flags.f >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) 224 225 static inline void set_dcache_dirty(struct folio *folio, int this_cpu) 226 { 227 unsigned long mask = this_cpu; 228 unsigned long non_cpu_bits; 229 230 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); 231 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); 232 233 __asm__ __volatile__("1:\n\t" 234 "ldx [%2], %%g7\n\t" 235 "and %%g7, %1, %%g1\n\t" 236 "or %%g1, %0, %%g1\n\t" 237 "casx [%2], %%g7, %%g1\n\t" 238 "cmp %%g7, %%g1\n\t" 239 "bne,pn %%xcc, 1b\n\t" 240 " nop" 241 : /* no outputs */ 242 : "r" (mask), "r" (non_cpu_bits), "r" (&folio->flags.f) 243 : "g1", "g7"); 244 } 245 246 static inline void clear_dcache_dirty_cpu(struct folio *folio, unsigned long cpu) 247 { 248 unsigned long mask = (1UL << PG_dcache_dirty); 249 250 __asm__ __volatile__("! test_and_clear_dcache_dirty\n" 251 "1:\n\t" 252 "ldx [%2], %%g7\n\t" 253 "srlx %%g7, %4, %%g1\n\t" 254 "and %%g1, %3, %%g1\n\t" 255 "cmp %%g1, %0\n\t" 256 "bne,pn %%icc, 2f\n\t" 257 " andn %%g7, %1, %%g1\n\t" 258 "casx [%2], %%g7, %%g1\n\t" 259 "cmp %%g7, %%g1\n\t" 260 "bne,pn %%xcc, 1b\n\t" 261 " nop\n" 262 "2:" 263 : /* no outputs */ 264 : "r" (cpu), "r" (mask), "r" (&folio->flags.f), 265 "i" (PG_dcache_cpu_mask), 266 "i" (PG_dcache_cpu_shift) 267 : "g1", "g7"); 268 } 269 270 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) 271 { 272 unsigned long tsb_addr = (unsigned long) ent; 273 274 if (tlb_type == cheetah_plus || tlb_type == hypervisor) 275 tsb_addr = __pa(tsb_addr); 276 277 __tsb_insert(tsb_addr, tag, pte); 278 } 279 280 unsigned long _PAGE_ALL_SZ_BITS __read_mostly; 281 282 static void flush_dcache(unsigned long pfn) 283 { 284 struct page *page; 285 286 page = pfn_to_page(pfn); 287 if (page) { 288 struct folio *folio = page_folio(page); 289 unsigned long pg_flags; 290 291 pg_flags = folio->flags.f; 292 if (pg_flags & (1UL << PG_dcache_dirty)) { 293 int cpu = ((pg_flags >> PG_dcache_cpu_shift) & 294 PG_dcache_cpu_mask); 295 int this_cpu = get_cpu(); 296 297 /* This is just to optimize away some function calls 298 * in the SMP case. 299 */ 300 if (cpu == this_cpu) 301 flush_dcache_folio_impl(folio); 302 else 303 smp_flush_dcache_folio_impl(folio, cpu); 304 305 clear_dcache_dirty_cpu(folio, cpu); 306 307 put_cpu(); 308 } 309 } 310 } 311 312 /* mm->context.lock must be held */ 313 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, 314 unsigned long tsb_hash_shift, unsigned long address, 315 unsigned long tte) 316 { 317 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; 318 unsigned long tag; 319 320 if (unlikely(!tsb)) 321 return; 322 323 tsb += ((address >> tsb_hash_shift) & 324 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); 325 tag = (address >> 22UL); 326 tsb_insert(tsb, tag, tte); 327 } 328 329 #ifdef CONFIG_HUGETLB_PAGE 330 static int __init hugetlbpage_init(void) 331 { 332 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT); 333 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT); 334 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT); 335 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT); 336 337 return 0; 338 } 339 340 arch_initcall(hugetlbpage_init); 341 342 static void __init pud_huge_patch(void) 343 { 344 struct pud_huge_patch_entry *p; 345 unsigned long addr; 346 347 p = &__pud_huge_patch; 348 addr = p->addr; 349 *(unsigned int *)addr = p->insn; 350 351 __asm__ __volatile__("flush %0" : : "r" (addr)); 352 } 353 354 bool __init arch_hugetlb_valid_size(unsigned long size) 355 { 356 unsigned int hugepage_shift = ilog2(size); 357 unsigned int hv_pgsz_mask; 358 359 switch (hugepage_shift) { 360 case HPAGE_16GB_SHIFT: 361 hv_pgsz_mask = HV_PGSZ_MASK_16GB; 362 pud_huge_patch(); 363 break; 364 case HPAGE_2GB_SHIFT: 365 hv_pgsz_mask = HV_PGSZ_MASK_2GB; 366 break; 367 case HPAGE_256MB_SHIFT: 368 hv_pgsz_mask = HV_PGSZ_MASK_256MB; 369 break; 370 case HPAGE_SHIFT: 371 hv_pgsz_mask = HV_PGSZ_MASK_4MB; 372 break; 373 case HPAGE_64K_SHIFT: 374 hv_pgsz_mask = HV_PGSZ_MASK_64K; 375 break; 376 default: 377 hv_pgsz_mask = 0; 378 } 379 380 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) 381 return false; 382 383 return true; 384 } 385 #endif /* CONFIG_HUGETLB_PAGE */ 386 387 void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma, 388 unsigned long address, pte_t *ptep, unsigned int nr) 389 { 390 struct mm_struct *mm; 391 unsigned long flags; 392 bool is_huge_tsb; 393 pte_t pte = *ptep; 394 unsigned int i; 395 396 if (tlb_type != hypervisor) { 397 unsigned long pfn = pte_pfn(pte); 398 399 if (pfn_valid(pfn)) 400 flush_dcache(pfn); 401 } 402 403 mm = vma->vm_mm; 404 405 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ 406 if (!pte_accessible(mm, pte)) 407 return; 408 409 spin_lock_irqsave(&mm->context.lock, flags); 410 411 is_huge_tsb = false; 412 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 413 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) { 414 unsigned long hugepage_size = PAGE_SIZE; 415 416 if (is_vm_hugetlb_page(vma)) 417 hugepage_size = huge_page_size(hstate_vma(vma)); 418 419 if (hugepage_size >= PUD_SIZE) { 420 unsigned long mask = 0x1ffc00000UL; 421 422 /* Transfer bits [32:22] from address to resolve 423 * at 4M granularity. 424 */ 425 pte_val(pte) &= ~mask; 426 pte_val(pte) |= (address & mask); 427 } else if (hugepage_size >= PMD_SIZE) { 428 /* We are fabricating 8MB pages using 4MB 429 * real hw pages. 430 */ 431 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT)); 432 } 433 434 if (hugepage_size >= PMD_SIZE) { 435 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, 436 REAL_HPAGE_SHIFT, address, pte_val(pte)); 437 is_huge_tsb = true; 438 } 439 } 440 #endif 441 if (!is_huge_tsb) { 442 for (i = 0; i < nr; i++) { 443 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, 444 address, pte_val(pte)); 445 address += PAGE_SIZE; 446 pte_val(pte) += PAGE_SIZE; 447 } 448 } 449 450 spin_unlock_irqrestore(&mm->context.lock, flags); 451 } 452 453 void flush_dcache_folio(struct folio *folio) 454 { 455 unsigned long pfn = folio_pfn(folio); 456 struct address_space *mapping; 457 int this_cpu; 458 459 if (tlb_type == hypervisor) 460 return; 461 462 /* Do not bother with the expensive D-cache flush if it 463 * is merely the zero page. The 'bigcore' testcase in GDB 464 * causes this case to run millions of times. 465 */ 466 if (is_zero_pfn(pfn)) 467 return; 468 469 this_cpu = get_cpu(); 470 471 mapping = folio_flush_mapping(folio); 472 if (mapping && !mapping_mapped(mapping)) { 473 bool dirty = test_bit(PG_dcache_dirty, &folio->flags.f); 474 if (dirty) { 475 int dirty_cpu = dcache_dirty_cpu(folio); 476 477 if (dirty_cpu == this_cpu) 478 goto out; 479 smp_flush_dcache_folio_impl(folio, dirty_cpu); 480 } 481 set_dcache_dirty(folio, this_cpu); 482 } else { 483 /* We could delay the flush for the !folio_mapping 484 * case too. But that case is for exec env/arg 485 * pages and those are %99 certainly going to get 486 * faulted into the tlb (and thus flushed) anyways. 487 */ 488 flush_dcache_folio_impl(folio); 489 } 490 491 out: 492 put_cpu(); 493 } 494 EXPORT_SYMBOL(flush_dcache_folio); 495 496 void __kprobes flush_icache_range(unsigned long start, unsigned long end) 497 { 498 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ 499 if (tlb_type == spitfire) { 500 unsigned long kaddr; 501 502 /* This code only runs on Spitfire cpus so this is 503 * why we can assume _PAGE_PADDR_4U. 504 */ 505 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { 506 unsigned long paddr, mask = _PAGE_PADDR_4U; 507 508 if (kaddr >= PAGE_OFFSET) 509 paddr = kaddr & mask; 510 else { 511 pte_t *ptep = virt_to_kpte(kaddr); 512 513 paddr = pte_val(*ptep) & mask; 514 } 515 __flush_icache_page(paddr); 516 } 517 } 518 } 519 EXPORT_SYMBOL(flush_icache_range); 520 521 void mmu_info(struct seq_file *m) 522 { 523 static const char *pgsz_strings[] = { 524 "8K", "64K", "512K", "4MB", "32MB", 525 "256MB", "2GB", "16GB", 526 }; 527 int i, printed; 528 529 if (tlb_type == cheetah) 530 seq_printf(m, "MMU Type\t: Cheetah\n"); 531 else if (tlb_type == cheetah_plus) 532 seq_printf(m, "MMU Type\t: Cheetah+\n"); 533 else if (tlb_type == spitfire) 534 seq_printf(m, "MMU Type\t: Spitfire\n"); 535 else if (tlb_type == hypervisor) 536 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); 537 else 538 seq_printf(m, "MMU Type\t: ???\n"); 539 540 seq_printf(m, "MMU PGSZs\t: "); 541 printed = 0; 542 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { 543 if (cpu_pgsz_mask & (1UL << i)) { 544 seq_printf(m, "%s%s", 545 printed ? "," : "", pgsz_strings[i]); 546 printed++; 547 } 548 } 549 seq_putc(m, '\n'); 550 551 #ifdef CONFIG_DEBUG_DCFLUSH 552 seq_printf(m, "DCPageFlushes\t: %d\n", 553 atomic_read(&dcpage_flushes)); 554 #ifdef CONFIG_SMP 555 seq_printf(m, "DCPageFlushesXC\t: %d\n", 556 atomic_read(&dcpage_flushes_xcall)); 557 #endif /* CONFIG_SMP */ 558 #endif /* CONFIG_DEBUG_DCFLUSH */ 559 } 560 561 struct linux_prom_translation prom_trans[512] __read_mostly; 562 unsigned int prom_trans_ents __read_mostly; 563 564 unsigned long kern_locked_tte_data; 565 566 /* The obp translations are saved based on 8k pagesize, since obp can 567 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> 568 * HI_OBP_ADDRESS range are handled in ktlb.S. 569 */ 570 static inline int in_obp_range(unsigned long vaddr) 571 { 572 return (vaddr >= LOW_OBP_ADDRESS && 573 vaddr < HI_OBP_ADDRESS); 574 } 575 576 static int cmp_ptrans(const void *a, const void *b) 577 { 578 const struct linux_prom_translation *x = a, *y = b; 579 580 if (x->virt > y->virt) 581 return 1; 582 if (x->virt < y->virt) 583 return -1; 584 return 0; 585 } 586 587 /* Read OBP translations property into 'prom_trans[]'. */ 588 static void __init read_obp_translations(void) 589 { 590 int n, node, ents, first, last, i; 591 592 node = prom_finddevice("/virtual-memory"); 593 n = prom_getproplen(node, "translations"); 594 if (unlikely(n == 0 || n == -1)) { 595 prom_printf("prom_mappings: Couldn't get size.\n"); 596 prom_halt(); 597 } 598 if (unlikely(n > sizeof(prom_trans))) { 599 prom_printf("prom_mappings: Size %d is too big.\n", n); 600 prom_halt(); 601 } 602 603 if ((n = prom_getproperty(node, "translations", 604 (char *)&prom_trans[0], 605 sizeof(prom_trans))) == -1) { 606 prom_printf("prom_mappings: Couldn't get property.\n"); 607 prom_halt(); 608 } 609 610 n = n / sizeof(struct linux_prom_translation); 611 612 ents = n; 613 614 sort(prom_trans, ents, sizeof(struct linux_prom_translation), 615 cmp_ptrans, NULL); 616 617 /* Now kick out all the non-OBP entries. */ 618 for (i = 0; i < ents; i++) { 619 if (in_obp_range(prom_trans[i].virt)) 620 break; 621 } 622 first = i; 623 for (; i < ents; i++) { 624 if (!in_obp_range(prom_trans[i].virt)) 625 break; 626 } 627 last = i; 628 629 for (i = 0; i < (last - first); i++) { 630 struct linux_prom_translation *src = &prom_trans[i + first]; 631 struct linux_prom_translation *dest = &prom_trans[i]; 632 633 *dest = *src; 634 } 635 for (; i < ents; i++) { 636 struct linux_prom_translation *dest = &prom_trans[i]; 637 dest->virt = dest->size = dest->data = 0x0UL; 638 } 639 640 prom_trans_ents = last - first; 641 642 if (tlb_type == spitfire) { 643 /* Clear diag TTE bits. */ 644 for (i = 0; i < prom_trans_ents; i++) 645 prom_trans[i].data &= ~0x0003fe0000000000UL; 646 } 647 648 /* Force execute bit on. */ 649 for (i = 0; i < prom_trans_ents; i++) 650 prom_trans[i].data |= (tlb_type == hypervisor ? 651 _PAGE_EXEC_4V : _PAGE_EXEC_4U); 652 } 653 654 static void __init hypervisor_tlb_lock(unsigned long vaddr, 655 unsigned long pte, 656 unsigned long mmu) 657 { 658 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); 659 660 if (ret != 0) { 661 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " 662 "errors with %lx\n", vaddr, 0, pte, mmu, ret); 663 prom_halt(); 664 } 665 } 666 667 static unsigned long kern_large_tte(unsigned long paddr); 668 669 static void __init remap_kernel(void) 670 { 671 unsigned long phys_page, tte_vaddr, tte_data; 672 int i, tlb_ent = sparc64_highest_locked_tlbent(); 673 674 tte_vaddr = (unsigned long) KERNBASE; 675 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 676 tte_data = kern_large_tte(phys_page); 677 678 kern_locked_tte_data = tte_data; 679 680 /* Now lock us into the TLBs via Hypervisor or OBP. */ 681 if (tlb_type == hypervisor) { 682 for (i = 0; i < num_kernel_image_mappings; i++) { 683 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); 684 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); 685 tte_vaddr += 0x400000; 686 tte_data += 0x400000; 687 } 688 } else { 689 for (i = 0; i < num_kernel_image_mappings; i++) { 690 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); 691 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); 692 tte_vaddr += 0x400000; 693 tte_data += 0x400000; 694 } 695 sparc64_highest_unlocked_tlb_ent = tlb_ent - i; 696 } 697 if (tlb_type == cheetah_plus) { 698 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 699 CTX_CHEETAH_PLUS_NUC); 700 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; 701 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; 702 } 703 } 704 705 706 static void __init inherit_prom_mappings(void) 707 { 708 /* Now fixup OBP's idea about where we really are mapped. */ 709 printk("Remapping the kernel... "); 710 remap_kernel(); 711 printk("done.\n"); 712 } 713 714 void prom_world(int enter) 715 { 716 /* 717 * No need to change the address space any more, just flush 718 * the register windows 719 */ 720 __asm__ __volatile__("flushw"); 721 } 722 723 void __flush_dcache_range(unsigned long start, unsigned long end) 724 { 725 unsigned long va; 726 727 if (tlb_type == spitfire) { 728 int n = 0; 729 730 for (va = start; va < end; va += 32) { 731 spitfire_put_dcache_tag(va & 0x3fe0, 0x0); 732 if (++n >= 512) 733 break; 734 } 735 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 736 start = __pa(start); 737 end = __pa(end); 738 for (va = start; va < end; va += 32) 739 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 740 "membar #Sync" 741 : /* no outputs */ 742 : "r" (va), 743 "i" (ASI_DCACHE_INVALIDATE)); 744 } 745 } 746 EXPORT_SYMBOL(__flush_dcache_range); 747 748 /* get_new_mmu_context() uses "cache + 1". */ 749 DEFINE_SPINLOCK(ctx_alloc_lock); 750 unsigned long tlb_context_cache = CTX_FIRST_VERSION; 751 #define MAX_CTX_NR (1UL << CTX_NR_BITS) 752 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) 753 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); 754 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0}; 755 756 static void mmu_context_wrap(void) 757 { 758 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK; 759 unsigned long new_ver, new_ctx, old_ctx; 760 struct mm_struct *mm; 761 int cpu; 762 763 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS); 764 765 /* Reserve kernel context */ 766 set_bit(0, mmu_context_bmap); 767 768 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION; 769 if (unlikely(new_ver == 0)) 770 new_ver = CTX_FIRST_VERSION; 771 tlb_context_cache = new_ver; 772 773 /* 774 * Make sure that any new mm that are added into per_cpu_secondary_mm, 775 * are going to go through get_new_mmu_context() path. 776 */ 777 mb(); 778 779 /* 780 * Updated versions to current on those CPUs that had valid secondary 781 * contexts 782 */ 783 for_each_online_cpu(cpu) { 784 /* 785 * If a new mm is stored after we took this mm from the array, 786 * it will go into get_new_mmu_context() path, because we 787 * already bumped the version in tlb_context_cache. 788 */ 789 mm = per_cpu(per_cpu_secondary_mm, cpu); 790 791 if (unlikely(!mm || mm == &init_mm)) 792 continue; 793 794 old_ctx = mm->context.sparc64_ctx_val; 795 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) { 796 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver; 797 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap); 798 mm->context.sparc64_ctx_val = new_ctx; 799 } 800 } 801 } 802 803 /* Caller does TLB context flushing on local CPU if necessary. 804 * The caller also ensures that CTX_VALID(mm->context) is false. 805 * 806 * We must be careful about boundary cases so that we never 807 * let the user have CTX 0 (nucleus) or we ever use a CTX 808 * version of zero (and thus NO_CONTEXT would not be caught 809 * by version mis-match tests in mmu_context.h). 810 * 811 * Always invoked with interrupts disabled. 812 */ 813 void get_new_mmu_context(struct mm_struct *mm) 814 { 815 unsigned long ctx, new_ctx; 816 unsigned long orig_pgsz_bits; 817 818 spin_lock(&ctx_alloc_lock); 819 retry: 820 /* wrap might have happened, test again if our context became valid */ 821 if (unlikely(CTX_VALID(mm->context))) 822 goto out; 823 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); 824 ctx = (tlb_context_cache + 1) & CTX_NR_MASK; 825 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); 826 if (new_ctx >= (1 << CTX_NR_BITS)) { 827 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); 828 if (new_ctx >= ctx) { 829 mmu_context_wrap(); 830 goto retry; 831 } 832 } 833 if (mm->context.sparc64_ctx_val) 834 cpumask_clear(mm_cpumask(mm)); 835 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); 836 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); 837 tlb_context_cache = new_ctx; 838 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; 839 out: 840 spin_unlock(&ctx_alloc_lock); 841 } 842 843 static int numa_enabled = 1; 844 static int numa_debug; 845 846 static int __init early_numa(char *p) 847 { 848 if (!p) 849 return 0; 850 851 if (strstr(p, "off")) 852 numa_enabled = 0; 853 854 if (strstr(p, "debug")) 855 numa_debug = 1; 856 857 return 0; 858 } 859 early_param("numa", early_numa); 860 861 #define numadbg(f, a...) \ 862 do { if (numa_debug) \ 863 printk(KERN_INFO f, ## a); \ 864 } while (0) 865 866 static void __init find_ramdisk(unsigned long phys_base) 867 { 868 #ifdef CONFIG_BLK_DEV_INITRD 869 if (sparc_ramdisk_image || sparc_ramdisk_image64) { 870 unsigned long ramdisk_image; 871 872 /* Older versions of the bootloader only supported a 873 * 32-bit physical address for the ramdisk image 874 * location, stored at sparc_ramdisk_image. Newer 875 * SILO versions set sparc_ramdisk_image to zero and 876 * provide a full 64-bit physical address at 877 * sparc_ramdisk_image64. 878 */ 879 ramdisk_image = sparc_ramdisk_image; 880 if (!ramdisk_image) 881 ramdisk_image = sparc_ramdisk_image64; 882 883 /* Another bootloader quirk. The bootloader normalizes 884 * the physical address to KERNBASE, so we have to 885 * factor that back out and add in the lowest valid 886 * physical page address to get the true physical address. 887 */ 888 ramdisk_image -= KERNBASE; 889 ramdisk_image += phys_base; 890 891 numadbg("Found ramdisk at physical address 0x%lx, size %u\n", 892 ramdisk_image, sparc_ramdisk_size); 893 894 initrd_start = ramdisk_image; 895 initrd_end = ramdisk_image + sparc_ramdisk_size; 896 897 memblock_reserve(initrd_start, sparc_ramdisk_size); 898 899 initrd_start += PAGE_OFFSET; 900 initrd_end += PAGE_OFFSET; 901 } 902 #endif 903 } 904 905 struct node_mem_mask { 906 unsigned long mask; 907 unsigned long match; 908 }; 909 static struct node_mem_mask node_masks[MAX_NUMNODES]; 910 static int num_node_masks; 911 912 #ifdef CONFIG_NUMA 913 914 struct mdesc_mlgroup { 915 u64 node; 916 u64 latency; 917 u64 match; 918 u64 mask; 919 }; 920 921 static struct mdesc_mlgroup *mlgroups; 922 static int num_mlgroups; 923 924 int numa_cpu_lookup_table[NR_CPUS]; 925 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; 926 927 struct mdesc_mblock { 928 u64 base; 929 u64 size; 930 u64 offset; /* RA-to-PA */ 931 }; 932 static struct mdesc_mblock *mblocks; 933 static int num_mblocks; 934 935 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr) 936 { 937 struct mdesc_mblock *m = NULL; 938 int i; 939 940 for (i = 0; i < num_mblocks; i++) { 941 m = &mblocks[i]; 942 943 if (addr >= m->base && 944 addr < (m->base + m->size)) { 945 break; 946 } 947 } 948 949 return m; 950 } 951 952 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid) 953 { 954 int prev_nid, new_nid; 955 956 prev_nid = NUMA_NO_NODE; 957 for ( ; start < end; start += PAGE_SIZE) { 958 for (new_nid = 0; new_nid < num_node_masks; new_nid++) { 959 struct node_mem_mask *p = &node_masks[new_nid]; 960 961 if ((start & p->mask) == p->match) { 962 if (prev_nid == NUMA_NO_NODE) 963 prev_nid = new_nid; 964 break; 965 } 966 } 967 968 if (new_nid == num_node_masks) { 969 prev_nid = 0; 970 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.", 971 start); 972 break; 973 } 974 975 if (prev_nid != new_nid) 976 break; 977 } 978 *nid = prev_nid; 979 980 return start > end ? end : start; 981 } 982 983 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid) 984 { 985 u64 ret_end, pa_start, m_mask, m_match, m_end; 986 struct mdesc_mblock *mblock; 987 int _nid, i; 988 989 if (tlb_type != hypervisor) 990 return memblock_nid_range_sun4u(start, end, nid); 991 992 mblock = addr_to_mblock(start); 993 if (!mblock) { 994 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]", 995 start); 996 997 _nid = 0; 998 ret_end = end; 999 goto done; 1000 } 1001 1002 pa_start = start + mblock->offset; 1003 m_match = 0; 1004 m_mask = 0; 1005 1006 for (_nid = 0; _nid < num_node_masks; _nid++) { 1007 struct node_mem_mask *const m = &node_masks[_nid]; 1008 1009 if ((pa_start & m->mask) == m->match) { 1010 m_match = m->match; 1011 m_mask = m->mask; 1012 break; 1013 } 1014 } 1015 1016 if (num_node_masks == _nid) { 1017 /* We could not find NUMA group, so default to 0, but lets 1018 * search for latency group, so we could calculate the correct 1019 * end address that we return 1020 */ 1021 _nid = 0; 1022 1023 for (i = 0; i < num_mlgroups; i++) { 1024 struct mdesc_mlgroup *const m = &mlgroups[i]; 1025 1026 if ((pa_start & m->mask) == m->match) { 1027 m_match = m->match; 1028 m_mask = m->mask; 1029 break; 1030 } 1031 } 1032 1033 if (i == num_mlgroups) { 1034 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]", 1035 start); 1036 1037 ret_end = end; 1038 goto done; 1039 } 1040 } 1041 1042 /* 1043 * Each latency group has match and mask, and each memory block has an 1044 * offset. An address belongs to a latency group if its address matches 1045 * the following formula: ((addr + offset) & mask) == match 1046 * It is, however, slow to check every single page if it matches a 1047 * particular latency group. As optimization we calculate end value by 1048 * using bit arithmetics. 1049 */ 1050 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset; 1051 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1); 1052 ret_end = m_end > end ? end : m_end; 1053 1054 done: 1055 *nid = _nid; 1056 return ret_end; 1057 } 1058 #endif 1059 1060 /* This must be invoked after performing all of the necessary 1061 * memblock_set_node() calls for 'nid'. We need to be able to get 1062 * correct data from get_pfn_range_for_nid(). 1063 */ 1064 static void __init allocate_node_data(int nid) 1065 { 1066 struct pglist_data *p; 1067 unsigned long start_pfn, end_pfn; 1068 1069 #ifdef CONFIG_NUMA 1070 alloc_node_data(nid); 1071 1072 NODE_DATA(nid)->node_id = nid; 1073 #endif 1074 1075 p = NODE_DATA(nid); 1076 1077 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); 1078 p->node_start_pfn = start_pfn; 1079 p->node_spanned_pages = end_pfn - start_pfn; 1080 } 1081 1082 static void init_node_masks_nonnuma(void) 1083 { 1084 #ifdef CONFIG_NUMA 1085 int i; 1086 #endif 1087 1088 numadbg("Initializing tables for non-numa.\n"); 1089 1090 node_masks[0].mask = 0; 1091 node_masks[0].match = 0; 1092 num_node_masks = 1; 1093 1094 #ifdef CONFIG_NUMA 1095 for (i = 0; i < NR_CPUS; i++) 1096 numa_cpu_lookup_table[i] = 0; 1097 1098 cpumask_setall(&numa_cpumask_lookup_table[0]); 1099 #endif 1100 } 1101 1102 #ifdef CONFIG_NUMA 1103 1104 EXPORT_SYMBOL(numa_cpu_lookup_table); 1105 EXPORT_SYMBOL(numa_cpumask_lookup_table); 1106 1107 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, 1108 u32 cfg_handle) 1109 { 1110 u64 arc; 1111 1112 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { 1113 u64 target = mdesc_arc_target(md, arc); 1114 const u64 *val; 1115 1116 val = mdesc_get_property(md, target, 1117 "cfg-handle", NULL); 1118 if (val && *val == cfg_handle) 1119 return 0; 1120 } 1121 return -ENODEV; 1122 } 1123 1124 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, 1125 u32 cfg_handle) 1126 { 1127 u64 arc, candidate, best_latency = ~(u64)0; 1128 1129 candidate = MDESC_NODE_NULL; 1130 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1131 u64 target = mdesc_arc_target(md, arc); 1132 const char *name = mdesc_node_name(md, target); 1133 const u64 *val; 1134 1135 if (strcmp(name, "pio-latency-group")) 1136 continue; 1137 1138 val = mdesc_get_property(md, target, "latency", NULL); 1139 if (!val) 1140 continue; 1141 1142 if (*val < best_latency) { 1143 candidate = target; 1144 best_latency = *val; 1145 } 1146 } 1147 1148 if (candidate == MDESC_NODE_NULL) 1149 return -ENODEV; 1150 1151 return scan_pio_for_cfg_handle(md, candidate, cfg_handle); 1152 } 1153 1154 int of_node_to_nid(struct device_node *dp) 1155 { 1156 const struct linux_prom64_registers *regs; 1157 struct mdesc_handle *md; 1158 u32 cfg_handle; 1159 int count, nid; 1160 u64 grp; 1161 1162 /* This is the right thing to do on currently supported 1163 * SUN4U NUMA platforms as well, as the PCI controller does 1164 * not sit behind any particular memory controller. 1165 */ 1166 if (!mlgroups) 1167 return -1; 1168 1169 regs = of_get_property(dp, "reg", NULL); 1170 if (!regs) 1171 return -1; 1172 1173 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; 1174 1175 md = mdesc_grab(); 1176 1177 count = 0; 1178 nid = NUMA_NO_NODE; 1179 mdesc_for_each_node_by_name(md, grp, "group") { 1180 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { 1181 nid = count; 1182 break; 1183 } 1184 count++; 1185 } 1186 1187 mdesc_release(md); 1188 1189 return nid; 1190 } 1191 1192 static void __init add_node_ranges(void) 1193 { 1194 phys_addr_t start, end; 1195 unsigned long prev_max; 1196 u64 i; 1197 1198 memblock_resized: 1199 prev_max = memblock.memory.max; 1200 1201 for_each_mem_range(i, &start, &end) { 1202 while (start < end) { 1203 unsigned long this_end; 1204 int nid; 1205 1206 this_end = memblock_nid_range(start, end, &nid); 1207 1208 numadbg("Setting memblock NUMA node nid[%d] " 1209 "start[%llx] end[%lx]\n", 1210 nid, start, this_end); 1211 1212 memblock_set_node(start, this_end - start, 1213 &memblock.memory, nid); 1214 if (memblock.memory.max != prev_max) 1215 goto memblock_resized; 1216 start = this_end; 1217 } 1218 } 1219 } 1220 1221 static int __init grab_mlgroups(struct mdesc_handle *md) 1222 { 1223 unsigned long paddr; 1224 int count = 0; 1225 u64 node; 1226 1227 mdesc_for_each_node_by_name(md, node, "memory-latency-group") 1228 count++; 1229 if (!count) 1230 return -ENOENT; 1231 1232 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup), 1233 SMP_CACHE_BYTES); 1234 if (!paddr) 1235 return -ENOMEM; 1236 1237 mlgroups = __va(paddr); 1238 num_mlgroups = count; 1239 1240 count = 0; 1241 mdesc_for_each_node_by_name(md, node, "memory-latency-group") { 1242 struct mdesc_mlgroup *m = &mlgroups[count++]; 1243 const u64 *val; 1244 1245 m->node = node; 1246 1247 val = mdesc_get_property(md, node, "latency", NULL); 1248 m->latency = *val; 1249 val = mdesc_get_property(md, node, "address-match", NULL); 1250 m->match = *val; 1251 val = mdesc_get_property(md, node, "address-mask", NULL); 1252 m->mask = *val; 1253 1254 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " 1255 "match[%llx] mask[%llx]\n", 1256 count - 1, m->node, m->latency, m->match, m->mask); 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int __init grab_mblocks(struct mdesc_handle *md) 1263 { 1264 unsigned long paddr; 1265 int count = 0; 1266 u64 node; 1267 1268 mdesc_for_each_node_by_name(md, node, "mblock") 1269 count++; 1270 if (!count) 1271 return -ENOENT; 1272 1273 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock), 1274 SMP_CACHE_BYTES); 1275 if (!paddr) 1276 return -ENOMEM; 1277 1278 mblocks = __va(paddr); 1279 num_mblocks = count; 1280 1281 count = 0; 1282 mdesc_for_each_node_by_name(md, node, "mblock") { 1283 struct mdesc_mblock *m = &mblocks[count++]; 1284 const u64 *val; 1285 1286 val = mdesc_get_property(md, node, "base", NULL); 1287 m->base = *val; 1288 val = mdesc_get_property(md, node, "size", NULL); 1289 m->size = *val; 1290 val = mdesc_get_property(md, node, 1291 "address-congruence-offset", NULL); 1292 1293 /* The address-congruence-offset property is optional. 1294 * Explicity zero it be identifty this. 1295 */ 1296 if (val) 1297 m->offset = *val; 1298 else 1299 m->offset = 0UL; 1300 1301 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", 1302 count - 1, m->base, m->size, m->offset); 1303 } 1304 1305 return 0; 1306 } 1307 1308 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, 1309 u64 grp, cpumask_t *mask) 1310 { 1311 u64 arc; 1312 1313 cpumask_clear(mask); 1314 1315 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { 1316 u64 target = mdesc_arc_target(md, arc); 1317 const char *name = mdesc_node_name(md, target); 1318 const u64 *id; 1319 1320 if (strcmp(name, "cpu")) 1321 continue; 1322 id = mdesc_get_property(md, target, "id", NULL); 1323 if (*id < nr_cpu_ids) 1324 cpumask_set_cpu(*id, mask); 1325 } 1326 } 1327 1328 static struct mdesc_mlgroup * __init find_mlgroup(u64 node) 1329 { 1330 int i; 1331 1332 for (i = 0; i < num_mlgroups; i++) { 1333 struct mdesc_mlgroup *m = &mlgroups[i]; 1334 if (m->node == node) 1335 return m; 1336 } 1337 return NULL; 1338 } 1339 1340 int __node_distance(int from, int to) 1341 { 1342 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) { 1343 pr_warn("Returning default NUMA distance value for %d->%d\n", 1344 from, to); 1345 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE; 1346 } 1347 return numa_latency[from][to]; 1348 } 1349 EXPORT_SYMBOL(__node_distance); 1350 1351 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp) 1352 { 1353 int i; 1354 1355 for (i = 0; i < MAX_NUMNODES; i++) { 1356 struct node_mem_mask *n = &node_masks[i]; 1357 1358 if ((grp->mask == n->mask) && (grp->match == n->match)) 1359 break; 1360 } 1361 return i; 1362 } 1363 1364 static void __init find_numa_latencies_for_group(struct mdesc_handle *md, 1365 u64 grp, int index) 1366 { 1367 u64 arc; 1368 1369 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1370 int tnode; 1371 u64 target = mdesc_arc_target(md, arc); 1372 struct mdesc_mlgroup *m = find_mlgroup(target); 1373 1374 if (!m) 1375 continue; 1376 tnode = find_best_numa_node_for_mlgroup(m); 1377 if (tnode == MAX_NUMNODES) 1378 continue; 1379 numa_latency[index][tnode] = m->latency; 1380 } 1381 } 1382 1383 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, 1384 int index) 1385 { 1386 struct mdesc_mlgroup *candidate = NULL; 1387 u64 arc, best_latency = ~(u64)0; 1388 struct node_mem_mask *n; 1389 1390 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1391 u64 target = mdesc_arc_target(md, arc); 1392 struct mdesc_mlgroup *m = find_mlgroup(target); 1393 if (!m) 1394 continue; 1395 if (m->latency < best_latency) { 1396 candidate = m; 1397 best_latency = m->latency; 1398 } 1399 } 1400 if (!candidate) 1401 return -ENOENT; 1402 1403 if (num_node_masks != index) { 1404 printk(KERN_ERR "Inconsistent NUMA state, " 1405 "index[%d] != num_node_masks[%d]\n", 1406 index, num_node_masks); 1407 return -EINVAL; 1408 } 1409 1410 n = &node_masks[num_node_masks++]; 1411 1412 n->mask = candidate->mask; 1413 n->match = candidate->match; 1414 1415 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n", 1416 index, n->mask, n->match, candidate->latency); 1417 1418 return 0; 1419 } 1420 1421 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, 1422 int index) 1423 { 1424 cpumask_t mask; 1425 int cpu; 1426 1427 numa_parse_mdesc_group_cpus(md, grp, &mask); 1428 1429 for_each_cpu(cpu, &mask) 1430 numa_cpu_lookup_table[cpu] = index; 1431 cpumask_copy(&numa_cpumask_lookup_table[index], &mask); 1432 1433 if (numa_debug) { 1434 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); 1435 for_each_cpu(cpu, &mask) 1436 printk("%d ", cpu); 1437 printk("]\n"); 1438 } 1439 1440 return numa_attach_mlgroup(md, grp, index); 1441 } 1442 1443 static int __init numa_parse_mdesc(void) 1444 { 1445 struct mdesc_handle *md = mdesc_grab(); 1446 int i, j, err, count; 1447 u64 node; 1448 1449 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); 1450 if (node == MDESC_NODE_NULL) { 1451 mdesc_release(md); 1452 return -ENOENT; 1453 } 1454 1455 err = grab_mblocks(md); 1456 if (err < 0) 1457 goto out; 1458 1459 err = grab_mlgroups(md); 1460 if (err < 0) 1461 goto out; 1462 1463 count = 0; 1464 mdesc_for_each_node_by_name(md, node, "group") { 1465 err = numa_parse_mdesc_group(md, node, count); 1466 if (err < 0) 1467 break; 1468 count++; 1469 } 1470 1471 count = 0; 1472 mdesc_for_each_node_by_name(md, node, "group") { 1473 find_numa_latencies_for_group(md, node, count); 1474 count++; 1475 } 1476 1477 /* Normalize numa latency matrix according to ACPI SLIT spec. */ 1478 for (i = 0; i < MAX_NUMNODES; i++) { 1479 u64 self_latency = numa_latency[i][i]; 1480 1481 for (j = 0; j < MAX_NUMNODES; j++) { 1482 numa_latency[i][j] = 1483 (numa_latency[i][j] * LOCAL_DISTANCE) / 1484 self_latency; 1485 } 1486 } 1487 1488 add_node_ranges(); 1489 1490 for (i = 0; i < num_node_masks; i++) { 1491 allocate_node_data(i); 1492 node_set_online(i); 1493 } 1494 1495 err = 0; 1496 out: 1497 mdesc_release(md); 1498 return err; 1499 } 1500 1501 static int __init numa_parse_jbus(void) 1502 { 1503 unsigned long cpu, index; 1504 1505 /* NUMA node id is encoded in bits 36 and higher, and there is 1506 * a 1-to-1 mapping from CPU ID to NUMA node ID. 1507 */ 1508 index = 0; 1509 for_each_present_cpu(cpu) { 1510 numa_cpu_lookup_table[cpu] = index; 1511 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); 1512 node_masks[index].mask = ~((1UL << 36UL) - 1UL); 1513 node_masks[index].match = cpu << 36UL; 1514 1515 index++; 1516 } 1517 num_node_masks = index; 1518 1519 add_node_ranges(); 1520 1521 for (index = 0; index < num_node_masks; index++) { 1522 allocate_node_data(index); 1523 node_set_online(index); 1524 } 1525 1526 return 0; 1527 } 1528 1529 static int __init numa_parse_sun4u(void) 1530 { 1531 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1532 unsigned long ver; 1533 1534 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 1535 if ((ver >> 32UL) == __JALAPENO_ID || 1536 (ver >> 32UL) == __SERRANO_ID) 1537 return numa_parse_jbus(); 1538 } 1539 return -1; 1540 } 1541 1542 static int __init bootmem_init_numa(void) 1543 { 1544 int i, j; 1545 int err = -1; 1546 1547 numadbg("bootmem_init_numa()\n"); 1548 1549 /* Some sane defaults for numa latency values */ 1550 for (i = 0; i < MAX_NUMNODES; i++) { 1551 for (j = 0; j < MAX_NUMNODES; j++) 1552 numa_latency[i][j] = (i == j) ? 1553 LOCAL_DISTANCE : REMOTE_DISTANCE; 1554 } 1555 1556 if (numa_enabled) { 1557 if (tlb_type == hypervisor) 1558 err = numa_parse_mdesc(); 1559 else 1560 err = numa_parse_sun4u(); 1561 } 1562 return err; 1563 } 1564 1565 #else 1566 1567 static int bootmem_init_numa(void) 1568 { 1569 return -1; 1570 } 1571 1572 #endif 1573 1574 static void __init bootmem_init_nonnuma(void) 1575 { 1576 unsigned long top_of_ram = memblock_end_of_DRAM(); 1577 unsigned long total_ram = memblock_phys_mem_size(); 1578 1579 numadbg("bootmem_init_nonnuma()\n"); 1580 1581 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", 1582 top_of_ram, total_ram); 1583 printk(KERN_INFO "Memory hole size: %ldMB\n", 1584 (top_of_ram - total_ram) >> 20); 1585 1586 init_node_masks_nonnuma(); 1587 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0); 1588 allocate_node_data(0); 1589 node_set_online(0); 1590 } 1591 1592 static unsigned long __init bootmem_init(unsigned long phys_base) 1593 { 1594 unsigned long end_pfn; 1595 1596 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; 1597 max_pfn = max_low_pfn = end_pfn; 1598 min_low_pfn = (phys_base >> PAGE_SHIFT); 1599 1600 if (bootmem_init_numa() < 0) 1601 bootmem_init_nonnuma(); 1602 1603 /* Dump memblock with node info. */ 1604 memblock_dump_all(); 1605 1606 /* XXX cpu notifier XXX */ 1607 1608 return end_pfn; 1609 } 1610 1611 static struct linux_prom64_registers pall[MAX_BANKS] __initdata; 1612 static int pall_ents __initdata; 1613 1614 static unsigned long max_phys_bits = 40; 1615 1616 bool kern_addr_valid(unsigned long addr) 1617 { 1618 pgd_t *pgd; 1619 p4d_t *p4d; 1620 pud_t *pud; 1621 pmd_t *pmd; 1622 pte_t *pte; 1623 1624 if ((long)addr < 0L) { 1625 unsigned long pa = __pa(addr); 1626 1627 if ((pa >> max_phys_bits) != 0UL) 1628 return false; 1629 1630 return pfn_valid(pa >> PAGE_SHIFT); 1631 } 1632 1633 if (addr >= (unsigned long) KERNBASE && 1634 addr < (unsigned long)&_end) 1635 return true; 1636 1637 pgd = pgd_offset_k(addr); 1638 if (pgd_none(*pgd)) 1639 return false; 1640 1641 p4d = p4d_offset(pgd, addr); 1642 if (p4d_none(*p4d)) 1643 return false; 1644 1645 pud = pud_offset(p4d, addr); 1646 if (pud_none(*pud)) 1647 return false; 1648 1649 if (pud_leaf(*pud)) 1650 return pfn_valid(pud_pfn(*pud)); 1651 1652 pmd = pmd_offset(pud, addr); 1653 if (pmd_none(*pmd)) 1654 return false; 1655 1656 if (pmd_leaf(*pmd)) 1657 return pfn_valid(pmd_pfn(*pmd)); 1658 1659 pte = pte_offset_kernel(pmd, addr); 1660 if (pte_none(*pte)) 1661 return false; 1662 1663 return pfn_valid(pte_pfn(*pte)); 1664 } 1665 1666 static unsigned long __ref kernel_map_hugepud(unsigned long vstart, 1667 unsigned long vend, 1668 pud_t *pud) 1669 { 1670 const unsigned long mask16gb = (1UL << 34) - 1UL; 1671 u64 pte_val = vstart; 1672 1673 /* Each PUD is 8GB */ 1674 if ((vstart & mask16gb) || 1675 (vend - vstart <= mask16gb)) { 1676 pte_val ^= kern_linear_pte_xor[2]; 1677 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE; 1678 1679 return vstart + PUD_SIZE; 1680 } 1681 1682 pte_val ^= kern_linear_pte_xor[3]; 1683 pte_val |= _PAGE_PUD_HUGE; 1684 1685 vend = vstart + mask16gb + 1UL; 1686 while (vstart < vend) { 1687 pud_val(*pud) = pte_val; 1688 1689 pte_val += PUD_SIZE; 1690 vstart += PUD_SIZE; 1691 pud++; 1692 } 1693 return vstart; 1694 } 1695 1696 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend, 1697 bool guard) 1698 { 1699 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE) 1700 return true; 1701 1702 return false; 1703 } 1704 1705 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart, 1706 unsigned long vend, 1707 pmd_t *pmd) 1708 { 1709 const unsigned long mask256mb = (1UL << 28) - 1UL; 1710 const unsigned long mask2gb = (1UL << 31) - 1UL; 1711 u64 pte_val = vstart; 1712 1713 /* Each PMD is 8MB */ 1714 if ((vstart & mask256mb) || 1715 (vend - vstart <= mask256mb)) { 1716 pte_val ^= kern_linear_pte_xor[0]; 1717 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE; 1718 1719 return vstart + PMD_SIZE; 1720 } 1721 1722 if ((vstart & mask2gb) || 1723 (vend - vstart <= mask2gb)) { 1724 pte_val ^= kern_linear_pte_xor[1]; 1725 pte_val |= _PAGE_PMD_HUGE; 1726 vend = vstart + mask256mb + 1UL; 1727 } else { 1728 pte_val ^= kern_linear_pte_xor[2]; 1729 pte_val |= _PAGE_PMD_HUGE; 1730 vend = vstart + mask2gb + 1UL; 1731 } 1732 1733 while (vstart < vend) { 1734 pmd_val(*pmd) = pte_val; 1735 1736 pte_val += PMD_SIZE; 1737 vstart += PMD_SIZE; 1738 pmd++; 1739 } 1740 1741 return vstart; 1742 } 1743 1744 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend, 1745 bool guard) 1746 { 1747 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE) 1748 return true; 1749 1750 return false; 1751 } 1752 1753 static unsigned long __ref kernel_map_range(unsigned long pstart, 1754 unsigned long pend, pgprot_t prot, 1755 bool use_huge) 1756 { 1757 unsigned long vstart = PAGE_OFFSET + pstart; 1758 unsigned long vend = PAGE_OFFSET + pend; 1759 unsigned long alloc_bytes = 0UL; 1760 1761 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { 1762 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", 1763 vstart, vend); 1764 prom_halt(); 1765 } 1766 1767 while (vstart < vend) { 1768 unsigned long this_end, paddr = __pa(vstart); 1769 pgd_t *pgd = pgd_offset_k(vstart); 1770 p4d_t *p4d; 1771 pud_t *pud; 1772 pmd_t *pmd; 1773 pte_t *pte; 1774 1775 if (pgd_none(*pgd)) { 1776 pud_t *new; 1777 1778 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1779 PAGE_SIZE); 1780 if (!new) 1781 goto err_alloc; 1782 alloc_bytes += PAGE_SIZE; 1783 pgd_populate(&init_mm, pgd, new); 1784 } 1785 1786 p4d = p4d_offset(pgd, vstart); 1787 if (p4d_none(*p4d)) { 1788 pud_t *new; 1789 1790 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1791 PAGE_SIZE); 1792 if (!new) 1793 goto err_alloc; 1794 alloc_bytes += PAGE_SIZE; 1795 p4d_populate(&init_mm, p4d, new); 1796 } 1797 1798 pud = pud_offset(p4d, vstart); 1799 if (pud_none(*pud)) { 1800 pmd_t *new; 1801 1802 if (kernel_can_map_hugepud(vstart, vend, use_huge)) { 1803 vstart = kernel_map_hugepud(vstart, vend, pud); 1804 continue; 1805 } 1806 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1807 PAGE_SIZE); 1808 if (!new) 1809 goto err_alloc; 1810 alloc_bytes += PAGE_SIZE; 1811 pud_populate(&init_mm, pud, new); 1812 } 1813 1814 pmd = pmd_offset(pud, vstart); 1815 if (pmd_none(*pmd)) { 1816 pte_t *new; 1817 1818 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) { 1819 vstart = kernel_map_hugepmd(vstart, vend, pmd); 1820 continue; 1821 } 1822 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1823 PAGE_SIZE); 1824 if (!new) 1825 goto err_alloc; 1826 alloc_bytes += PAGE_SIZE; 1827 pmd_populate_kernel(&init_mm, pmd, new); 1828 } 1829 1830 pte = pte_offset_kernel(pmd, vstart); 1831 this_end = (vstart + PMD_SIZE) & PMD_MASK; 1832 if (this_end > vend) 1833 this_end = vend; 1834 1835 while (vstart < this_end) { 1836 pte_val(*pte) = (paddr | pgprot_val(prot)); 1837 1838 vstart += PAGE_SIZE; 1839 paddr += PAGE_SIZE; 1840 pte++; 1841 } 1842 } 1843 1844 return alloc_bytes; 1845 1846 err_alloc: 1847 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n", 1848 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1849 return -ENOMEM; 1850 } 1851 1852 static void __init flush_all_kernel_tsbs(void) 1853 { 1854 int i; 1855 1856 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) { 1857 struct tsb *ent = &swapper_tsb[i]; 1858 1859 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1860 } 1861 #ifndef CONFIG_DEBUG_PAGEALLOC 1862 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) { 1863 struct tsb *ent = &swapper_4m_tsb[i]; 1864 1865 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1866 } 1867 #endif 1868 } 1869 1870 extern unsigned int kvmap_linear_patch[1]; 1871 1872 static void __init kernel_physical_mapping_init(void) 1873 { 1874 unsigned long i, mem_alloced = 0UL; 1875 bool use_huge = true; 1876 1877 #ifdef CONFIG_DEBUG_PAGEALLOC 1878 use_huge = false; 1879 #endif 1880 for (i = 0; i < pall_ents; i++) { 1881 unsigned long phys_start, phys_end; 1882 1883 phys_start = pall[i].phys_addr; 1884 phys_end = phys_start + pall[i].reg_size; 1885 1886 mem_alloced += kernel_map_range(phys_start, phys_end, 1887 PAGE_KERNEL, use_huge); 1888 } 1889 1890 printk("Allocated %ld bytes for kernel page tables.\n", 1891 mem_alloced); 1892 1893 kvmap_linear_patch[0] = 0x01000000; /* nop */ 1894 flushi(&kvmap_linear_patch[0]); 1895 1896 flush_all_kernel_tsbs(); 1897 1898 __flush_tlb_all(); 1899 } 1900 1901 #ifdef CONFIG_DEBUG_PAGEALLOC 1902 void __kernel_map_pages(struct page *page, int numpages, int enable) 1903 { 1904 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; 1905 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); 1906 1907 kernel_map_range(phys_start, phys_end, 1908 (enable ? PAGE_KERNEL : __pgprot(0)), false); 1909 1910 flush_tsb_kernel_range(PAGE_OFFSET + phys_start, 1911 PAGE_OFFSET + phys_end); 1912 1913 /* we should perform an IPI and flush all tlbs, 1914 * but that can deadlock->flush only current cpu. 1915 */ 1916 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, 1917 PAGE_OFFSET + phys_end); 1918 } 1919 #endif 1920 1921 unsigned long __init find_ecache_flush_span(unsigned long size) 1922 { 1923 int i; 1924 1925 for (i = 0; i < pavail_ents; i++) { 1926 if (pavail[i].reg_size >= size) 1927 return pavail[i].phys_addr; 1928 } 1929 1930 return ~0UL; 1931 } 1932 1933 unsigned long PAGE_OFFSET; 1934 EXPORT_SYMBOL(PAGE_OFFSET); 1935 1936 unsigned long VMALLOC_END = 0x0000010000000000UL; 1937 EXPORT_SYMBOL(VMALLOC_END); 1938 1939 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; 1940 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; 1941 1942 static void __init setup_page_offset(void) 1943 { 1944 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1945 /* Cheetah/Panther support a full 64-bit virtual 1946 * address, so we can use all that our page tables 1947 * support. 1948 */ 1949 sparc64_va_hole_top = 0xfff0000000000000UL; 1950 sparc64_va_hole_bottom = 0x0010000000000000UL; 1951 1952 max_phys_bits = 42; 1953 } else if (tlb_type == hypervisor) { 1954 switch (sun4v_chip_type) { 1955 case SUN4V_CHIP_NIAGARA1: 1956 case SUN4V_CHIP_NIAGARA2: 1957 /* T1 and T2 support 48-bit virtual addresses. */ 1958 sparc64_va_hole_top = 0xffff800000000000UL; 1959 sparc64_va_hole_bottom = 0x0000800000000000UL; 1960 1961 max_phys_bits = 39; 1962 break; 1963 case SUN4V_CHIP_NIAGARA3: 1964 /* T3 supports 48-bit virtual addresses. */ 1965 sparc64_va_hole_top = 0xffff800000000000UL; 1966 sparc64_va_hole_bottom = 0x0000800000000000UL; 1967 1968 max_phys_bits = 43; 1969 break; 1970 case SUN4V_CHIP_NIAGARA4: 1971 case SUN4V_CHIP_NIAGARA5: 1972 case SUN4V_CHIP_SPARC64X: 1973 case SUN4V_CHIP_SPARC_M6: 1974 /* T4 and later support 52-bit virtual addresses. */ 1975 sparc64_va_hole_top = 0xfff8000000000000UL; 1976 sparc64_va_hole_bottom = 0x0008000000000000UL; 1977 max_phys_bits = 47; 1978 break; 1979 case SUN4V_CHIP_SPARC_M7: 1980 case SUN4V_CHIP_SPARC_SN: 1981 /* M7 and later support 52-bit virtual addresses. */ 1982 sparc64_va_hole_top = 0xfff8000000000000UL; 1983 sparc64_va_hole_bottom = 0x0008000000000000UL; 1984 max_phys_bits = 49; 1985 break; 1986 case SUN4V_CHIP_SPARC_M8: 1987 default: 1988 /* M8 and later support 54-bit virtual addresses. 1989 * However, restricting M8 and above VA bits to 53 1990 * as 4-level page table cannot support more than 1991 * 53 VA bits. 1992 */ 1993 sparc64_va_hole_top = 0xfff0000000000000UL; 1994 sparc64_va_hole_bottom = 0x0010000000000000UL; 1995 max_phys_bits = 51; 1996 break; 1997 } 1998 } 1999 2000 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { 2001 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", 2002 max_phys_bits); 2003 prom_halt(); 2004 } 2005 2006 PAGE_OFFSET = sparc64_va_hole_top; 2007 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) + 2008 (sparc64_va_hole_bottom >> 2)); 2009 2010 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", 2011 PAGE_OFFSET, max_phys_bits); 2012 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n", 2013 VMALLOC_START, VMALLOC_END); 2014 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n", 2015 VMEMMAP_BASE, VMEMMAP_BASE << 1); 2016 } 2017 2018 static void __init tsb_phys_patch(void) 2019 { 2020 struct tsb_ldquad_phys_patch_entry *pquad; 2021 struct tsb_phys_patch_entry *p; 2022 2023 pquad = &__tsb_ldquad_phys_patch; 2024 while (pquad < &__tsb_ldquad_phys_patch_end) { 2025 unsigned long addr = pquad->addr; 2026 2027 if (tlb_type == hypervisor) 2028 *(unsigned int *) addr = pquad->sun4v_insn; 2029 else 2030 *(unsigned int *) addr = pquad->sun4u_insn; 2031 wmb(); 2032 __asm__ __volatile__("flush %0" 2033 : /* no outputs */ 2034 : "r" (addr)); 2035 2036 pquad++; 2037 } 2038 2039 p = &__tsb_phys_patch; 2040 while (p < &__tsb_phys_patch_end) { 2041 unsigned long addr = p->addr; 2042 2043 *(unsigned int *) addr = p->insn; 2044 wmb(); 2045 __asm__ __volatile__("flush %0" 2046 : /* no outputs */ 2047 : "r" (addr)); 2048 2049 p++; 2050 } 2051 } 2052 2053 /* Don't mark as init, we give this to the Hypervisor. */ 2054 #ifndef CONFIG_DEBUG_PAGEALLOC 2055 #define NUM_KTSB_DESCR 2 2056 #else 2057 #define NUM_KTSB_DESCR 1 2058 #endif 2059 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; 2060 2061 /* The swapper TSBs are loaded with a base sequence of: 2062 * 2063 * sethi %uhi(SYMBOL), REG1 2064 * sethi %hi(SYMBOL), REG2 2065 * or REG1, %ulo(SYMBOL), REG1 2066 * or REG2, %lo(SYMBOL), REG2 2067 * sllx REG1, 32, REG1 2068 * or REG1, REG2, REG1 2069 * 2070 * When we use physical addressing for the TSB accesses, we patch the 2071 * first four instructions in the above sequence. 2072 */ 2073 2074 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) 2075 { 2076 unsigned long high_bits, low_bits; 2077 2078 high_bits = (pa >> 32) & 0xffffffff; 2079 low_bits = (pa >> 0) & 0xffffffff; 2080 2081 while (start < end) { 2082 unsigned int *ia = (unsigned int *)(unsigned long)*start; 2083 2084 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10); 2085 __asm__ __volatile__("flush %0" : : "r" (ia)); 2086 2087 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10); 2088 __asm__ __volatile__("flush %0" : : "r" (ia + 1)); 2089 2090 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff); 2091 __asm__ __volatile__("flush %0" : : "r" (ia + 2)); 2092 2093 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff); 2094 __asm__ __volatile__("flush %0" : : "r" (ia + 3)); 2095 2096 start++; 2097 } 2098 } 2099 2100 static void ktsb_phys_patch(void) 2101 { 2102 extern unsigned int __swapper_tsb_phys_patch; 2103 extern unsigned int __swapper_tsb_phys_patch_end; 2104 unsigned long ktsb_pa; 2105 2106 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2107 patch_one_ktsb_phys(&__swapper_tsb_phys_patch, 2108 &__swapper_tsb_phys_patch_end, ktsb_pa); 2109 #ifndef CONFIG_DEBUG_PAGEALLOC 2110 { 2111 extern unsigned int __swapper_4m_tsb_phys_patch; 2112 extern unsigned int __swapper_4m_tsb_phys_patch_end; 2113 ktsb_pa = (kern_base + 2114 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2115 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, 2116 &__swapper_4m_tsb_phys_patch_end, ktsb_pa); 2117 } 2118 #endif 2119 } 2120 2121 static void __init sun4v_ktsb_init(void) 2122 { 2123 unsigned long ktsb_pa; 2124 2125 /* First KTSB for PAGE_SIZE mappings. */ 2126 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2127 2128 switch (PAGE_SIZE) { 2129 case 8 * 1024: 2130 default: 2131 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; 2132 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; 2133 break; 2134 2135 case 64 * 1024: 2136 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; 2137 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; 2138 break; 2139 2140 case 512 * 1024: 2141 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; 2142 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; 2143 break; 2144 2145 case 4 * 1024 * 1024: 2146 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; 2147 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; 2148 break; 2149 } 2150 2151 ktsb_descr[0].assoc = 1; 2152 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; 2153 ktsb_descr[0].ctx_idx = 0; 2154 ktsb_descr[0].tsb_base = ktsb_pa; 2155 ktsb_descr[0].resv = 0; 2156 2157 #ifndef CONFIG_DEBUG_PAGEALLOC 2158 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ 2159 ktsb_pa = (kern_base + 2160 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2161 2162 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; 2163 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | 2164 HV_PGSZ_MASK_256MB | 2165 HV_PGSZ_MASK_2GB | 2166 HV_PGSZ_MASK_16GB) & 2167 cpu_pgsz_mask); 2168 ktsb_descr[1].assoc = 1; 2169 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; 2170 ktsb_descr[1].ctx_idx = 0; 2171 ktsb_descr[1].tsb_base = ktsb_pa; 2172 ktsb_descr[1].resv = 0; 2173 #endif 2174 } 2175 2176 void sun4v_ktsb_register(void) 2177 { 2178 unsigned long pa, ret; 2179 2180 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); 2181 2182 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); 2183 if (ret != 0) { 2184 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " 2185 "errors with %lx\n", pa, ret); 2186 prom_halt(); 2187 } 2188 } 2189 2190 static void __init sun4u_linear_pte_xor_finalize(void) 2191 { 2192 #ifndef CONFIG_DEBUG_PAGEALLOC 2193 /* This is where we would add Panther support for 2194 * 32MB and 256MB pages. 2195 */ 2196 #endif 2197 } 2198 2199 static void __init sun4v_linear_pte_xor_finalize(void) 2200 { 2201 unsigned long pagecv_flag; 2202 2203 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead 2204 * enables MCD error. Do not set bit 9 on M7 processor. 2205 */ 2206 switch (sun4v_chip_type) { 2207 case SUN4V_CHIP_SPARC_M7: 2208 case SUN4V_CHIP_SPARC_M8: 2209 case SUN4V_CHIP_SPARC_SN: 2210 pagecv_flag = 0x00; 2211 break; 2212 default: 2213 pagecv_flag = _PAGE_CV_4V; 2214 break; 2215 } 2216 #ifndef CONFIG_DEBUG_PAGEALLOC 2217 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { 2218 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ 2219 PAGE_OFFSET; 2220 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag | 2221 _PAGE_P_4V | _PAGE_W_4V); 2222 } else { 2223 kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; 2224 } 2225 2226 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { 2227 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ 2228 PAGE_OFFSET; 2229 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag | 2230 _PAGE_P_4V | _PAGE_W_4V); 2231 } else { 2232 kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; 2233 } 2234 2235 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { 2236 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ 2237 PAGE_OFFSET; 2238 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag | 2239 _PAGE_P_4V | _PAGE_W_4V); 2240 } else { 2241 kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; 2242 } 2243 #endif 2244 } 2245 2246 /* paging_init() sets up the page tables */ 2247 2248 static unsigned long last_valid_pfn; 2249 2250 static void sun4u_pgprot_init(void); 2251 static void sun4v_pgprot_init(void); 2252 2253 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) 2254 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) 2255 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) 2256 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) 2257 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) 2258 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) 2259 2260 /* We need to exclude reserved regions. This exclusion will include 2261 * vmlinux and initrd. To be more precise the initrd size could be used to 2262 * compute a new lower limit because it is freed later during initialization. 2263 */ 2264 static void __init reduce_memory(phys_addr_t limit_ram) 2265 { 2266 limit_ram += memblock_reserved_size(); 2267 memblock_enforce_memory_limit(limit_ram); 2268 } 2269 2270 void __init arch_zone_limits_init(unsigned long *max_zone_pfns) 2271 { 2272 max_zone_pfns[ZONE_NORMAL] = last_valid_pfn; 2273 } 2274 2275 void __init paging_init(void) 2276 { 2277 unsigned long end_pfn, shift, phys_base; 2278 unsigned long real_end, i; 2279 2280 setup_page_offset(); 2281 2282 /* These build time checkes make sure that the dcache_dirty_cpu() 2283 * folio->flags usage will work. 2284 * 2285 * When a page gets marked as dcache-dirty, we store the 2286 * cpu number starting at bit 32 in the folio->flags. Also, 2287 * functions like clear_dcache_dirty_cpu use the cpu mask 2288 * in 13-bit signed-immediate instruction fields. 2289 */ 2290 2291 /* 2292 * Page flags must not reach into upper 32 bits that are used 2293 * for the cpu number 2294 */ 2295 BUILD_BUG_ON(NR_PAGEFLAGS > 32); 2296 2297 /* 2298 * The bit fields placed in the high range must not reach below 2299 * the 32 bit boundary. Otherwise we cannot place the cpu field 2300 * at the 32 bit boundary. 2301 */ 2302 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + 2303 ilog2(roundup_pow_of_two(NR_CPUS)) > 32); 2304 2305 BUILD_BUG_ON(NR_CPUS > 4096); 2306 2307 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 2308 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 2309 2310 /* Invalidate both kernel TSBs. */ 2311 memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); 2312 #ifndef CONFIG_DEBUG_PAGEALLOC 2313 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2314 #endif 2315 2316 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde 2317 * bit on M7 processor. This is a conflicting usage of the same 2318 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption 2319 * Detection error on all pages and this will lead to problems 2320 * later. Kernel does not run with MCD enabled and hence rest 2321 * of the required steps to fully configure memory corruption 2322 * detection are not taken. We need to ensure TTE.mcde is not 2323 * set on M7 processor. Compute the value of cacheability 2324 * flag for use later taking this into consideration. 2325 */ 2326 switch (sun4v_chip_type) { 2327 case SUN4V_CHIP_SPARC_M7: 2328 case SUN4V_CHIP_SPARC_M8: 2329 case SUN4V_CHIP_SPARC_SN: 2330 page_cache4v_flag = _PAGE_CP_4V; 2331 break; 2332 default: 2333 page_cache4v_flag = _PAGE_CACHE_4V; 2334 break; 2335 } 2336 2337 if (tlb_type == hypervisor) 2338 sun4v_pgprot_init(); 2339 else 2340 sun4u_pgprot_init(); 2341 2342 if (tlb_type == cheetah_plus || 2343 tlb_type == hypervisor) { 2344 tsb_phys_patch(); 2345 ktsb_phys_patch(); 2346 } 2347 2348 if (tlb_type == hypervisor) 2349 sun4v_patch_tlb_handlers(); 2350 2351 /* Find available physical memory... 2352 * 2353 * Read it twice in order to work around a bug in openfirmware. 2354 * The call to grab this table itself can cause openfirmware to 2355 * allocate memory, which in turn can take away some space from 2356 * the list of available memory. Reading it twice makes sure 2357 * we really do get the final value. 2358 */ 2359 read_obp_translations(); 2360 read_obp_memory("reg", &pall[0], &pall_ents); 2361 read_obp_memory("available", &pavail[0], &pavail_ents); 2362 read_obp_memory("available", &pavail[0], &pavail_ents); 2363 2364 phys_base = 0xffffffffffffffffUL; 2365 for (i = 0; i < pavail_ents; i++) { 2366 phys_base = min(phys_base, pavail[i].phys_addr); 2367 memblock_add(pavail[i].phys_addr, pavail[i].reg_size); 2368 } 2369 2370 memblock_reserve(kern_base, kern_size); 2371 2372 find_ramdisk(phys_base); 2373 2374 if (cmdline_memory_size) 2375 reduce_memory(cmdline_memory_size); 2376 2377 memblock_allow_resize(); 2378 memblock_dump_all(); 2379 2380 set_bit(0, mmu_context_bmap); 2381 2382 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); 2383 2384 real_end = (unsigned long)_end; 2385 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); 2386 printk("Kernel: Using %d locked TLB entries for main kernel image.\n", 2387 num_kernel_image_mappings); 2388 2389 /* Set kernel pgd to upper alias so physical page computations 2390 * work. 2391 */ 2392 init_mm.pgd += ((shift) / (sizeof(pgd_t))); 2393 2394 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); 2395 2396 inherit_prom_mappings(); 2397 2398 /* Ok, we can use our TLB miss and window trap handlers safely. */ 2399 setup_tba(); 2400 2401 __flush_tlb_all(); 2402 2403 prom_build_devicetree(); 2404 of_populate_present_mask(); 2405 #ifndef CONFIG_SMP 2406 of_fill_in_cpu_data(); 2407 #endif 2408 2409 if (tlb_type == hypervisor) { 2410 sun4v_mdesc_init(); 2411 mdesc_populate_present_mask(cpu_all_mask); 2412 #ifndef CONFIG_SMP 2413 mdesc_fill_in_cpu_data(cpu_all_mask); 2414 #endif 2415 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); 2416 2417 sun4v_linear_pte_xor_finalize(); 2418 2419 sun4v_ktsb_init(); 2420 sun4v_ktsb_register(); 2421 } else { 2422 unsigned long impl, ver; 2423 2424 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | 2425 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); 2426 2427 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 2428 impl = ((ver >> 32) & 0xffff); 2429 if (impl == PANTHER_IMPL) 2430 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | 2431 HV_PGSZ_MASK_256MB); 2432 2433 sun4u_linear_pte_xor_finalize(); 2434 } 2435 2436 /* Flush the TLBs and the 4M TSB so that the updated linear 2437 * pte XOR settings are realized for all mappings. 2438 */ 2439 __flush_tlb_all(); 2440 #ifndef CONFIG_DEBUG_PAGEALLOC 2441 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2442 #endif 2443 __flush_tlb_all(); 2444 2445 /* Setup bootmem... */ 2446 last_valid_pfn = end_pfn = bootmem_init(phys_base); 2447 2448 kernel_physical_mapping_init(); 2449 2450 printk("Booting Linux...\n"); 2451 } 2452 2453 int page_in_phys_avail(unsigned long paddr) 2454 { 2455 int i; 2456 2457 paddr &= PAGE_MASK; 2458 2459 for (i = 0; i < pavail_ents; i++) { 2460 unsigned long start, end; 2461 2462 start = pavail[i].phys_addr; 2463 end = start + pavail[i].reg_size; 2464 2465 if (paddr >= start && paddr < end) 2466 return 1; 2467 } 2468 if (paddr >= kern_base && paddr < (kern_base + kern_size)) 2469 return 1; 2470 #ifdef CONFIG_BLK_DEV_INITRD 2471 if (paddr >= __pa(initrd_start) && 2472 paddr < __pa(PAGE_ALIGN(initrd_end))) 2473 return 1; 2474 #endif 2475 2476 return 0; 2477 } 2478 2479 void __init arch_setup_zero_pages(void) 2480 { 2481 phys_addr_t zero_page_pa = kern_base + 2482 ((unsigned long)&empty_zero_page[0] - KERNBASE); 2483 2484 __zero_page = phys_to_page(zero_page_pa); 2485 } 2486 2487 void __init mem_init(void) 2488 { 2489 if (tlb_type == cheetah || tlb_type == cheetah_plus) 2490 cheetah_ecache_flush_init(); 2491 } 2492 2493 void free_initmem(void) 2494 { 2495 unsigned long addr, initend; 2496 int do_free = 1; 2497 2498 /* If the physical memory maps were trimmed by kernel command 2499 * line options, don't even try freeing this initmem stuff up. 2500 * The kernel image could have been in the trimmed out region 2501 * and if so the freeing below will free invalid page structs. 2502 */ 2503 if (cmdline_memory_size) 2504 do_free = 0; 2505 2506 /* 2507 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. 2508 */ 2509 addr = PAGE_ALIGN((unsigned long)(__init_begin)); 2510 initend = (unsigned long)(__init_end) & PAGE_MASK; 2511 for (; addr < initend; addr += PAGE_SIZE) { 2512 unsigned long page; 2513 2514 page = (addr + 2515 ((unsigned long) __va(kern_base)) - 2516 ((unsigned long) KERNBASE)); 2517 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); 2518 2519 if (do_free) 2520 free_reserved_page(virt_to_page(page)); 2521 } 2522 } 2523 2524 pgprot_t PAGE_KERNEL __read_mostly; 2525 EXPORT_SYMBOL(PAGE_KERNEL); 2526 2527 pgprot_t PAGE_KERNEL_LOCKED __read_mostly; 2528 pgprot_t PAGE_COPY __read_mostly; 2529 2530 pgprot_t PAGE_SHARED __read_mostly; 2531 EXPORT_SYMBOL(PAGE_SHARED); 2532 2533 unsigned long pg_iobits __read_mostly; 2534 2535 unsigned long _PAGE_IE __read_mostly; 2536 EXPORT_SYMBOL(_PAGE_IE); 2537 2538 unsigned long _PAGE_E __read_mostly; 2539 EXPORT_SYMBOL(_PAGE_E); 2540 2541 unsigned long _PAGE_CACHE __read_mostly; 2542 EXPORT_SYMBOL(_PAGE_CACHE); 2543 2544 #ifdef CONFIG_SPARSEMEM_VMEMMAP 2545 void __meminit vmemmap_set_pmd(pmd_t *pmd, void *p, int node, 2546 unsigned long addr, unsigned long next) 2547 { 2548 unsigned long pte_base; 2549 2550 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2551 _PAGE_CP_4U | _PAGE_CV_4U | 2552 _PAGE_P_4U | _PAGE_W_4U); 2553 if (tlb_type == hypervisor) 2554 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2555 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V); 2556 2557 pte_base |= _PAGE_PMD_HUGE; 2558 2559 pmd_val(*pmd) = pte_base | __pa(p); 2560 } 2561 2562 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, 2563 int node, struct vmem_altmap *altmap) 2564 { 2565 return vmemmap_populate_hugepages(vstart, vend, node, NULL); 2566 } 2567 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 2568 2569 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 2570 static pgprot_t protection_map[16] __ro_after_init; 2571 2572 static void prot_init_common(unsigned long page_none, 2573 unsigned long page_shared, 2574 unsigned long page_copy, 2575 unsigned long page_readonly, 2576 unsigned long page_exec_bit) 2577 { 2578 PAGE_COPY = __pgprot(page_copy); 2579 PAGE_SHARED = __pgprot(page_shared); 2580 2581 protection_map[0x0] = __pgprot(page_none); 2582 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); 2583 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); 2584 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); 2585 protection_map[0x4] = __pgprot(page_readonly); 2586 protection_map[0x5] = __pgprot(page_readonly); 2587 protection_map[0x6] = __pgprot(page_copy); 2588 protection_map[0x7] = __pgprot(page_copy); 2589 protection_map[0x8] = __pgprot(page_none); 2590 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); 2591 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); 2592 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); 2593 protection_map[0xc] = __pgprot(page_readonly); 2594 protection_map[0xd] = __pgprot(page_readonly); 2595 protection_map[0xe] = __pgprot(page_shared); 2596 protection_map[0xf] = __pgprot(page_shared); 2597 } 2598 2599 static void __init sun4u_pgprot_init(void) 2600 { 2601 unsigned long page_none, page_shared, page_copy, page_readonly; 2602 unsigned long page_exec_bit; 2603 int i; 2604 2605 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2606 _PAGE_CACHE_4U | _PAGE_P_4U | 2607 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2608 _PAGE_EXEC_4U); 2609 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2610 _PAGE_CACHE_4U | _PAGE_P_4U | 2611 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2612 _PAGE_EXEC_4U | _PAGE_L_4U); 2613 2614 _PAGE_IE = _PAGE_IE_4U; 2615 _PAGE_E = _PAGE_E_4U; 2616 _PAGE_CACHE = _PAGE_CACHE_4U; 2617 2618 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | 2619 __ACCESS_BITS_4U | _PAGE_E_4U); 2620 2621 #ifdef CONFIG_DEBUG_PAGEALLOC 2622 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2623 #else 2624 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ 2625 PAGE_OFFSET; 2626 #endif 2627 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | 2628 _PAGE_P_4U | _PAGE_W_4U); 2629 2630 for (i = 1; i < 4; i++) 2631 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2632 2633 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | 2634 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | 2635 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); 2636 2637 2638 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; 2639 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2640 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); 2641 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2642 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2643 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2644 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2645 2646 page_exec_bit = _PAGE_EXEC_4U; 2647 2648 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2649 page_exec_bit); 2650 } 2651 2652 static void __init sun4v_pgprot_init(void) 2653 { 2654 unsigned long page_none, page_shared, page_copy, page_readonly; 2655 unsigned long page_exec_bit; 2656 int i; 2657 2658 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | 2659 page_cache4v_flag | _PAGE_P_4V | 2660 __ACCESS_BITS_4V | __DIRTY_BITS_4V | 2661 _PAGE_EXEC_4V); 2662 PAGE_KERNEL_LOCKED = PAGE_KERNEL; 2663 2664 _PAGE_IE = _PAGE_IE_4V; 2665 _PAGE_E = _PAGE_E_4V; 2666 _PAGE_CACHE = page_cache4v_flag; 2667 2668 #ifdef CONFIG_DEBUG_PAGEALLOC 2669 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2670 #else 2671 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ 2672 PAGE_OFFSET; 2673 #endif 2674 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V | 2675 _PAGE_W_4V); 2676 2677 for (i = 1; i < 4; i++) 2678 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2679 2680 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | 2681 __ACCESS_BITS_4V | _PAGE_E_4V); 2682 2683 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | 2684 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | 2685 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | 2686 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); 2687 2688 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag; 2689 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2690 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); 2691 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2692 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2693 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2694 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2695 2696 page_exec_bit = _PAGE_EXEC_4V; 2697 2698 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2699 page_exec_bit); 2700 } 2701 2702 unsigned long pte_sz_bits(unsigned long sz) 2703 { 2704 if (tlb_type == hypervisor) { 2705 switch (sz) { 2706 case 8 * 1024: 2707 default: 2708 return _PAGE_SZ8K_4V; 2709 case 64 * 1024: 2710 return _PAGE_SZ64K_4V; 2711 case 512 * 1024: 2712 return _PAGE_SZ512K_4V; 2713 case 4 * 1024 * 1024: 2714 return _PAGE_SZ4MB_4V; 2715 } 2716 } else { 2717 switch (sz) { 2718 case 8 * 1024: 2719 default: 2720 return _PAGE_SZ8K_4U; 2721 case 64 * 1024: 2722 return _PAGE_SZ64K_4U; 2723 case 512 * 1024: 2724 return _PAGE_SZ512K_4U; 2725 case 4 * 1024 * 1024: 2726 return _PAGE_SZ4MB_4U; 2727 } 2728 } 2729 } 2730 2731 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) 2732 { 2733 pte_t pte; 2734 2735 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); 2736 pte_val(pte) |= (((unsigned long)space) << 32); 2737 pte_val(pte) |= pte_sz_bits(page_size); 2738 2739 return pte; 2740 } 2741 2742 static unsigned long kern_large_tte(unsigned long paddr) 2743 { 2744 unsigned long val; 2745 2746 val = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2747 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | 2748 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); 2749 if (tlb_type == hypervisor) 2750 val = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2751 page_cache4v_flag | _PAGE_P_4V | 2752 _PAGE_EXEC_4V | _PAGE_W_4V); 2753 2754 return val | paddr; 2755 } 2756 2757 /* If not locked, zap it. */ 2758 void __flush_tlb_all(void) 2759 { 2760 unsigned long pstate; 2761 int i; 2762 2763 __asm__ __volatile__("flushw\n\t" 2764 "rdpr %%pstate, %0\n\t" 2765 "wrpr %0, %1, %%pstate" 2766 : "=r" (pstate) 2767 : "i" (PSTATE_IE)); 2768 if (tlb_type == hypervisor) { 2769 sun4v_mmu_demap_all(); 2770 } else if (tlb_type == spitfire) { 2771 for (i = 0; i < 64; i++) { 2772 /* Spitfire Errata #32 workaround */ 2773 /* NOTE: Always runs on spitfire, so no 2774 * cheetah+ page size encodings. 2775 */ 2776 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2777 "flush %%g6" 2778 : /* No outputs */ 2779 : "r" (0), 2780 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2781 2782 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { 2783 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2784 "membar #Sync" 2785 : /* no outputs */ 2786 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); 2787 spitfire_put_dtlb_data(i, 0x0UL); 2788 } 2789 2790 /* Spitfire Errata #32 workaround */ 2791 /* NOTE: Always runs on spitfire, so no 2792 * cheetah+ page size encodings. 2793 */ 2794 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2795 "flush %%g6" 2796 : /* No outputs */ 2797 : "r" (0), 2798 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2799 2800 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { 2801 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2802 "membar #Sync" 2803 : /* no outputs */ 2804 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); 2805 spitfire_put_itlb_data(i, 0x0UL); 2806 } 2807 } 2808 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 2809 cheetah_flush_dtlb_all(); 2810 cheetah_flush_itlb_all(); 2811 } 2812 __asm__ __volatile__("wrpr %0, 0, %%pstate" 2813 : : "r" (pstate)); 2814 } 2815 2816 static pte_t *__pte_alloc_one(struct mm_struct *mm) 2817 { 2818 struct ptdesc *ptdesc = pagetable_alloc(GFP_KERNEL | __GFP_ZERO, 0); 2819 2820 if (!ptdesc) 2821 return NULL; 2822 if (!pagetable_pte_ctor(mm, ptdesc)) { 2823 pagetable_free(ptdesc); 2824 return NULL; 2825 } 2826 return ptdesc_address(ptdesc); 2827 } 2828 2829 pte_t *pte_alloc_one_kernel(struct mm_struct *mm) 2830 { 2831 return __pte_alloc_one(mm); 2832 } 2833 2834 pgtable_t pte_alloc_one(struct mm_struct *mm) 2835 { 2836 return __pte_alloc_one(mm); 2837 } 2838 2839 static void __pte_free(pgtable_t pte) 2840 { 2841 struct ptdesc *ptdesc = virt_to_ptdesc(pte); 2842 2843 pagetable_dtor(ptdesc); 2844 pagetable_free(ptdesc); 2845 } 2846 2847 void pte_free_kernel(struct mm_struct *mm, pte_t *pte) 2848 { 2849 __pte_free(pte); 2850 } 2851 2852 void pte_free(struct mm_struct *mm, pgtable_t pte) 2853 { 2854 __pte_free(pte); 2855 } 2856 2857 void pgtable_free(void *table, bool is_page) 2858 { 2859 if (is_page) 2860 __pte_free(table); 2861 else 2862 kmem_cache_free(pgtable_cache, table); 2863 } 2864 2865 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 2866 static void pte_free_now(struct rcu_head *head) 2867 { 2868 struct page *page; 2869 2870 page = container_of(head, struct page, rcu_head); 2871 __pte_free((pgtable_t)page_address(page)); 2872 } 2873 2874 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable) 2875 { 2876 struct page *page; 2877 2878 page = virt_to_page(pgtable); 2879 call_rcu(&page->rcu_head, pte_free_now); 2880 } 2881 2882 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 2883 pmd_t *pmd) 2884 { 2885 unsigned long pte, flags; 2886 struct mm_struct *mm; 2887 pmd_t entry = *pmd; 2888 2889 if (!pmd_leaf(entry) || !pmd_young(entry)) 2890 return; 2891 2892 pte = pmd_val(entry); 2893 2894 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ 2895 if (!(pte & _PAGE_VALID)) 2896 return; 2897 2898 /* We are fabricating 8MB pages using 4MB real hw pages. */ 2899 pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); 2900 2901 mm = vma->vm_mm; 2902 2903 spin_lock_irqsave(&mm->context.lock, flags); 2904 2905 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) 2906 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, 2907 addr, pte); 2908 2909 spin_unlock_irqrestore(&mm->context.lock, flags); 2910 } 2911 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 2912 2913 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 2914 static void context_reload(void *__data) 2915 { 2916 struct mm_struct *mm = __data; 2917 2918 if (mm == current->mm) 2919 load_secondary_context(mm); 2920 } 2921 2922 void hugetlb_setup(struct pt_regs *regs) 2923 { 2924 struct mm_struct *mm = current->mm; 2925 struct tsb_config *tp; 2926 2927 if (faulthandler_disabled() || !mm) { 2928 const struct exception_table_entry *entry; 2929 2930 entry = search_exception_tables(regs->tpc); 2931 if (entry) { 2932 regs->tpc = entry->fixup; 2933 regs->tnpc = regs->tpc + 4; 2934 return; 2935 } 2936 pr_alert("Unexpected HugeTLB setup in atomic context.\n"); 2937 die_if_kernel("HugeTSB in atomic", regs); 2938 } 2939 2940 tp = &mm->context.tsb_block[MM_TSB_HUGE]; 2941 if (likely(tp->tsb == NULL)) 2942 tsb_grow(mm, MM_TSB_HUGE, 0); 2943 2944 tsb_context_switch(mm); 2945 smp_tsb_sync(mm); 2946 2947 /* On UltraSPARC-III+ and later, configure the second half of 2948 * the Data-TLB for huge pages. 2949 */ 2950 if (tlb_type == cheetah_plus) { 2951 bool need_context_reload = false; 2952 unsigned long ctx; 2953 2954 spin_lock_irq(&ctx_alloc_lock); 2955 ctx = mm->context.sparc64_ctx_val; 2956 ctx &= ~CTX_PGSZ_MASK; 2957 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; 2958 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; 2959 2960 if (ctx != mm->context.sparc64_ctx_val) { 2961 /* When changing the page size fields, we 2962 * must perform a context flush so that no 2963 * stale entries match. This flush must 2964 * occur with the original context register 2965 * settings. 2966 */ 2967 do_flush_tlb_mm(mm); 2968 2969 /* Reload the context register of all processors 2970 * also executing in this address space. 2971 */ 2972 mm->context.sparc64_ctx_val = ctx; 2973 need_context_reload = true; 2974 } 2975 spin_unlock_irq(&ctx_alloc_lock); 2976 2977 if (need_context_reload) 2978 on_each_cpu(context_reload, mm, 0); 2979 } 2980 } 2981 #endif 2982 2983 static struct resource code_resource = { 2984 .name = "Kernel code", 2985 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 2986 }; 2987 2988 static struct resource data_resource = { 2989 .name = "Kernel data", 2990 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 2991 }; 2992 2993 static struct resource bss_resource = { 2994 .name = "Kernel bss", 2995 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 2996 }; 2997 2998 static inline resource_size_t compute_kern_paddr(void *addr) 2999 { 3000 return (resource_size_t) (addr - KERNBASE + kern_base); 3001 } 3002 3003 static void __init kernel_lds_init(void) 3004 { 3005 code_resource.start = compute_kern_paddr(_text); 3006 code_resource.end = compute_kern_paddr(_etext - 1); 3007 data_resource.start = compute_kern_paddr(_etext); 3008 data_resource.end = compute_kern_paddr(_edata - 1); 3009 bss_resource.start = compute_kern_paddr(__bss_start); 3010 bss_resource.end = compute_kern_paddr(_end - 1); 3011 } 3012 3013 static int __init report_memory(void) 3014 { 3015 int i; 3016 struct resource *res; 3017 3018 kernel_lds_init(); 3019 3020 for (i = 0; i < pavail_ents; i++) { 3021 res = kzalloc_obj(struct resource); 3022 3023 if (!res) { 3024 pr_warn("Failed to allocate source.\n"); 3025 break; 3026 } 3027 3028 res->name = "System RAM"; 3029 res->start = pavail[i].phys_addr; 3030 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; 3031 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM; 3032 3033 if (insert_resource(&iomem_resource, res) < 0) { 3034 pr_warn("Resource insertion failed.\n"); 3035 break; 3036 } 3037 3038 insert_resource(res, &code_resource); 3039 insert_resource(res, &data_resource); 3040 insert_resource(res, &bss_resource); 3041 } 3042 3043 return 0; 3044 } 3045 arch_initcall(report_memory); 3046 3047 #ifdef CONFIG_SMP 3048 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range 3049 #else 3050 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range 3051 #endif 3052 3053 void flush_tlb_kernel_range(unsigned long start, unsigned long end) 3054 { 3055 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { 3056 if (start < LOW_OBP_ADDRESS) { 3057 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); 3058 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); 3059 } 3060 if (end > HI_OBP_ADDRESS) { 3061 flush_tsb_kernel_range(HI_OBP_ADDRESS, end); 3062 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end); 3063 } 3064 } else { 3065 flush_tsb_kernel_range(start, end); 3066 do_flush_tlb_kernel_range(start, end); 3067 } 3068 } 3069 3070 void copy_user_highpage(struct page *to, struct page *from, 3071 unsigned long vaddr, struct vm_area_struct *vma) 3072 { 3073 char *vfrom, *vto; 3074 3075 vfrom = kmap_atomic(from); 3076 vto = kmap_atomic(to); 3077 copy_user_page(vto, vfrom, vaddr, to); 3078 kunmap_atomic(vto); 3079 kunmap_atomic(vfrom); 3080 3081 /* If this page has ADI enabled, copy over any ADI tags 3082 * as well 3083 */ 3084 if (vma->vm_flags & VM_SPARC_ADI) { 3085 unsigned long pfrom, pto, i, adi_tag; 3086 3087 pfrom = page_to_phys(from); 3088 pto = page_to_phys(to); 3089 3090 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3091 asm volatile("ldxa [%1] %2, %0\n\t" 3092 : "=r" (adi_tag) 3093 : "r" (i), "i" (ASI_MCD_REAL)); 3094 asm volatile("stxa %0, [%1] %2\n\t" 3095 : 3096 : "r" (adi_tag), "r" (pto), 3097 "i" (ASI_MCD_REAL)); 3098 pto += adi_blksize(); 3099 } 3100 asm volatile("membar #Sync\n\t"); 3101 } 3102 } 3103 EXPORT_SYMBOL(copy_user_highpage); 3104 3105 void copy_highpage(struct page *to, struct page *from) 3106 { 3107 char *vfrom, *vto; 3108 3109 vfrom = kmap_atomic(from); 3110 vto = kmap_atomic(to); 3111 copy_page(vto, vfrom); 3112 kunmap_atomic(vto); 3113 kunmap_atomic(vfrom); 3114 3115 /* If this platform is ADI enabled, copy any ADI tags 3116 * as well 3117 */ 3118 if (adi_capable()) { 3119 unsigned long pfrom, pto, i, adi_tag; 3120 3121 pfrom = page_to_phys(from); 3122 pto = page_to_phys(to); 3123 3124 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3125 asm volatile("ldxa [%1] %2, %0\n\t" 3126 : "=r" (adi_tag) 3127 : "r" (i), "i" (ASI_MCD_REAL)); 3128 asm volatile("stxa %0, [%1] %2\n\t" 3129 : 3130 : "r" (adi_tag), "r" (pto), 3131 "i" (ASI_MCD_REAL)); 3132 pto += adi_blksize(); 3133 } 3134 asm volatile("membar #Sync\n\t"); 3135 } 3136 } 3137 EXPORT_SYMBOL(copy_highpage); 3138 3139 pgprot_t vm_get_page_prot(vm_flags_t vm_flags) 3140 { 3141 unsigned long prot = pgprot_val(protection_map[vm_flags & 3142 (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]); 3143 3144 if (vm_flags & VM_SPARC_ADI) 3145 prot |= _PAGE_MCD_4V; 3146 3147 return __pgprot(prot); 3148 } 3149 EXPORT_SYMBOL(vm_get_page_prot); 3150