1 /* 2 * arch/sparc64/mm/init.c 3 * 4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #include <linux/extable.h> 9 #include <linux/kernel.h> 10 #include <linux/sched.h> 11 #include <linux/string.h> 12 #include <linux/init.h> 13 #include <linux/bootmem.h> 14 #include <linux/mm.h> 15 #include <linux/hugetlb.h> 16 #include <linux/initrd.h> 17 #include <linux/swap.h> 18 #include <linux/pagemap.h> 19 #include <linux/poison.h> 20 #include <linux/fs.h> 21 #include <linux/seq_file.h> 22 #include <linux/kprobes.h> 23 #include <linux/cache.h> 24 #include <linux/sort.h> 25 #include <linux/ioport.h> 26 #include <linux/percpu.h> 27 #include <linux/memblock.h> 28 #include <linux/mmzone.h> 29 #include <linux/gfp.h> 30 31 #include <asm/head.h> 32 #include <asm/page.h> 33 #include <asm/pgalloc.h> 34 #include <asm/pgtable.h> 35 #include <asm/oplib.h> 36 #include <asm/iommu.h> 37 #include <asm/io.h> 38 #include <linux/uaccess.h> 39 #include <asm/mmu_context.h> 40 #include <asm/tlbflush.h> 41 #include <asm/dma.h> 42 #include <asm/starfire.h> 43 #include <asm/tlb.h> 44 #include <asm/spitfire.h> 45 #include <asm/sections.h> 46 #include <asm/tsb.h> 47 #include <asm/hypervisor.h> 48 #include <asm/prom.h> 49 #include <asm/mdesc.h> 50 #include <asm/cpudata.h> 51 #include <asm/setup.h> 52 #include <asm/irq.h> 53 54 #include "init_64.h" 55 56 unsigned long kern_linear_pte_xor[4] __read_mostly; 57 static unsigned long page_cache4v_flag; 58 59 /* A bitmap, two bits for every 256MB of physical memory. These two 60 * bits determine what page size we use for kernel linear 61 * translations. They form an index into kern_linear_pte_xor[]. The 62 * value in the indexed slot is XOR'd with the TLB miss virtual 63 * address to form the resulting TTE. The mapping is: 64 * 65 * 0 ==> 4MB 66 * 1 ==> 256MB 67 * 2 ==> 2GB 68 * 3 ==> 16GB 69 * 70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later 71 * support 2GB pages, and hopefully future cpus will support the 16GB 72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there 73 * if these larger page sizes are not supported by the cpu. 74 * 75 * It would be nice to determine this from the machine description 76 * 'cpu' properties, but we need to have this table setup before the 77 * MDESC is initialized. 78 */ 79 80 #ifndef CONFIG_DEBUG_PAGEALLOC 81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. 82 * Space is allocated for this right after the trap table in 83 * arch/sparc64/kernel/head.S 84 */ 85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; 86 #endif 87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; 88 89 static unsigned long cpu_pgsz_mask; 90 91 #define MAX_BANKS 1024 92 93 static struct linux_prom64_registers pavail[MAX_BANKS]; 94 static int pavail_ents; 95 96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES]; 97 98 static int cmp_p64(const void *a, const void *b) 99 { 100 const struct linux_prom64_registers *x = a, *y = b; 101 102 if (x->phys_addr > y->phys_addr) 103 return 1; 104 if (x->phys_addr < y->phys_addr) 105 return -1; 106 return 0; 107 } 108 109 static void __init read_obp_memory(const char *property, 110 struct linux_prom64_registers *regs, 111 int *num_ents) 112 { 113 phandle node = prom_finddevice("/memory"); 114 int prop_size = prom_getproplen(node, property); 115 int ents, ret, i; 116 117 ents = prop_size / sizeof(struct linux_prom64_registers); 118 if (ents > MAX_BANKS) { 119 prom_printf("The machine has more %s property entries than " 120 "this kernel can support (%d).\n", 121 property, MAX_BANKS); 122 prom_halt(); 123 } 124 125 ret = prom_getproperty(node, property, (char *) regs, prop_size); 126 if (ret == -1) { 127 prom_printf("Couldn't get %s property from /memory.\n", 128 property); 129 prom_halt(); 130 } 131 132 /* Sanitize what we got from the firmware, by page aligning 133 * everything. 134 */ 135 for (i = 0; i < ents; i++) { 136 unsigned long base, size; 137 138 base = regs[i].phys_addr; 139 size = regs[i].reg_size; 140 141 size &= PAGE_MASK; 142 if (base & ~PAGE_MASK) { 143 unsigned long new_base = PAGE_ALIGN(base); 144 145 size -= new_base - base; 146 if ((long) size < 0L) 147 size = 0UL; 148 base = new_base; 149 } 150 if (size == 0UL) { 151 /* If it is empty, simply get rid of it. 152 * This simplifies the logic of the other 153 * functions that process these arrays. 154 */ 155 memmove(®s[i], ®s[i + 1], 156 (ents - i - 1) * sizeof(regs[0])); 157 i--; 158 ents--; 159 continue; 160 } 161 regs[i].phys_addr = base; 162 regs[i].reg_size = size; 163 } 164 165 *num_ents = ents; 166 167 sort(regs, ents, sizeof(struct linux_prom64_registers), 168 cmp_p64, NULL); 169 } 170 171 /* Kernel physical address base and size in bytes. */ 172 unsigned long kern_base __read_mostly; 173 unsigned long kern_size __read_mostly; 174 175 /* Initial ramdisk setup */ 176 extern unsigned long sparc_ramdisk_image64; 177 extern unsigned int sparc_ramdisk_image; 178 extern unsigned int sparc_ramdisk_size; 179 180 struct page *mem_map_zero __read_mostly; 181 EXPORT_SYMBOL(mem_map_zero); 182 183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; 184 185 unsigned long sparc64_kern_pri_context __read_mostly; 186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly; 187 unsigned long sparc64_kern_sec_context __read_mostly; 188 189 int num_kernel_image_mappings; 190 191 #ifdef CONFIG_DEBUG_DCFLUSH 192 atomic_t dcpage_flushes = ATOMIC_INIT(0); 193 #ifdef CONFIG_SMP 194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); 195 #endif 196 #endif 197 198 inline void flush_dcache_page_impl(struct page *page) 199 { 200 BUG_ON(tlb_type == hypervisor); 201 #ifdef CONFIG_DEBUG_DCFLUSH 202 atomic_inc(&dcpage_flushes); 203 #endif 204 205 #ifdef DCACHE_ALIASING_POSSIBLE 206 __flush_dcache_page(page_address(page), 207 ((tlb_type == spitfire) && 208 page_mapping(page) != NULL)); 209 #else 210 if (page_mapping(page) != NULL && 211 tlb_type == spitfire) 212 __flush_icache_page(__pa(page_address(page))); 213 #endif 214 } 215 216 #define PG_dcache_dirty PG_arch_1 217 #define PG_dcache_cpu_shift 32UL 218 #define PG_dcache_cpu_mask \ 219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) 220 221 #define dcache_dirty_cpu(page) \ 222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) 223 224 static inline void set_dcache_dirty(struct page *page, int this_cpu) 225 { 226 unsigned long mask = this_cpu; 227 unsigned long non_cpu_bits; 228 229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); 230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); 231 232 __asm__ __volatile__("1:\n\t" 233 "ldx [%2], %%g7\n\t" 234 "and %%g7, %1, %%g1\n\t" 235 "or %%g1, %0, %%g1\n\t" 236 "casx [%2], %%g7, %%g1\n\t" 237 "cmp %%g7, %%g1\n\t" 238 "bne,pn %%xcc, 1b\n\t" 239 " nop" 240 : /* no outputs */ 241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) 242 : "g1", "g7"); 243 } 244 245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) 246 { 247 unsigned long mask = (1UL << PG_dcache_dirty); 248 249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n" 250 "1:\n\t" 251 "ldx [%2], %%g7\n\t" 252 "srlx %%g7, %4, %%g1\n\t" 253 "and %%g1, %3, %%g1\n\t" 254 "cmp %%g1, %0\n\t" 255 "bne,pn %%icc, 2f\n\t" 256 " andn %%g7, %1, %%g1\n\t" 257 "casx [%2], %%g7, %%g1\n\t" 258 "cmp %%g7, %%g1\n\t" 259 "bne,pn %%xcc, 1b\n\t" 260 " nop\n" 261 "2:" 262 : /* no outputs */ 263 : "r" (cpu), "r" (mask), "r" (&page->flags), 264 "i" (PG_dcache_cpu_mask), 265 "i" (PG_dcache_cpu_shift) 266 : "g1", "g7"); 267 } 268 269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) 270 { 271 unsigned long tsb_addr = (unsigned long) ent; 272 273 if (tlb_type == cheetah_plus || tlb_type == hypervisor) 274 tsb_addr = __pa(tsb_addr); 275 276 __tsb_insert(tsb_addr, tag, pte); 277 } 278 279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly; 280 281 static void flush_dcache(unsigned long pfn) 282 { 283 struct page *page; 284 285 page = pfn_to_page(pfn); 286 if (page) { 287 unsigned long pg_flags; 288 289 pg_flags = page->flags; 290 if (pg_flags & (1UL << PG_dcache_dirty)) { 291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) & 292 PG_dcache_cpu_mask); 293 int this_cpu = get_cpu(); 294 295 /* This is just to optimize away some function calls 296 * in the SMP case. 297 */ 298 if (cpu == this_cpu) 299 flush_dcache_page_impl(page); 300 else 301 smp_flush_dcache_page_impl(page, cpu); 302 303 clear_dcache_dirty_cpu(page, cpu); 304 305 put_cpu(); 306 } 307 } 308 } 309 310 /* mm->context.lock must be held */ 311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, 312 unsigned long tsb_hash_shift, unsigned long address, 313 unsigned long tte) 314 { 315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; 316 unsigned long tag; 317 318 if (unlikely(!tsb)) 319 return; 320 321 tsb += ((address >> tsb_hash_shift) & 322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); 323 tag = (address >> 22UL); 324 tsb_insert(tsb, tag, tte); 325 } 326 327 #ifdef CONFIG_HUGETLB_PAGE 328 static void __init add_huge_page_size(unsigned long size) 329 { 330 unsigned int order; 331 332 if (size_to_hstate(size)) 333 return; 334 335 order = ilog2(size) - PAGE_SHIFT; 336 hugetlb_add_hstate(order); 337 } 338 339 static int __init hugetlbpage_init(void) 340 { 341 add_huge_page_size(1UL << HPAGE_64K_SHIFT); 342 add_huge_page_size(1UL << HPAGE_SHIFT); 343 add_huge_page_size(1UL << HPAGE_256MB_SHIFT); 344 add_huge_page_size(1UL << HPAGE_2GB_SHIFT); 345 346 return 0; 347 } 348 349 arch_initcall(hugetlbpage_init); 350 351 static int __init setup_hugepagesz(char *string) 352 { 353 unsigned long long hugepage_size; 354 unsigned int hugepage_shift; 355 unsigned short hv_pgsz_idx; 356 unsigned int hv_pgsz_mask; 357 int rc = 0; 358 359 hugepage_size = memparse(string, &string); 360 hugepage_shift = ilog2(hugepage_size); 361 362 switch (hugepage_shift) { 363 case HPAGE_2GB_SHIFT: 364 hv_pgsz_mask = HV_PGSZ_MASK_2GB; 365 hv_pgsz_idx = HV_PGSZ_IDX_2GB; 366 break; 367 case HPAGE_256MB_SHIFT: 368 hv_pgsz_mask = HV_PGSZ_MASK_256MB; 369 hv_pgsz_idx = HV_PGSZ_IDX_256MB; 370 break; 371 case HPAGE_SHIFT: 372 hv_pgsz_mask = HV_PGSZ_MASK_4MB; 373 hv_pgsz_idx = HV_PGSZ_IDX_4MB; 374 break; 375 case HPAGE_64K_SHIFT: 376 hv_pgsz_mask = HV_PGSZ_MASK_64K; 377 hv_pgsz_idx = HV_PGSZ_IDX_64K; 378 break; 379 default: 380 hv_pgsz_mask = 0; 381 } 382 383 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) { 384 hugetlb_bad_size(); 385 pr_err("hugepagesz=%llu not supported by MMU.\n", 386 hugepage_size); 387 goto out; 388 } 389 390 add_huge_page_size(hugepage_size); 391 rc = 1; 392 393 out: 394 return rc; 395 } 396 __setup("hugepagesz=", setup_hugepagesz); 397 #endif /* CONFIG_HUGETLB_PAGE */ 398 399 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) 400 { 401 struct mm_struct *mm; 402 unsigned long flags; 403 pte_t pte = *ptep; 404 405 if (tlb_type != hypervisor) { 406 unsigned long pfn = pte_pfn(pte); 407 408 if (pfn_valid(pfn)) 409 flush_dcache(pfn); 410 } 411 412 mm = vma->vm_mm; 413 414 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ 415 if (!pte_accessible(mm, pte)) 416 return; 417 418 spin_lock_irqsave(&mm->context.lock, flags); 419 420 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 421 if ((mm->context.hugetlb_pte_count || mm->context.thp_pte_count) && 422 is_hugetlb_pmd(__pmd(pte_val(pte)))) { 423 /* We are fabricating 8MB pages using 4MB real hw pages. */ 424 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT)); 425 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, 426 address, pte_val(pte)); 427 } else 428 #endif 429 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, 430 address, pte_val(pte)); 431 432 spin_unlock_irqrestore(&mm->context.lock, flags); 433 } 434 435 void flush_dcache_page(struct page *page) 436 { 437 struct address_space *mapping; 438 int this_cpu; 439 440 if (tlb_type == hypervisor) 441 return; 442 443 /* Do not bother with the expensive D-cache flush if it 444 * is merely the zero page. The 'bigcore' testcase in GDB 445 * causes this case to run millions of times. 446 */ 447 if (page == ZERO_PAGE(0)) 448 return; 449 450 this_cpu = get_cpu(); 451 452 mapping = page_mapping(page); 453 if (mapping && !mapping_mapped(mapping)) { 454 int dirty = test_bit(PG_dcache_dirty, &page->flags); 455 if (dirty) { 456 int dirty_cpu = dcache_dirty_cpu(page); 457 458 if (dirty_cpu == this_cpu) 459 goto out; 460 smp_flush_dcache_page_impl(page, dirty_cpu); 461 } 462 set_dcache_dirty(page, this_cpu); 463 } else { 464 /* We could delay the flush for the !page_mapping 465 * case too. But that case is for exec env/arg 466 * pages and those are %99 certainly going to get 467 * faulted into the tlb (and thus flushed) anyways. 468 */ 469 flush_dcache_page_impl(page); 470 } 471 472 out: 473 put_cpu(); 474 } 475 EXPORT_SYMBOL(flush_dcache_page); 476 477 void __kprobes flush_icache_range(unsigned long start, unsigned long end) 478 { 479 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ 480 if (tlb_type == spitfire) { 481 unsigned long kaddr; 482 483 /* This code only runs on Spitfire cpus so this is 484 * why we can assume _PAGE_PADDR_4U. 485 */ 486 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { 487 unsigned long paddr, mask = _PAGE_PADDR_4U; 488 489 if (kaddr >= PAGE_OFFSET) 490 paddr = kaddr & mask; 491 else { 492 pgd_t *pgdp = pgd_offset_k(kaddr); 493 pud_t *pudp = pud_offset(pgdp, kaddr); 494 pmd_t *pmdp = pmd_offset(pudp, kaddr); 495 pte_t *ptep = pte_offset_kernel(pmdp, kaddr); 496 497 paddr = pte_val(*ptep) & mask; 498 } 499 __flush_icache_page(paddr); 500 } 501 } 502 } 503 EXPORT_SYMBOL(flush_icache_range); 504 505 void mmu_info(struct seq_file *m) 506 { 507 static const char *pgsz_strings[] = { 508 "8K", "64K", "512K", "4MB", "32MB", 509 "256MB", "2GB", "16GB", 510 }; 511 int i, printed; 512 513 if (tlb_type == cheetah) 514 seq_printf(m, "MMU Type\t: Cheetah\n"); 515 else if (tlb_type == cheetah_plus) 516 seq_printf(m, "MMU Type\t: Cheetah+\n"); 517 else if (tlb_type == spitfire) 518 seq_printf(m, "MMU Type\t: Spitfire\n"); 519 else if (tlb_type == hypervisor) 520 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); 521 else 522 seq_printf(m, "MMU Type\t: ???\n"); 523 524 seq_printf(m, "MMU PGSZs\t: "); 525 printed = 0; 526 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { 527 if (cpu_pgsz_mask & (1UL << i)) { 528 seq_printf(m, "%s%s", 529 printed ? "," : "", pgsz_strings[i]); 530 printed++; 531 } 532 } 533 seq_putc(m, '\n'); 534 535 #ifdef CONFIG_DEBUG_DCFLUSH 536 seq_printf(m, "DCPageFlushes\t: %d\n", 537 atomic_read(&dcpage_flushes)); 538 #ifdef CONFIG_SMP 539 seq_printf(m, "DCPageFlushesXC\t: %d\n", 540 atomic_read(&dcpage_flushes_xcall)); 541 #endif /* CONFIG_SMP */ 542 #endif /* CONFIG_DEBUG_DCFLUSH */ 543 } 544 545 struct linux_prom_translation prom_trans[512] __read_mostly; 546 unsigned int prom_trans_ents __read_mostly; 547 548 unsigned long kern_locked_tte_data; 549 550 /* The obp translations are saved based on 8k pagesize, since obp can 551 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> 552 * HI_OBP_ADDRESS range are handled in ktlb.S. 553 */ 554 static inline int in_obp_range(unsigned long vaddr) 555 { 556 return (vaddr >= LOW_OBP_ADDRESS && 557 vaddr < HI_OBP_ADDRESS); 558 } 559 560 static int cmp_ptrans(const void *a, const void *b) 561 { 562 const struct linux_prom_translation *x = a, *y = b; 563 564 if (x->virt > y->virt) 565 return 1; 566 if (x->virt < y->virt) 567 return -1; 568 return 0; 569 } 570 571 /* Read OBP translations property into 'prom_trans[]'. */ 572 static void __init read_obp_translations(void) 573 { 574 int n, node, ents, first, last, i; 575 576 node = prom_finddevice("/virtual-memory"); 577 n = prom_getproplen(node, "translations"); 578 if (unlikely(n == 0 || n == -1)) { 579 prom_printf("prom_mappings: Couldn't get size.\n"); 580 prom_halt(); 581 } 582 if (unlikely(n > sizeof(prom_trans))) { 583 prom_printf("prom_mappings: Size %d is too big.\n", n); 584 prom_halt(); 585 } 586 587 if ((n = prom_getproperty(node, "translations", 588 (char *)&prom_trans[0], 589 sizeof(prom_trans))) == -1) { 590 prom_printf("prom_mappings: Couldn't get property.\n"); 591 prom_halt(); 592 } 593 594 n = n / sizeof(struct linux_prom_translation); 595 596 ents = n; 597 598 sort(prom_trans, ents, sizeof(struct linux_prom_translation), 599 cmp_ptrans, NULL); 600 601 /* Now kick out all the non-OBP entries. */ 602 for (i = 0; i < ents; i++) { 603 if (in_obp_range(prom_trans[i].virt)) 604 break; 605 } 606 first = i; 607 for (; i < ents; i++) { 608 if (!in_obp_range(prom_trans[i].virt)) 609 break; 610 } 611 last = i; 612 613 for (i = 0; i < (last - first); i++) { 614 struct linux_prom_translation *src = &prom_trans[i + first]; 615 struct linux_prom_translation *dest = &prom_trans[i]; 616 617 *dest = *src; 618 } 619 for (; i < ents; i++) { 620 struct linux_prom_translation *dest = &prom_trans[i]; 621 dest->virt = dest->size = dest->data = 0x0UL; 622 } 623 624 prom_trans_ents = last - first; 625 626 if (tlb_type == spitfire) { 627 /* Clear diag TTE bits. */ 628 for (i = 0; i < prom_trans_ents; i++) 629 prom_trans[i].data &= ~0x0003fe0000000000UL; 630 } 631 632 /* Force execute bit on. */ 633 for (i = 0; i < prom_trans_ents; i++) 634 prom_trans[i].data |= (tlb_type == hypervisor ? 635 _PAGE_EXEC_4V : _PAGE_EXEC_4U); 636 } 637 638 static void __init hypervisor_tlb_lock(unsigned long vaddr, 639 unsigned long pte, 640 unsigned long mmu) 641 { 642 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); 643 644 if (ret != 0) { 645 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " 646 "errors with %lx\n", vaddr, 0, pte, mmu, ret); 647 prom_halt(); 648 } 649 } 650 651 static unsigned long kern_large_tte(unsigned long paddr); 652 653 static void __init remap_kernel(void) 654 { 655 unsigned long phys_page, tte_vaddr, tte_data; 656 int i, tlb_ent = sparc64_highest_locked_tlbent(); 657 658 tte_vaddr = (unsigned long) KERNBASE; 659 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 660 tte_data = kern_large_tte(phys_page); 661 662 kern_locked_tte_data = tte_data; 663 664 /* Now lock us into the TLBs via Hypervisor or OBP. */ 665 if (tlb_type == hypervisor) { 666 for (i = 0; i < num_kernel_image_mappings; i++) { 667 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); 668 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); 669 tte_vaddr += 0x400000; 670 tte_data += 0x400000; 671 } 672 } else { 673 for (i = 0; i < num_kernel_image_mappings; i++) { 674 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); 675 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); 676 tte_vaddr += 0x400000; 677 tte_data += 0x400000; 678 } 679 sparc64_highest_unlocked_tlb_ent = tlb_ent - i; 680 } 681 if (tlb_type == cheetah_plus) { 682 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 683 CTX_CHEETAH_PLUS_NUC); 684 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; 685 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; 686 } 687 } 688 689 690 static void __init inherit_prom_mappings(void) 691 { 692 /* Now fixup OBP's idea about where we really are mapped. */ 693 printk("Remapping the kernel... "); 694 remap_kernel(); 695 printk("done.\n"); 696 } 697 698 void prom_world(int enter) 699 { 700 if (!enter) 701 set_fs(get_fs()); 702 703 __asm__ __volatile__("flushw"); 704 } 705 706 void __flush_dcache_range(unsigned long start, unsigned long end) 707 { 708 unsigned long va; 709 710 if (tlb_type == spitfire) { 711 int n = 0; 712 713 for (va = start; va < end; va += 32) { 714 spitfire_put_dcache_tag(va & 0x3fe0, 0x0); 715 if (++n >= 512) 716 break; 717 } 718 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 719 start = __pa(start); 720 end = __pa(end); 721 for (va = start; va < end; va += 32) 722 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 723 "membar #Sync" 724 : /* no outputs */ 725 : "r" (va), 726 "i" (ASI_DCACHE_INVALIDATE)); 727 } 728 } 729 EXPORT_SYMBOL(__flush_dcache_range); 730 731 /* get_new_mmu_context() uses "cache + 1". */ 732 DEFINE_SPINLOCK(ctx_alloc_lock); 733 unsigned long tlb_context_cache = CTX_FIRST_VERSION; 734 #define MAX_CTX_NR (1UL << CTX_NR_BITS) 735 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) 736 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); 737 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0}; 738 739 static void mmu_context_wrap(void) 740 { 741 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK; 742 unsigned long new_ver, new_ctx, old_ctx; 743 struct mm_struct *mm; 744 int cpu; 745 746 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS); 747 748 /* Reserve kernel context */ 749 set_bit(0, mmu_context_bmap); 750 751 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION; 752 if (unlikely(new_ver == 0)) 753 new_ver = CTX_FIRST_VERSION; 754 tlb_context_cache = new_ver; 755 756 /* 757 * Make sure that any new mm that are added into per_cpu_secondary_mm, 758 * are going to go through get_new_mmu_context() path. 759 */ 760 mb(); 761 762 /* 763 * Updated versions to current on those CPUs that had valid secondary 764 * contexts 765 */ 766 for_each_online_cpu(cpu) { 767 /* 768 * If a new mm is stored after we took this mm from the array, 769 * it will go into get_new_mmu_context() path, because we 770 * already bumped the version in tlb_context_cache. 771 */ 772 mm = per_cpu(per_cpu_secondary_mm, cpu); 773 774 if (unlikely(!mm || mm == &init_mm)) 775 continue; 776 777 old_ctx = mm->context.sparc64_ctx_val; 778 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) { 779 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver; 780 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap); 781 mm->context.sparc64_ctx_val = new_ctx; 782 } 783 } 784 } 785 786 /* Caller does TLB context flushing on local CPU if necessary. 787 * The caller also ensures that CTX_VALID(mm->context) is false. 788 * 789 * We must be careful about boundary cases so that we never 790 * let the user have CTX 0 (nucleus) or we ever use a CTX 791 * version of zero (and thus NO_CONTEXT would not be caught 792 * by version mis-match tests in mmu_context.h). 793 * 794 * Always invoked with interrupts disabled. 795 */ 796 void get_new_mmu_context(struct mm_struct *mm) 797 { 798 unsigned long ctx, new_ctx; 799 unsigned long orig_pgsz_bits; 800 801 spin_lock(&ctx_alloc_lock); 802 retry: 803 /* wrap might have happened, test again if our context became valid */ 804 if (unlikely(CTX_VALID(mm->context))) 805 goto out; 806 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); 807 ctx = (tlb_context_cache + 1) & CTX_NR_MASK; 808 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); 809 if (new_ctx >= (1 << CTX_NR_BITS)) { 810 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); 811 if (new_ctx >= ctx) { 812 mmu_context_wrap(); 813 goto retry; 814 } 815 } 816 if (mm->context.sparc64_ctx_val) 817 cpumask_clear(mm_cpumask(mm)); 818 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); 819 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); 820 tlb_context_cache = new_ctx; 821 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; 822 out: 823 spin_unlock(&ctx_alloc_lock); 824 } 825 826 static int numa_enabled = 1; 827 static int numa_debug; 828 829 static int __init early_numa(char *p) 830 { 831 if (!p) 832 return 0; 833 834 if (strstr(p, "off")) 835 numa_enabled = 0; 836 837 if (strstr(p, "debug")) 838 numa_debug = 1; 839 840 return 0; 841 } 842 early_param("numa", early_numa); 843 844 #define numadbg(f, a...) \ 845 do { if (numa_debug) \ 846 printk(KERN_INFO f, ## a); \ 847 } while (0) 848 849 static void __init find_ramdisk(unsigned long phys_base) 850 { 851 #ifdef CONFIG_BLK_DEV_INITRD 852 if (sparc_ramdisk_image || sparc_ramdisk_image64) { 853 unsigned long ramdisk_image; 854 855 /* Older versions of the bootloader only supported a 856 * 32-bit physical address for the ramdisk image 857 * location, stored at sparc_ramdisk_image. Newer 858 * SILO versions set sparc_ramdisk_image to zero and 859 * provide a full 64-bit physical address at 860 * sparc_ramdisk_image64. 861 */ 862 ramdisk_image = sparc_ramdisk_image; 863 if (!ramdisk_image) 864 ramdisk_image = sparc_ramdisk_image64; 865 866 /* Another bootloader quirk. The bootloader normalizes 867 * the physical address to KERNBASE, so we have to 868 * factor that back out and add in the lowest valid 869 * physical page address to get the true physical address. 870 */ 871 ramdisk_image -= KERNBASE; 872 ramdisk_image += phys_base; 873 874 numadbg("Found ramdisk at physical address 0x%lx, size %u\n", 875 ramdisk_image, sparc_ramdisk_size); 876 877 initrd_start = ramdisk_image; 878 initrd_end = ramdisk_image + sparc_ramdisk_size; 879 880 memblock_reserve(initrd_start, sparc_ramdisk_size); 881 882 initrd_start += PAGE_OFFSET; 883 initrd_end += PAGE_OFFSET; 884 } 885 #endif 886 } 887 888 struct node_mem_mask { 889 unsigned long mask; 890 unsigned long match; 891 }; 892 static struct node_mem_mask node_masks[MAX_NUMNODES]; 893 static int num_node_masks; 894 895 #ifdef CONFIG_NEED_MULTIPLE_NODES 896 897 struct mdesc_mlgroup { 898 u64 node; 899 u64 latency; 900 u64 match; 901 u64 mask; 902 }; 903 904 static struct mdesc_mlgroup *mlgroups; 905 static int num_mlgroups; 906 907 int numa_cpu_lookup_table[NR_CPUS]; 908 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; 909 910 struct mdesc_mblock { 911 u64 base; 912 u64 size; 913 u64 offset; /* RA-to-PA */ 914 }; 915 static struct mdesc_mblock *mblocks; 916 static int num_mblocks; 917 918 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr) 919 { 920 struct mdesc_mblock *m = NULL; 921 int i; 922 923 for (i = 0; i < num_mblocks; i++) { 924 m = &mblocks[i]; 925 926 if (addr >= m->base && 927 addr < (m->base + m->size)) { 928 break; 929 } 930 } 931 932 return m; 933 } 934 935 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid) 936 { 937 int prev_nid, new_nid; 938 939 prev_nid = -1; 940 for ( ; start < end; start += PAGE_SIZE) { 941 for (new_nid = 0; new_nid < num_node_masks; new_nid++) { 942 struct node_mem_mask *p = &node_masks[new_nid]; 943 944 if ((start & p->mask) == p->match) { 945 if (prev_nid == -1) 946 prev_nid = new_nid; 947 break; 948 } 949 } 950 951 if (new_nid == num_node_masks) { 952 prev_nid = 0; 953 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.", 954 start); 955 break; 956 } 957 958 if (prev_nid != new_nid) 959 break; 960 } 961 *nid = prev_nid; 962 963 return start > end ? end : start; 964 } 965 966 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid) 967 { 968 u64 ret_end, pa_start, m_mask, m_match, m_end; 969 struct mdesc_mblock *mblock; 970 int _nid, i; 971 972 if (tlb_type != hypervisor) 973 return memblock_nid_range_sun4u(start, end, nid); 974 975 mblock = addr_to_mblock(start); 976 if (!mblock) { 977 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]", 978 start); 979 980 _nid = 0; 981 ret_end = end; 982 goto done; 983 } 984 985 pa_start = start + mblock->offset; 986 m_match = 0; 987 m_mask = 0; 988 989 for (_nid = 0; _nid < num_node_masks; _nid++) { 990 struct node_mem_mask *const m = &node_masks[_nid]; 991 992 if ((pa_start & m->mask) == m->match) { 993 m_match = m->match; 994 m_mask = m->mask; 995 break; 996 } 997 } 998 999 if (num_node_masks == _nid) { 1000 /* We could not find NUMA group, so default to 0, but lets 1001 * search for latency group, so we could calculate the correct 1002 * end address that we return 1003 */ 1004 _nid = 0; 1005 1006 for (i = 0; i < num_mlgroups; i++) { 1007 struct mdesc_mlgroup *const m = &mlgroups[i]; 1008 1009 if ((pa_start & m->mask) == m->match) { 1010 m_match = m->match; 1011 m_mask = m->mask; 1012 break; 1013 } 1014 } 1015 1016 if (i == num_mlgroups) { 1017 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]", 1018 start); 1019 1020 ret_end = end; 1021 goto done; 1022 } 1023 } 1024 1025 /* 1026 * Each latency group has match and mask, and each memory block has an 1027 * offset. An address belongs to a latency group if its address matches 1028 * the following formula: ((addr + offset) & mask) == match 1029 * It is, however, slow to check every single page if it matches a 1030 * particular latency group. As optimization we calculate end value by 1031 * using bit arithmetics. 1032 */ 1033 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset; 1034 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1); 1035 ret_end = m_end > end ? end : m_end; 1036 1037 done: 1038 *nid = _nid; 1039 return ret_end; 1040 } 1041 #endif 1042 1043 /* This must be invoked after performing all of the necessary 1044 * memblock_set_node() calls for 'nid'. We need to be able to get 1045 * correct data from get_pfn_range_for_nid(). 1046 */ 1047 static void __init allocate_node_data(int nid) 1048 { 1049 struct pglist_data *p; 1050 unsigned long start_pfn, end_pfn; 1051 #ifdef CONFIG_NEED_MULTIPLE_NODES 1052 unsigned long paddr; 1053 1054 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid); 1055 if (!paddr) { 1056 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); 1057 prom_halt(); 1058 } 1059 NODE_DATA(nid) = __va(paddr); 1060 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); 1061 1062 NODE_DATA(nid)->node_id = nid; 1063 #endif 1064 1065 p = NODE_DATA(nid); 1066 1067 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); 1068 p->node_start_pfn = start_pfn; 1069 p->node_spanned_pages = end_pfn - start_pfn; 1070 } 1071 1072 static void init_node_masks_nonnuma(void) 1073 { 1074 #ifdef CONFIG_NEED_MULTIPLE_NODES 1075 int i; 1076 #endif 1077 1078 numadbg("Initializing tables for non-numa.\n"); 1079 1080 node_masks[0].mask = 0; 1081 node_masks[0].match = 0; 1082 num_node_masks = 1; 1083 1084 #ifdef CONFIG_NEED_MULTIPLE_NODES 1085 for (i = 0; i < NR_CPUS; i++) 1086 numa_cpu_lookup_table[i] = 0; 1087 1088 cpumask_setall(&numa_cpumask_lookup_table[0]); 1089 #endif 1090 } 1091 1092 #ifdef CONFIG_NEED_MULTIPLE_NODES 1093 struct pglist_data *node_data[MAX_NUMNODES]; 1094 1095 EXPORT_SYMBOL(numa_cpu_lookup_table); 1096 EXPORT_SYMBOL(numa_cpumask_lookup_table); 1097 EXPORT_SYMBOL(node_data); 1098 1099 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, 1100 u32 cfg_handle) 1101 { 1102 u64 arc; 1103 1104 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { 1105 u64 target = mdesc_arc_target(md, arc); 1106 const u64 *val; 1107 1108 val = mdesc_get_property(md, target, 1109 "cfg-handle", NULL); 1110 if (val && *val == cfg_handle) 1111 return 0; 1112 } 1113 return -ENODEV; 1114 } 1115 1116 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, 1117 u32 cfg_handle) 1118 { 1119 u64 arc, candidate, best_latency = ~(u64)0; 1120 1121 candidate = MDESC_NODE_NULL; 1122 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1123 u64 target = mdesc_arc_target(md, arc); 1124 const char *name = mdesc_node_name(md, target); 1125 const u64 *val; 1126 1127 if (strcmp(name, "pio-latency-group")) 1128 continue; 1129 1130 val = mdesc_get_property(md, target, "latency", NULL); 1131 if (!val) 1132 continue; 1133 1134 if (*val < best_latency) { 1135 candidate = target; 1136 best_latency = *val; 1137 } 1138 } 1139 1140 if (candidate == MDESC_NODE_NULL) 1141 return -ENODEV; 1142 1143 return scan_pio_for_cfg_handle(md, candidate, cfg_handle); 1144 } 1145 1146 int of_node_to_nid(struct device_node *dp) 1147 { 1148 const struct linux_prom64_registers *regs; 1149 struct mdesc_handle *md; 1150 u32 cfg_handle; 1151 int count, nid; 1152 u64 grp; 1153 1154 /* This is the right thing to do on currently supported 1155 * SUN4U NUMA platforms as well, as the PCI controller does 1156 * not sit behind any particular memory controller. 1157 */ 1158 if (!mlgroups) 1159 return -1; 1160 1161 regs = of_get_property(dp, "reg", NULL); 1162 if (!regs) 1163 return -1; 1164 1165 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; 1166 1167 md = mdesc_grab(); 1168 1169 count = 0; 1170 nid = -1; 1171 mdesc_for_each_node_by_name(md, grp, "group") { 1172 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { 1173 nid = count; 1174 break; 1175 } 1176 count++; 1177 } 1178 1179 mdesc_release(md); 1180 1181 return nid; 1182 } 1183 1184 static void __init add_node_ranges(void) 1185 { 1186 struct memblock_region *reg; 1187 unsigned long prev_max; 1188 1189 memblock_resized: 1190 prev_max = memblock.memory.max; 1191 1192 for_each_memblock(memory, reg) { 1193 unsigned long size = reg->size; 1194 unsigned long start, end; 1195 1196 start = reg->base; 1197 end = start + size; 1198 while (start < end) { 1199 unsigned long this_end; 1200 int nid; 1201 1202 this_end = memblock_nid_range(start, end, &nid); 1203 1204 numadbg("Setting memblock NUMA node nid[%d] " 1205 "start[%lx] end[%lx]\n", 1206 nid, start, this_end); 1207 1208 memblock_set_node(start, this_end - start, 1209 &memblock.memory, nid); 1210 if (memblock.memory.max != prev_max) 1211 goto memblock_resized; 1212 start = this_end; 1213 } 1214 } 1215 } 1216 1217 static int __init grab_mlgroups(struct mdesc_handle *md) 1218 { 1219 unsigned long paddr; 1220 int count = 0; 1221 u64 node; 1222 1223 mdesc_for_each_node_by_name(md, node, "memory-latency-group") 1224 count++; 1225 if (!count) 1226 return -ENOENT; 1227 1228 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup), 1229 SMP_CACHE_BYTES); 1230 if (!paddr) 1231 return -ENOMEM; 1232 1233 mlgroups = __va(paddr); 1234 num_mlgroups = count; 1235 1236 count = 0; 1237 mdesc_for_each_node_by_name(md, node, "memory-latency-group") { 1238 struct mdesc_mlgroup *m = &mlgroups[count++]; 1239 const u64 *val; 1240 1241 m->node = node; 1242 1243 val = mdesc_get_property(md, node, "latency", NULL); 1244 m->latency = *val; 1245 val = mdesc_get_property(md, node, "address-match", NULL); 1246 m->match = *val; 1247 val = mdesc_get_property(md, node, "address-mask", NULL); 1248 m->mask = *val; 1249 1250 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " 1251 "match[%llx] mask[%llx]\n", 1252 count - 1, m->node, m->latency, m->match, m->mask); 1253 } 1254 1255 return 0; 1256 } 1257 1258 static int __init grab_mblocks(struct mdesc_handle *md) 1259 { 1260 unsigned long paddr; 1261 int count = 0; 1262 u64 node; 1263 1264 mdesc_for_each_node_by_name(md, node, "mblock") 1265 count++; 1266 if (!count) 1267 return -ENOENT; 1268 1269 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock), 1270 SMP_CACHE_BYTES); 1271 if (!paddr) 1272 return -ENOMEM; 1273 1274 mblocks = __va(paddr); 1275 num_mblocks = count; 1276 1277 count = 0; 1278 mdesc_for_each_node_by_name(md, node, "mblock") { 1279 struct mdesc_mblock *m = &mblocks[count++]; 1280 const u64 *val; 1281 1282 val = mdesc_get_property(md, node, "base", NULL); 1283 m->base = *val; 1284 val = mdesc_get_property(md, node, "size", NULL); 1285 m->size = *val; 1286 val = mdesc_get_property(md, node, 1287 "address-congruence-offset", NULL); 1288 1289 /* The address-congruence-offset property is optional. 1290 * Explicity zero it be identifty this. 1291 */ 1292 if (val) 1293 m->offset = *val; 1294 else 1295 m->offset = 0UL; 1296 1297 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", 1298 count - 1, m->base, m->size, m->offset); 1299 } 1300 1301 return 0; 1302 } 1303 1304 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, 1305 u64 grp, cpumask_t *mask) 1306 { 1307 u64 arc; 1308 1309 cpumask_clear(mask); 1310 1311 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { 1312 u64 target = mdesc_arc_target(md, arc); 1313 const char *name = mdesc_node_name(md, target); 1314 const u64 *id; 1315 1316 if (strcmp(name, "cpu")) 1317 continue; 1318 id = mdesc_get_property(md, target, "id", NULL); 1319 if (*id < nr_cpu_ids) 1320 cpumask_set_cpu(*id, mask); 1321 } 1322 } 1323 1324 static struct mdesc_mlgroup * __init find_mlgroup(u64 node) 1325 { 1326 int i; 1327 1328 for (i = 0; i < num_mlgroups; i++) { 1329 struct mdesc_mlgroup *m = &mlgroups[i]; 1330 if (m->node == node) 1331 return m; 1332 } 1333 return NULL; 1334 } 1335 1336 int __node_distance(int from, int to) 1337 { 1338 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) { 1339 pr_warn("Returning default NUMA distance value for %d->%d\n", 1340 from, to); 1341 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE; 1342 } 1343 return numa_latency[from][to]; 1344 } 1345 1346 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp) 1347 { 1348 int i; 1349 1350 for (i = 0; i < MAX_NUMNODES; i++) { 1351 struct node_mem_mask *n = &node_masks[i]; 1352 1353 if ((grp->mask == n->mask) && (grp->match == n->match)) 1354 break; 1355 } 1356 return i; 1357 } 1358 1359 static void __init find_numa_latencies_for_group(struct mdesc_handle *md, 1360 u64 grp, int index) 1361 { 1362 u64 arc; 1363 1364 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1365 int tnode; 1366 u64 target = mdesc_arc_target(md, arc); 1367 struct mdesc_mlgroup *m = find_mlgroup(target); 1368 1369 if (!m) 1370 continue; 1371 tnode = find_best_numa_node_for_mlgroup(m); 1372 if (tnode == MAX_NUMNODES) 1373 continue; 1374 numa_latency[index][tnode] = m->latency; 1375 } 1376 } 1377 1378 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, 1379 int index) 1380 { 1381 struct mdesc_mlgroup *candidate = NULL; 1382 u64 arc, best_latency = ~(u64)0; 1383 struct node_mem_mask *n; 1384 1385 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1386 u64 target = mdesc_arc_target(md, arc); 1387 struct mdesc_mlgroup *m = find_mlgroup(target); 1388 if (!m) 1389 continue; 1390 if (m->latency < best_latency) { 1391 candidate = m; 1392 best_latency = m->latency; 1393 } 1394 } 1395 if (!candidate) 1396 return -ENOENT; 1397 1398 if (num_node_masks != index) { 1399 printk(KERN_ERR "Inconsistent NUMA state, " 1400 "index[%d] != num_node_masks[%d]\n", 1401 index, num_node_masks); 1402 return -EINVAL; 1403 } 1404 1405 n = &node_masks[num_node_masks++]; 1406 1407 n->mask = candidate->mask; 1408 n->match = candidate->match; 1409 1410 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n", 1411 index, n->mask, n->match, candidate->latency); 1412 1413 return 0; 1414 } 1415 1416 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, 1417 int index) 1418 { 1419 cpumask_t mask; 1420 int cpu; 1421 1422 numa_parse_mdesc_group_cpus(md, grp, &mask); 1423 1424 for_each_cpu(cpu, &mask) 1425 numa_cpu_lookup_table[cpu] = index; 1426 cpumask_copy(&numa_cpumask_lookup_table[index], &mask); 1427 1428 if (numa_debug) { 1429 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); 1430 for_each_cpu(cpu, &mask) 1431 printk("%d ", cpu); 1432 printk("]\n"); 1433 } 1434 1435 return numa_attach_mlgroup(md, grp, index); 1436 } 1437 1438 static int __init numa_parse_mdesc(void) 1439 { 1440 struct mdesc_handle *md = mdesc_grab(); 1441 int i, j, err, count; 1442 u64 node; 1443 1444 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); 1445 if (node == MDESC_NODE_NULL) { 1446 mdesc_release(md); 1447 return -ENOENT; 1448 } 1449 1450 err = grab_mblocks(md); 1451 if (err < 0) 1452 goto out; 1453 1454 err = grab_mlgroups(md); 1455 if (err < 0) 1456 goto out; 1457 1458 count = 0; 1459 mdesc_for_each_node_by_name(md, node, "group") { 1460 err = numa_parse_mdesc_group(md, node, count); 1461 if (err < 0) 1462 break; 1463 count++; 1464 } 1465 1466 count = 0; 1467 mdesc_for_each_node_by_name(md, node, "group") { 1468 find_numa_latencies_for_group(md, node, count); 1469 count++; 1470 } 1471 1472 /* Normalize numa latency matrix according to ACPI SLIT spec. */ 1473 for (i = 0; i < MAX_NUMNODES; i++) { 1474 u64 self_latency = numa_latency[i][i]; 1475 1476 for (j = 0; j < MAX_NUMNODES; j++) { 1477 numa_latency[i][j] = 1478 (numa_latency[i][j] * LOCAL_DISTANCE) / 1479 self_latency; 1480 } 1481 } 1482 1483 add_node_ranges(); 1484 1485 for (i = 0; i < num_node_masks; i++) { 1486 allocate_node_data(i); 1487 node_set_online(i); 1488 } 1489 1490 err = 0; 1491 out: 1492 mdesc_release(md); 1493 return err; 1494 } 1495 1496 static int __init numa_parse_jbus(void) 1497 { 1498 unsigned long cpu, index; 1499 1500 /* NUMA node id is encoded in bits 36 and higher, and there is 1501 * a 1-to-1 mapping from CPU ID to NUMA node ID. 1502 */ 1503 index = 0; 1504 for_each_present_cpu(cpu) { 1505 numa_cpu_lookup_table[cpu] = index; 1506 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); 1507 node_masks[index].mask = ~((1UL << 36UL) - 1UL); 1508 node_masks[index].match = cpu << 36UL; 1509 1510 index++; 1511 } 1512 num_node_masks = index; 1513 1514 add_node_ranges(); 1515 1516 for (index = 0; index < num_node_masks; index++) { 1517 allocate_node_data(index); 1518 node_set_online(index); 1519 } 1520 1521 return 0; 1522 } 1523 1524 static int __init numa_parse_sun4u(void) 1525 { 1526 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1527 unsigned long ver; 1528 1529 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 1530 if ((ver >> 32UL) == __JALAPENO_ID || 1531 (ver >> 32UL) == __SERRANO_ID) 1532 return numa_parse_jbus(); 1533 } 1534 return -1; 1535 } 1536 1537 static int __init bootmem_init_numa(void) 1538 { 1539 int i, j; 1540 int err = -1; 1541 1542 numadbg("bootmem_init_numa()\n"); 1543 1544 /* Some sane defaults for numa latency values */ 1545 for (i = 0; i < MAX_NUMNODES; i++) { 1546 for (j = 0; j < MAX_NUMNODES; j++) 1547 numa_latency[i][j] = (i == j) ? 1548 LOCAL_DISTANCE : REMOTE_DISTANCE; 1549 } 1550 1551 if (numa_enabled) { 1552 if (tlb_type == hypervisor) 1553 err = numa_parse_mdesc(); 1554 else 1555 err = numa_parse_sun4u(); 1556 } 1557 return err; 1558 } 1559 1560 #else 1561 1562 static int bootmem_init_numa(void) 1563 { 1564 return -1; 1565 } 1566 1567 #endif 1568 1569 static void __init bootmem_init_nonnuma(void) 1570 { 1571 unsigned long top_of_ram = memblock_end_of_DRAM(); 1572 unsigned long total_ram = memblock_phys_mem_size(); 1573 1574 numadbg("bootmem_init_nonnuma()\n"); 1575 1576 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", 1577 top_of_ram, total_ram); 1578 printk(KERN_INFO "Memory hole size: %ldMB\n", 1579 (top_of_ram - total_ram) >> 20); 1580 1581 init_node_masks_nonnuma(); 1582 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0); 1583 allocate_node_data(0); 1584 node_set_online(0); 1585 } 1586 1587 static unsigned long __init bootmem_init(unsigned long phys_base) 1588 { 1589 unsigned long end_pfn; 1590 1591 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; 1592 max_pfn = max_low_pfn = end_pfn; 1593 min_low_pfn = (phys_base >> PAGE_SHIFT); 1594 1595 if (bootmem_init_numa() < 0) 1596 bootmem_init_nonnuma(); 1597 1598 /* Dump memblock with node info. */ 1599 memblock_dump_all(); 1600 1601 /* XXX cpu notifier XXX */ 1602 1603 sparse_memory_present_with_active_regions(MAX_NUMNODES); 1604 sparse_init(); 1605 1606 return end_pfn; 1607 } 1608 1609 static struct linux_prom64_registers pall[MAX_BANKS] __initdata; 1610 static int pall_ents __initdata; 1611 1612 static unsigned long max_phys_bits = 40; 1613 1614 bool kern_addr_valid(unsigned long addr) 1615 { 1616 pgd_t *pgd; 1617 pud_t *pud; 1618 pmd_t *pmd; 1619 pte_t *pte; 1620 1621 if ((long)addr < 0L) { 1622 unsigned long pa = __pa(addr); 1623 1624 if ((pa >> max_phys_bits) != 0UL) 1625 return false; 1626 1627 return pfn_valid(pa >> PAGE_SHIFT); 1628 } 1629 1630 if (addr >= (unsigned long) KERNBASE && 1631 addr < (unsigned long)&_end) 1632 return true; 1633 1634 pgd = pgd_offset_k(addr); 1635 if (pgd_none(*pgd)) 1636 return 0; 1637 1638 pud = pud_offset(pgd, addr); 1639 if (pud_none(*pud)) 1640 return 0; 1641 1642 if (pud_large(*pud)) 1643 return pfn_valid(pud_pfn(*pud)); 1644 1645 pmd = pmd_offset(pud, addr); 1646 if (pmd_none(*pmd)) 1647 return 0; 1648 1649 if (pmd_large(*pmd)) 1650 return pfn_valid(pmd_pfn(*pmd)); 1651 1652 pte = pte_offset_kernel(pmd, addr); 1653 if (pte_none(*pte)) 1654 return 0; 1655 1656 return pfn_valid(pte_pfn(*pte)); 1657 } 1658 EXPORT_SYMBOL(kern_addr_valid); 1659 1660 static unsigned long __ref kernel_map_hugepud(unsigned long vstart, 1661 unsigned long vend, 1662 pud_t *pud) 1663 { 1664 const unsigned long mask16gb = (1UL << 34) - 1UL; 1665 u64 pte_val = vstart; 1666 1667 /* Each PUD is 8GB */ 1668 if ((vstart & mask16gb) || 1669 (vend - vstart <= mask16gb)) { 1670 pte_val ^= kern_linear_pte_xor[2]; 1671 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE; 1672 1673 return vstart + PUD_SIZE; 1674 } 1675 1676 pte_val ^= kern_linear_pte_xor[3]; 1677 pte_val |= _PAGE_PUD_HUGE; 1678 1679 vend = vstart + mask16gb + 1UL; 1680 while (vstart < vend) { 1681 pud_val(*pud) = pte_val; 1682 1683 pte_val += PUD_SIZE; 1684 vstart += PUD_SIZE; 1685 pud++; 1686 } 1687 return vstart; 1688 } 1689 1690 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend, 1691 bool guard) 1692 { 1693 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE) 1694 return true; 1695 1696 return false; 1697 } 1698 1699 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart, 1700 unsigned long vend, 1701 pmd_t *pmd) 1702 { 1703 const unsigned long mask256mb = (1UL << 28) - 1UL; 1704 const unsigned long mask2gb = (1UL << 31) - 1UL; 1705 u64 pte_val = vstart; 1706 1707 /* Each PMD is 8MB */ 1708 if ((vstart & mask256mb) || 1709 (vend - vstart <= mask256mb)) { 1710 pte_val ^= kern_linear_pte_xor[0]; 1711 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE; 1712 1713 return vstart + PMD_SIZE; 1714 } 1715 1716 if ((vstart & mask2gb) || 1717 (vend - vstart <= mask2gb)) { 1718 pte_val ^= kern_linear_pte_xor[1]; 1719 pte_val |= _PAGE_PMD_HUGE; 1720 vend = vstart + mask256mb + 1UL; 1721 } else { 1722 pte_val ^= kern_linear_pte_xor[2]; 1723 pte_val |= _PAGE_PMD_HUGE; 1724 vend = vstart + mask2gb + 1UL; 1725 } 1726 1727 while (vstart < vend) { 1728 pmd_val(*pmd) = pte_val; 1729 1730 pte_val += PMD_SIZE; 1731 vstart += PMD_SIZE; 1732 pmd++; 1733 } 1734 1735 return vstart; 1736 } 1737 1738 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend, 1739 bool guard) 1740 { 1741 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE) 1742 return true; 1743 1744 return false; 1745 } 1746 1747 static unsigned long __ref kernel_map_range(unsigned long pstart, 1748 unsigned long pend, pgprot_t prot, 1749 bool use_huge) 1750 { 1751 unsigned long vstart = PAGE_OFFSET + pstart; 1752 unsigned long vend = PAGE_OFFSET + pend; 1753 unsigned long alloc_bytes = 0UL; 1754 1755 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { 1756 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", 1757 vstart, vend); 1758 prom_halt(); 1759 } 1760 1761 while (vstart < vend) { 1762 unsigned long this_end, paddr = __pa(vstart); 1763 pgd_t *pgd = pgd_offset_k(vstart); 1764 pud_t *pud; 1765 pmd_t *pmd; 1766 pte_t *pte; 1767 1768 if (pgd_none(*pgd)) { 1769 pud_t *new; 1770 1771 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1772 alloc_bytes += PAGE_SIZE; 1773 pgd_populate(&init_mm, pgd, new); 1774 } 1775 pud = pud_offset(pgd, vstart); 1776 if (pud_none(*pud)) { 1777 pmd_t *new; 1778 1779 if (kernel_can_map_hugepud(vstart, vend, use_huge)) { 1780 vstart = kernel_map_hugepud(vstart, vend, pud); 1781 continue; 1782 } 1783 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1784 alloc_bytes += PAGE_SIZE; 1785 pud_populate(&init_mm, pud, new); 1786 } 1787 1788 pmd = pmd_offset(pud, vstart); 1789 if (pmd_none(*pmd)) { 1790 pte_t *new; 1791 1792 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) { 1793 vstart = kernel_map_hugepmd(vstart, vend, pmd); 1794 continue; 1795 } 1796 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1797 alloc_bytes += PAGE_SIZE; 1798 pmd_populate_kernel(&init_mm, pmd, new); 1799 } 1800 1801 pte = pte_offset_kernel(pmd, vstart); 1802 this_end = (vstart + PMD_SIZE) & PMD_MASK; 1803 if (this_end > vend) 1804 this_end = vend; 1805 1806 while (vstart < this_end) { 1807 pte_val(*pte) = (paddr | pgprot_val(prot)); 1808 1809 vstart += PAGE_SIZE; 1810 paddr += PAGE_SIZE; 1811 pte++; 1812 } 1813 } 1814 1815 return alloc_bytes; 1816 } 1817 1818 static void __init flush_all_kernel_tsbs(void) 1819 { 1820 int i; 1821 1822 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) { 1823 struct tsb *ent = &swapper_tsb[i]; 1824 1825 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1826 } 1827 #ifndef CONFIG_DEBUG_PAGEALLOC 1828 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) { 1829 struct tsb *ent = &swapper_4m_tsb[i]; 1830 1831 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1832 } 1833 #endif 1834 } 1835 1836 extern unsigned int kvmap_linear_patch[1]; 1837 1838 static void __init kernel_physical_mapping_init(void) 1839 { 1840 unsigned long i, mem_alloced = 0UL; 1841 bool use_huge = true; 1842 1843 #ifdef CONFIG_DEBUG_PAGEALLOC 1844 use_huge = false; 1845 #endif 1846 for (i = 0; i < pall_ents; i++) { 1847 unsigned long phys_start, phys_end; 1848 1849 phys_start = pall[i].phys_addr; 1850 phys_end = phys_start + pall[i].reg_size; 1851 1852 mem_alloced += kernel_map_range(phys_start, phys_end, 1853 PAGE_KERNEL, use_huge); 1854 } 1855 1856 printk("Allocated %ld bytes for kernel page tables.\n", 1857 mem_alloced); 1858 1859 kvmap_linear_patch[0] = 0x01000000; /* nop */ 1860 flushi(&kvmap_linear_patch[0]); 1861 1862 flush_all_kernel_tsbs(); 1863 1864 __flush_tlb_all(); 1865 } 1866 1867 #ifdef CONFIG_DEBUG_PAGEALLOC 1868 void __kernel_map_pages(struct page *page, int numpages, int enable) 1869 { 1870 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; 1871 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); 1872 1873 kernel_map_range(phys_start, phys_end, 1874 (enable ? PAGE_KERNEL : __pgprot(0)), false); 1875 1876 flush_tsb_kernel_range(PAGE_OFFSET + phys_start, 1877 PAGE_OFFSET + phys_end); 1878 1879 /* we should perform an IPI and flush all tlbs, 1880 * but that can deadlock->flush only current cpu. 1881 */ 1882 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, 1883 PAGE_OFFSET + phys_end); 1884 } 1885 #endif 1886 1887 unsigned long __init find_ecache_flush_span(unsigned long size) 1888 { 1889 int i; 1890 1891 for (i = 0; i < pavail_ents; i++) { 1892 if (pavail[i].reg_size >= size) 1893 return pavail[i].phys_addr; 1894 } 1895 1896 return ~0UL; 1897 } 1898 1899 unsigned long PAGE_OFFSET; 1900 EXPORT_SYMBOL(PAGE_OFFSET); 1901 1902 unsigned long VMALLOC_END = 0x0000010000000000UL; 1903 EXPORT_SYMBOL(VMALLOC_END); 1904 1905 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; 1906 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; 1907 1908 static void __init setup_page_offset(void) 1909 { 1910 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1911 /* Cheetah/Panther support a full 64-bit virtual 1912 * address, so we can use all that our page tables 1913 * support. 1914 */ 1915 sparc64_va_hole_top = 0xfff0000000000000UL; 1916 sparc64_va_hole_bottom = 0x0010000000000000UL; 1917 1918 max_phys_bits = 42; 1919 } else if (tlb_type == hypervisor) { 1920 switch (sun4v_chip_type) { 1921 case SUN4V_CHIP_NIAGARA1: 1922 case SUN4V_CHIP_NIAGARA2: 1923 /* T1 and T2 support 48-bit virtual addresses. */ 1924 sparc64_va_hole_top = 0xffff800000000000UL; 1925 sparc64_va_hole_bottom = 0x0000800000000000UL; 1926 1927 max_phys_bits = 39; 1928 break; 1929 case SUN4V_CHIP_NIAGARA3: 1930 /* T3 supports 48-bit virtual addresses. */ 1931 sparc64_va_hole_top = 0xffff800000000000UL; 1932 sparc64_va_hole_bottom = 0x0000800000000000UL; 1933 1934 max_phys_bits = 43; 1935 break; 1936 case SUN4V_CHIP_NIAGARA4: 1937 case SUN4V_CHIP_NIAGARA5: 1938 case SUN4V_CHIP_SPARC64X: 1939 case SUN4V_CHIP_SPARC_M6: 1940 /* T4 and later support 52-bit virtual addresses. */ 1941 sparc64_va_hole_top = 0xfff8000000000000UL; 1942 sparc64_va_hole_bottom = 0x0008000000000000UL; 1943 max_phys_bits = 47; 1944 break; 1945 case SUN4V_CHIP_SPARC_M7: 1946 case SUN4V_CHIP_SPARC_SN: 1947 default: 1948 /* M7 and later support 52-bit virtual addresses. */ 1949 sparc64_va_hole_top = 0xfff8000000000000UL; 1950 sparc64_va_hole_bottom = 0x0008000000000000UL; 1951 max_phys_bits = 49; 1952 break; 1953 } 1954 } 1955 1956 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { 1957 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", 1958 max_phys_bits); 1959 prom_halt(); 1960 } 1961 1962 PAGE_OFFSET = sparc64_va_hole_top; 1963 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) + 1964 (sparc64_va_hole_bottom >> 2)); 1965 1966 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", 1967 PAGE_OFFSET, max_phys_bits); 1968 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n", 1969 VMALLOC_START, VMALLOC_END); 1970 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n", 1971 VMEMMAP_BASE, VMEMMAP_BASE << 1); 1972 } 1973 1974 static void __init tsb_phys_patch(void) 1975 { 1976 struct tsb_ldquad_phys_patch_entry *pquad; 1977 struct tsb_phys_patch_entry *p; 1978 1979 pquad = &__tsb_ldquad_phys_patch; 1980 while (pquad < &__tsb_ldquad_phys_patch_end) { 1981 unsigned long addr = pquad->addr; 1982 1983 if (tlb_type == hypervisor) 1984 *(unsigned int *) addr = pquad->sun4v_insn; 1985 else 1986 *(unsigned int *) addr = pquad->sun4u_insn; 1987 wmb(); 1988 __asm__ __volatile__("flush %0" 1989 : /* no outputs */ 1990 : "r" (addr)); 1991 1992 pquad++; 1993 } 1994 1995 p = &__tsb_phys_patch; 1996 while (p < &__tsb_phys_patch_end) { 1997 unsigned long addr = p->addr; 1998 1999 *(unsigned int *) addr = p->insn; 2000 wmb(); 2001 __asm__ __volatile__("flush %0" 2002 : /* no outputs */ 2003 : "r" (addr)); 2004 2005 p++; 2006 } 2007 } 2008 2009 /* Don't mark as init, we give this to the Hypervisor. */ 2010 #ifndef CONFIG_DEBUG_PAGEALLOC 2011 #define NUM_KTSB_DESCR 2 2012 #else 2013 #define NUM_KTSB_DESCR 1 2014 #endif 2015 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; 2016 2017 /* The swapper TSBs are loaded with a base sequence of: 2018 * 2019 * sethi %uhi(SYMBOL), REG1 2020 * sethi %hi(SYMBOL), REG2 2021 * or REG1, %ulo(SYMBOL), REG1 2022 * or REG2, %lo(SYMBOL), REG2 2023 * sllx REG1, 32, REG1 2024 * or REG1, REG2, REG1 2025 * 2026 * When we use physical addressing for the TSB accesses, we patch the 2027 * first four instructions in the above sequence. 2028 */ 2029 2030 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) 2031 { 2032 unsigned long high_bits, low_bits; 2033 2034 high_bits = (pa >> 32) & 0xffffffff; 2035 low_bits = (pa >> 0) & 0xffffffff; 2036 2037 while (start < end) { 2038 unsigned int *ia = (unsigned int *)(unsigned long)*start; 2039 2040 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10); 2041 __asm__ __volatile__("flush %0" : : "r" (ia)); 2042 2043 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10); 2044 __asm__ __volatile__("flush %0" : : "r" (ia + 1)); 2045 2046 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff); 2047 __asm__ __volatile__("flush %0" : : "r" (ia + 2)); 2048 2049 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff); 2050 __asm__ __volatile__("flush %0" : : "r" (ia + 3)); 2051 2052 start++; 2053 } 2054 } 2055 2056 static void ktsb_phys_patch(void) 2057 { 2058 extern unsigned int __swapper_tsb_phys_patch; 2059 extern unsigned int __swapper_tsb_phys_patch_end; 2060 unsigned long ktsb_pa; 2061 2062 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2063 patch_one_ktsb_phys(&__swapper_tsb_phys_patch, 2064 &__swapper_tsb_phys_patch_end, ktsb_pa); 2065 #ifndef CONFIG_DEBUG_PAGEALLOC 2066 { 2067 extern unsigned int __swapper_4m_tsb_phys_patch; 2068 extern unsigned int __swapper_4m_tsb_phys_patch_end; 2069 ktsb_pa = (kern_base + 2070 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2071 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, 2072 &__swapper_4m_tsb_phys_patch_end, ktsb_pa); 2073 } 2074 #endif 2075 } 2076 2077 static void __init sun4v_ktsb_init(void) 2078 { 2079 unsigned long ktsb_pa; 2080 2081 /* First KTSB for PAGE_SIZE mappings. */ 2082 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2083 2084 switch (PAGE_SIZE) { 2085 case 8 * 1024: 2086 default: 2087 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; 2088 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; 2089 break; 2090 2091 case 64 * 1024: 2092 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; 2093 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; 2094 break; 2095 2096 case 512 * 1024: 2097 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; 2098 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; 2099 break; 2100 2101 case 4 * 1024 * 1024: 2102 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; 2103 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; 2104 break; 2105 } 2106 2107 ktsb_descr[0].assoc = 1; 2108 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; 2109 ktsb_descr[0].ctx_idx = 0; 2110 ktsb_descr[0].tsb_base = ktsb_pa; 2111 ktsb_descr[0].resv = 0; 2112 2113 #ifndef CONFIG_DEBUG_PAGEALLOC 2114 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ 2115 ktsb_pa = (kern_base + 2116 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2117 2118 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; 2119 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | 2120 HV_PGSZ_MASK_256MB | 2121 HV_PGSZ_MASK_2GB | 2122 HV_PGSZ_MASK_16GB) & 2123 cpu_pgsz_mask); 2124 ktsb_descr[1].assoc = 1; 2125 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; 2126 ktsb_descr[1].ctx_idx = 0; 2127 ktsb_descr[1].tsb_base = ktsb_pa; 2128 ktsb_descr[1].resv = 0; 2129 #endif 2130 } 2131 2132 void sun4v_ktsb_register(void) 2133 { 2134 unsigned long pa, ret; 2135 2136 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); 2137 2138 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); 2139 if (ret != 0) { 2140 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " 2141 "errors with %lx\n", pa, ret); 2142 prom_halt(); 2143 } 2144 } 2145 2146 static void __init sun4u_linear_pte_xor_finalize(void) 2147 { 2148 #ifndef CONFIG_DEBUG_PAGEALLOC 2149 /* This is where we would add Panther support for 2150 * 32MB and 256MB pages. 2151 */ 2152 #endif 2153 } 2154 2155 static void __init sun4v_linear_pte_xor_finalize(void) 2156 { 2157 unsigned long pagecv_flag; 2158 2159 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead 2160 * enables MCD error. Do not set bit 9 on M7 processor. 2161 */ 2162 switch (sun4v_chip_type) { 2163 case SUN4V_CHIP_SPARC_M7: 2164 case SUN4V_CHIP_SPARC_SN: 2165 pagecv_flag = 0x00; 2166 break; 2167 default: 2168 pagecv_flag = _PAGE_CV_4V; 2169 break; 2170 } 2171 #ifndef CONFIG_DEBUG_PAGEALLOC 2172 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { 2173 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ 2174 PAGE_OFFSET; 2175 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag | 2176 _PAGE_P_4V | _PAGE_W_4V); 2177 } else { 2178 kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; 2179 } 2180 2181 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { 2182 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ 2183 PAGE_OFFSET; 2184 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag | 2185 _PAGE_P_4V | _PAGE_W_4V); 2186 } else { 2187 kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; 2188 } 2189 2190 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { 2191 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ 2192 PAGE_OFFSET; 2193 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag | 2194 _PAGE_P_4V | _PAGE_W_4V); 2195 } else { 2196 kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; 2197 } 2198 #endif 2199 } 2200 2201 /* paging_init() sets up the page tables */ 2202 2203 static unsigned long last_valid_pfn; 2204 2205 static void sun4u_pgprot_init(void); 2206 static void sun4v_pgprot_init(void); 2207 2208 static phys_addr_t __init available_memory(void) 2209 { 2210 phys_addr_t available = 0ULL; 2211 phys_addr_t pa_start, pa_end; 2212 u64 i; 2213 2214 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, 2215 &pa_end, NULL) 2216 available = available + (pa_end - pa_start); 2217 2218 return available; 2219 } 2220 2221 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) 2222 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) 2223 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) 2224 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) 2225 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) 2226 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) 2227 2228 /* We need to exclude reserved regions. This exclusion will include 2229 * vmlinux and initrd. To be more precise the initrd size could be used to 2230 * compute a new lower limit because it is freed later during initialization. 2231 */ 2232 static void __init reduce_memory(phys_addr_t limit_ram) 2233 { 2234 phys_addr_t avail_ram = available_memory(); 2235 phys_addr_t pa_start, pa_end; 2236 u64 i; 2237 2238 if (limit_ram >= avail_ram) 2239 return; 2240 2241 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, 2242 &pa_end, NULL) { 2243 phys_addr_t region_size = pa_end - pa_start; 2244 phys_addr_t clip_start = pa_start; 2245 2246 avail_ram = avail_ram - region_size; 2247 /* Are we consuming too much? */ 2248 if (avail_ram < limit_ram) { 2249 phys_addr_t give_back = limit_ram - avail_ram; 2250 2251 region_size = region_size - give_back; 2252 clip_start = clip_start + give_back; 2253 } 2254 2255 memblock_remove(clip_start, region_size); 2256 2257 if (avail_ram <= limit_ram) 2258 break; 2259 i = 0UL; 2260 } 2261 } 2262 2263 void __init paging_init(void) 2264 { 2265 unsigned long end_pfn, shift, phys_base; 2266 unsigned long real_end, i; 2267 2268 setup_page_offset(); 2269 2270 /* These build time checkes make sure that the dcache_dirty_cpu() 2271 * page->flags usage will work. 2272 * 2273 * When a page gets marked as dcache-dirty, we store the 2274 * cpu number starting at bit 32 in the page->flags. Also, 2275 * functions like clear_dcache_dirty_cpu use the cpu mask 2276 * in 13-bit signed-immediate instruction fields. 2277 */ 2278 2279 /* 2280 * Page flags must not reach into upper 32 bits that are used 2281 * for the cpu number 2282 */ 2283 BUILD_BUG_ON(NR_PAGEFLAGS > 32); 2284 2285 /* 2286 * The bit fields placed in the high range must not reach below 2287 * the 32 bit boundary. Otherwise we cannot place the cpu field 2288 * at the 32 bit boundary. 2289 */ 2290 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + 2291 ilog2(roundup_pow_of_two(NR_CPUS)) > 32); 2292 2293 BUILD_BUG_ON(NR_CPUS > 4096); 2294 2295 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 2296 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 2297 2298 /* Invalidate both kernel TSBs. */ 2299 memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); 2300 #ifndef CONFIG_DEBUG_PAGEALLOC 2301 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2302 #endif 2303 2304 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde 2305 * bit on M7 processor. This is a conflicting usage of the same 2306 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption 2307 * Detection error on all pages and this will lead to problems 2308 * later. Kernel does not run with MCD enabled and hence rest 2309 * of the required steps to fully configure memory corruption 2310 * detection are not taken. We need to ensure TTE.mcde is not 2311 * set on M7 processor. Compute the value of cacheability 2312 * flag for use later taking this into consideration. 2313 */ 2314 switch (sun4v_chip_type) { 2315 case SUN4V_CHIP_SPARC_M7: 2316 case SUN4V_CHIP_SPARC_SN: 2317 page_cache4v_flag = _PAGE_CP_4V; 2318 break; 2319 default: 2320 page_cache4v_flag = _PAGE_CACHE_4V; 2321 break; 2322 } 2323 2324 if (tlb_type == hypervisor) 2325 sun4v_pgprot_init(); 2326 else 2327 sun4u_pgprot_init(); 2328 2329 if (tlb_type == cheetah_plus || 2330 tlb_type == hypervisor) { 2331 tsb_phys_patch(); 2332 ktsb_phys_patch(); 2333 } 2334 2335 if (tlb_type == hypervisor) 2336 sun4v_patch_tlb_handlers(); 2337 2338 /* Find available physical memory... 2339 * 2340 * Read it twice in order to work around a bug in openfirmware. 2341 * The call to grab this table itself can cause openfirmware to 2342 * allocate memory, which in turn can take away some space from 2343 * the list of available memory. Reading it twice makes sure 2344 * we really do get the final value. 2345 */ 2346 read_obp_translations(); 2347 read_obp_memory("reg", &pall[0], &pall_ents); 2348 read_obp_memory("available", &pavail[0], &pavail_ents); 2349 read_obp_memory("available", &pavail[0], &pavail_ents); 2350 2351 phys_base = 0xffffffffffffffffUL; 2352 for (i = 0; i < pavail_ents; i++) { 2353 phys_base = min(phys_base, pavail[i].phys_addr); 2354 memblock_add(pavail[i].phys_addr, pavail[i].reg_size); 2355 } 2356 2357 memblock_reserve(kern_base, kern_size); 2358 2359 find_ramdisk(phys_base); 2360 2361 if (cmdline_memory_size) 2362 reduce_memory(cmdline_memory_size); 2363 2364 memblock_allow_resize(); 2365 memblock_dump_all(); 2366 2367 set_bit(0, mmu_context_bmap); 2368 2369 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); 2370 2371 real_end = (unsigned long)_end; 2372 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); 2373 printk("Kernel: Using %d locked TLB entries for main kernel image.\n", 2374 num_kernel_image_mappings); 2375 2376 /* Set kernel pgd to upper alias so physical page computations 2377 * work. 2378 */ 2379 init_mm.pgd += ((shift) / (sizeof(pgd_t))); 2380 2381 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); 2382 2383 inherit_prom_mappings(); 2384 2385 /* Ok, we can use our TLB miss and window trap handlers safely. */ 2386 setup_tba(); 2387 2388 __flush_tlb_all(); 2389 2390 prom_build_devicetree(); 2391 of_populate_present_mask(); 2392 #ifndef CONFIG_SMP 2393 of_fill_in_cpu_data(); 2394 #endif 2395 2396 if (tlb_type == hypervisor) { 2397 sun4v_mdesc_init(); 2398 mdesc_populate_present_mask(cpu_all_mask); 2399 #ifndef CONFIG_SMP 2400 mdesc_fill_in_cpu_data(cpu_all_mask); 2401 #endif 2402 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); 2403 2404 sun4v_linear_pte_xor_finalize(); 2405 2406 sun4v_ktsb_init(); 2407 sun4v_ktsb_register(); 2408 } else { 2409 unsigned long impl, ver; 2410 2411 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | 2412 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); 2413 2414 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 2415 impl = ((ver >> 32) & 0xffff); 2416 if (impl == PANTHER_IMPL) 2417 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | 2418 HV_PGSZ_MASK_256MB); 2419 2420 sun4u_linear_pte_xor_finalize(); 2421 } 2422 2423 /* Flush the TLBs and the 4M TSB so that the updated linear 2424 * pte XOR settings are realized for all mappings. 2425 */ 2426 __flush_tlb_all(); 2427 #ifndef CONFIG_DEBUG_PAGEALLOC 2428 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2429 #endif 2430 __flush_tlb_all(); 2431 2432 /* Setup bootmem... */ 2433 last_valid_pfn = end_pfn = bootmem_init(phys_base); 2434 2435 kernel_physical_mapping_init(); 2436 2437 { 2438 unsigned long max_zone_pfns[MAX_NR_ZONES]; 2439 2440 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 2441 2442 max_zone_pfns[ZONE_NORMAL] = end_pfn; 2443 2444 free_area_init_nodes(max_zone_pfns); 2445 } 2446 2447 printk("Booting Linux...\n"); 2448 } 2449 2450 int page_in_phys_avail(unsigned long paddr) 2451 { 2452 int i; 2453 2454 paddr &= PAGE_MASK; 2455 2456 for (i = 0; i < pavail_ents; i++) { 2457 unsigned long start, end; 2458 2459 start = pavail[i].phys_addr; 2460 end = start + pavail[i].reg_size; 2461 2462 if (paddr >= start && paddr < end) 2463 return 1; 2464 } 2465 if (paddr >= kern_base && paddr < (kern_base + kern_size)) 2466 return 1; 2467 #ifdef CONFIG_BLK_DEV_INITRD 2468 if (paddr >= __pa(initrd_start) && 2469 paddr < __pa(PAGE_ALIGN(initrd_end))) 2470 return 1; 2471 #endif 2472 2473 return 0; 2474 } 2475 2476 static void __init register_page_bootmem_info(void) 2477 { 2478 #ifdef CONFIG_NEED_MULTIPLE_NODES 2479 int i; 2480 2481 for_each_online_node(i) 2482 if (NODE_DATA(i)->node_spanned_pages) 2483 register_page_bootmem_info_node(NODE_DATA(i)); 2484 #endif 2485 } 2486 void __init mem_init(void) 2487 { 2488 high_memory = __va(last_valid_pfn << PAGE_SHIFT); 2489 2490 register_page_bootmem_info(); 2491 free_all_bootmem(); 2492 2493 /* 2494 * Set up the zero page, mark it reserved, so that page count 2495 * is not manipulated when freeing the page from user ptes. 2496 */ 2497 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); 2498 if (mem_map_zero == NULL) { 2499 prom_printf("paging_init: Cannot alloc zero page.\n"); 2500 prom_halt(); 2501 } 2502 mark_page_reserved(mem_map_zero); 2503 2504 mem_init_print_info(NULL); 2505 2506 if (tlb_type == cheetah || tlb_type == cheetah_plus) 2507 cheetah_ecache_flush_init(); 2508 } 2509 2510 void free_initmem(void) 2511 { 2512 unsigned long addr, initend; 2513 int do_free = 1; 2514 2515 /* If the physical memory maps were trimmed by kernel command 2516 * line options, don't even try freeing this initmem stuff up. 2517 * The kernel image could have been in the trimmed out region 2518 * and if so the freeing below will free invalid page structs. 2519 */ 2520 if (cmdline_memory_size) 2521 do_free = 0; 2522 2523 /* 2524 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. 2525 */ 2526 addr = PAGE_ALIGN((unsigned long)(__init_begin)); 2527 initend = (unsigned long)(__init_end) & PAGE_MASK; 2528 for (; addr < initend; addr += PAGE_SIZE) { 2529 unsigned long page; 2530 2531 page = (addr + 2532 ((unsigned long) __va(kern_base)) - 2533 ((unsigned long) KERNBASE)); 2534 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); 2535 2536 if (do_free) 2537 free_reserved_page(virt_to_page(page)); 2538 } 2539 } 2540 2541 #ifdef CONFIG_BLK_DEV_INITRD 2542 void free_initrd_mem(unsigned long start, unsigned long end) 2543 { 2544 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM, 2545 "initrd"); 2546 } 2547 #endif 2548 2549 pgprot_t PAGE_KERNEL __read_mostly; 2550 EXPORT_SYMBOL(PAGE_KERNEL); 2551 2552 pgprot_t PAGE_KERNEL_LOCKED __read_mostly; 2553 pgprot_t PAGE_COPY __read_mostly; 2554 2555 pgprot_t PAGE_SHARED __read_mostly; 2556 EXPORT_SYMBOL(PAGE_SHARED); 2557 2558 unsigned long pg_iobits __read_mostly; 2559 2560 unsigned long _PAGE_IE __read_mostly; 2561 EXPORT_SYMBOL(_PAGE_IE); 2562 2563 unsigned long _PAGE_E __read_mostly; 2564 EXPORT_SYMBOL(_PAGE_E); 2565 2566 unsigned long _PAGE_CACHE __read_mostly; 2567 EXPORT_SYMBOL(_PAGE_CACHE); 2568 2569 #ifdef CONFIG_SPARSEMEM_VMEMMAP 2570 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, 2571 int node) 2572 { 2573 unsigned long pte_base; 2574 2575 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2576 _PAGE_CP_4U | _PAGE_CV_4U | 2577 _PAGE_P_4U | _PAGE_W_4U); 2578 if (tlb_type == hypervisor) 2579 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2580 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V); 2581 2582 pte_base |= _PAGE_PMD_HUGE; 2583 2584 vstart = vstart & PMD_MASK; 2585 vend = ALIGN(vend, PMD_SIZE); 2586 for (; vstart < vend; vstart += PMD_SIZE) { 2587 pgd_t *pgd = pgd_offset_k(vstart); 2588 unsigned long pte; 2589 pud_t *pud; 2590 pmd_t *pmd; 2591 2592 if (pgd_none(*pgd)) { 2593 pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node); 2594 2595 if (!new) 2596 return -ENOMEM; 2597 pgd_populate(&init_mm, pgd, new); 2598 } 2599 2600 pud = pud_offset(pgd, vstart); 2601 if (pud_none(*pud)) { 2602 pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node); 2603 2604 if (!new) 2605 return -ENOMEM; 2606 pud_populate(&init_mm, pud, new); 2607 } 2608 2609 pmd = pmd_offset(pud, vstart); 2610 2611 pte = pmd_val(*pmd); 2612 if (!(pte & _PAGE_VALID)) { 2613 void *block = vmemmap_alloc_block(PMD_SIZE, node); 2614 2615 if (!block) 2616 return -ENOMEM; 2617 2618 pmd_val(*pmd) = pte_base | __pa(block); 2619 } 2620 } 2621 2622 return 0; 2623 } 2624 2625 void vmemmap_free(unsigned long start, unsigned long end) 2626 { 2627 } 2628 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 2629 2630 static void prot_init_common(unsigned long page_none, 2631 unsigned long page_shared, 2632 unsigned long page_copy, 2633 unsigned long page_readonly, 2634 unsigned long page_exec_bit) 2635 { 2636 PAGE_COPY = __pgprot(page_copy); 2637 PAGE_SHARED = __pgprot(page_shared); 2638 2639 protection_map[0x0] = __pgprot(page_none); 2640 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); 2641 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); 2642 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); 2643 protection_map[0x4] = __pgprot(page_readonly); 2644 protection_map[0x5] = __pgprot(page_readonly); 2645 protection_map[0x6] = __pgprot(page_copy); 2646 protection_map[0x7] = __pgprot(page_copy); 2647 protection_map[0x8] = __pgprot(page_none); 2648 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); 2649 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); 2650 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); 2651 protection_map[0xc] = __pgprot(page_readonly); 2652 protection_map[0xd] = __pgprot(page_readonly); 2653 protection_map[0xe] = __pgprot(page_shared); 2654 protection_map[0xf] = __pgprot(page_shared); 2655 } 2656 2657 static void __init sun4u_pgprot_init(void) 2658 { 2659 unsigned long page_none, page_shared, page_copy, page_readonly; 2660 unsigned long page_exec_bit; 2661 int i; 2662 2663 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2664 _PAGE_CACHE_4U | _PAGE_P_4U | 2665 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2666 _PAGE_EXEC_4U); 2667 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2668 _PAGE_CACHE_4U | _PAGE_P_4U | 2669 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2670 _PAGE_EXEC_4U | _PAGE_L_4U); 2671 2672 _PAGE_IE = _PAGE_IE_4U; 2673 _PAGE_E = _PAGE_E_4U; 2674 _PAGE_CACHE = _PAGE_CACHE_4U; 2675 2676 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | 2677 __ACCESS_BITS_4U | _PAGE_E_4U); 2678 2679 #ifdef CONFIG_DEBUG_PAGEALLOC 2680 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2681 #else 2682 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ 2683 PAGE_OFFSET; 2684 #endif 2685 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | 2686 _PAGE_P_4U | _PAGE_W_4U); 2687 2688 for (i = 1; i < 4; i++) 2689 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2690 2691 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | 2692 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | 2693 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); 2694 2695 2696 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; 2697 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2698 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); 2699 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2700 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2701 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2702 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2703 2704 page_exec_bit = _PAGE_EXEC_4U; 2705 2706 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2707 page_exec_bit); 2708 } 2709 2710 static void __init sun4v_pgprot_init(void) 2711 { 2712 unsigned long page_none, page_shared, page_copy, page_readonly; 2713 unsigned long page_exec_bit; 2714 int i; 2715 2716 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | 2717 page_cache4v_flag | _PAGE_P_4V | 2718 __ACCESS_BITS_4V | __DIRTY_BITS_4V | 2719 _PAGE_EXEC_4V); 2720 PAGE_KERNEL_LOCKED = PAGE_KERNEL; 2721 2722 _PAGE_IE = _PAGE_IE_4V; 2723 _PAGE_E = _PAGE_E_4V; 2724 _PAGE_CACHE = page_cache4v_flag; 2725 2726 #ifdef CONFIG_DEBUG_PAGEALLOC 2727 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2728 #else 2729 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ 2730 PAGE_OFFSET; 2731 #endif 2732 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V | 2733 _PAGE_W_4V); 2734 2735 for (i = 1; i < 4; i++) 2736 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2737 2738 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | 2739 __ACCESS_BITS_4V | _PAGE_E_4V); 2740 2741 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | 2742 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | 2743 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | 2744 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); 2745 2746 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag; 2747 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2748 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); 2749 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2750 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2751 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2752 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2753 2754 page_exec_bit = _PAGE_EXEC_4V; 2755 2756 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2757 page_exec_bit); 2758 } 2759 2760 unsigned long pte_sz_bits(unsigned long sz) 2761 { 2762 if (tlb_type == hypervisor) { 2763 switch (sz) { 2764 case 8 * 1024: 2765 default: 2766 return _PAGE_SZ8K_4V; 2767 case 64 * 1024: 2768 return _PAGE_SZ64K_4V; 2769 case 512 * 1024: 2770 return _PAGE_SZ512K_4V; 2771 case 4 * 1024 * 1024: 2772 return _PAGE_SZ4MB_4V; 2773 } 2774 } else { 2775 switch (sz) { 2776 case 8 * 1024: 2777 default: 2778 return _PAGE_SZ8K_4U; 2779 case 64 * 1024: 2780 return _PAGE_SZ64K_4U; 2781 case 512 * 1024: 2782 return _PAGE_SZ512K_4U; 2783 case 4 * 1024 * 1024: 2784 return _PAGE_SZ4MB_4U; 2785 } 2786 } 2787 } 2788 2789 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) 2790 { 2791 pte_t pte; 2792 2793 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); 2794 pte_val(pte) |= (((unsigned long)space) << 32); 2795 pte_val(pte) |= pte_sz_bits(page_size); 2796 2797 return pte; 2798 } 2799 2800 static unsigned long kern_large_tte(unsigned long paddr) 2801 { 2802 unsigned long val; 2803 2804 val = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2805 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | 2806 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); 2807 if (tlb_type == hypervisor) 2808 val = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2809 page_cache4v_flag | _PAGE_P_4V | 2810 _PAGE_EXEC_4V | _PAGE_W_4V); 2811 2812 return val | paddr; 2813 } 2814 2815 /* If not locked, zap it. */ 2816 void __flush_tlb_all(void) 2817 { 2818 unsigned long pstate; 2819 int i; 2820 2821 __asm__ __volatile__("flushw\n\t" 2822 "rdpr %%pstate, %0\n\t" 2823 "wrpr %0, %1, %%pstate" 2824 : "=r" (pstate) 2825 : "i" (PSTATE_IE)); 2826 if (tlb_type == hypervisor) { 2827 sun4v_mmu_demap_all(); 2828 } else if (tlb_type == spitfire) { 2829 for (i = 0; i < 64; i++) { 2830 /* Spitfire Errata #32 workaround */ 2831 /* NOTE: Always runs on spitfire, so no 2832 * cheetah+ page size encodings. 2833 */ 2834 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2835 "flush %%g6" 2836 : /* No outputs */ 2837 : "r" (0), 2838 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2839 2840 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { 2841 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2842 "membar #Sync" 2843 : /* no outputs */ 2844 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); 2845 spitfire_put_dtlb_data(i, 0x0UL); 2846 } 2847 2848 /* Spitfire Errata #32 workaround */ 2849 /* NOTE: Always runs on spitfire, so no 2850 * cheetah+ page size encodings. 2851 */ 2852 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2853 "flush %%g6" 2854 : /* No outputs */ 2855 : "r" (0), 2856 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2857 2858 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { 2859 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2860 "membar #Sync" 2861 : /* no outputs */ 2862 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); 2863 spitfire_put_itlb_data(i, 0x0UL); 2864 } 2865 } 2866 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 2867 cheetah_flush_dtlb_all(); 2868 cheetah_flush_itlb_all(); 2869 } 2870 __asm__ __volatile__("wrpr %0, 0, %%pstate" 2871 : : "r" (pstate)); 2872 } 2873 2874 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, 2875 unsigned long address) 2876 { 2877 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO); 2878 pte_t *pte = NULL; 2879 2880 if (page) 2881 pte = (pte_t *) page_address(page); 2882 2883 return pte; 2884 } 2885 2886 pgtable_t pte_alloc_one(struct mm_struct *mm, 2887 unsigned long address) 2888 { 2889 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO); 2890 if (!page) 2891 return NULL; 2892 if (!pgtable_page_ctor(page)) { 2893 free_hot_cold_page(page, 0); 2894 return NULL; 2895 } 2896 return (pte_t *) page_address(page); 2897 } 2898 2899 void pte_free_kernel(struct mm_struct *mm, pte_t *pte) 2900 { 2901 free_page((unsigned long)pte); 2902 } 2903 2904 static void __pte_free(pgtable_t pte) 2905 { 2906 struct page *page = virt_to_page(pte); 2907 2908 pgtable_page_dtor(page); 2909 __free_page(page); 2910 } 2911 2912 void pte_free(struct mm_struct *mm, pgtable_t pte) 2913 { 2914 __pte_free(pte); 2915 } 2916 2917 void pgtable_free(void *table, bool is_page) 2918 { 2919 if (is_page) 2920 __pte_free(table); 2921 else 2922 kmem_cache_free(pgtable_cache, table); 2923 } 2924 2925 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 2926 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 2927 pmd_t *pmd) 2928 { 2929 unsigned long pte, flags; 2930 struct mm_struct *mm; 2931 pmd_t entry = *pmd; 2932 2933 if (!pmd_large(entry) || !pmd_young(entry)) 2934 return; 2935 2936 pte = pmd_val(entry); 2937 2938 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ 2939 if (!(pte & _PAGE_VALID)) 2940 return; 2941 2942 /* We are fabricating 8MB pages using 4MB real hw pages. */ 2943 pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); 2944 2945 mm = vma->vm_mm; 2946 2947 spin_lock_irqsave(&mm->context.lock, flags); 2948 2949 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) 2950 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, 2951 addr, pte); 2952 2953 spin_unlock_irqrestore(&mm->context.lock, flags); 2954 } 2955 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 2956 2957 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 2958 static void context_reload(void *__data) 2959 { 2960 struct mm_struct *mm = __data; 2961 2962 if (mm == current->mm) 2963 load_secondary_context(mm); 2964 } 2965 2966 void hugetlb_setup(struct pt_regs *regs) 2967 { 2968 struct mm_struct *mm = current->mm; 2969 struct tsb_config *tp; 2970 2971 if (faulthandler_disabled() || !mm) { 2972 const struct exception_table_entry *entry; 2973 2974 entry = search_exception_tables(regs->tpc); 2975 if (entry) { 2976 regs->tpc = entry->fixup; 2977 regs->tnpc = regs->tpc + 4; 2978 return; 2979 } 2980 pr_alert("Unexpected HugeTLB setup in atomic context.\n"); 2981 die_if_kernel("HugeTSB in atomic", regs); 2982 } 2983 2984 tp = &mm->context.tsb_block[MM_TSB_HUGE]; 2985 if (likely(tp->tsb == NULL)) 2986 tsb_grow(mm, MM_TSB_HUGE, 0); 2987 2988 tsb_context_switch(mm); 2989 smp_tsb_sync(mm); 2990 2991 /* On UltraSPARC-III+ and later, configure the second half of 2992 * the Data-TLB for huge pages. 2993 */ 2994 if (tlb_type == cheetah_plus) { 2995 bool need_context_reload = false; 2996 unsigned long ctx; 2997 2998 spin_lock_irq(&ctx_alloc_lock); 2999 ctx = mm->context.sparc64_ctx_val; 3000 ctx &= ~CTX_PGSZ_MASK; 3001 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; 3002 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; 3003 3004 if (ctx != mm->context.sparc64_ctx_val) { 3005 /* When changing the page size fields, we 3006 * must perform a context flush so that no 3007 * stale entries match. This flush must 3008 * occur with the original context register 3009 * settings. 3010 */ 3011 do_flush_tlb_mm(mm); 3012 3013 /* Reload the context register of all processors 3014 * also executing in this address space. 3015 */ 3016 mm->context.sparc64_ctx_val = ctx; 3017 need_context_reload = true; 3018 } 3019 spin_unlock_irq(&ctx_alloc_lock); 3020 3021 if (need_context_reload) 3022 on_each_cpu(context_reload, mm, 0); 3023 } 3024 } 3025 #endif 3026 3027 static struct resource code_resource = { 3028 .name = "Kernel code", 3029 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3030 }; 3031 3032 static struct resource data_resource = { 3033 .name = "Kernel data", 3034 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3035 }; 3036 3037 static struct resource bss_resource = { 3038 .name = "Kernel bss", 3039 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3040 }; 3041 3042 static inline resource_size_t compute_kern_paddr(void *addr) 3043 { 3044 return (resource_size_t) (addr - KERNBASE + kern_base); 3045 } 3046 3047 static void __init kernel_lds_init(void) 3048 { 3049 code_resource.start = compute_kern_paddr(_text); 3050 code_resource.end = compute_kern_paddr(_etext - 1); 3051 data_resource.start = compute_kern_paddr(_etext); 3052 data_resource.end = compute_kern_paddr(_edata - 1); 3053 bss_resource.start = compute_kern_paddr(__bss_start); 3054 bss_resource.end = compute_kern_paddr(_end - 1); 3055 } 3056 3057 static int __init report_memory(void) 3058 { 3059 int i; 3060 struct resource *res; 3061 3062 kernel_lds_init(); 3063 3064 for (i = 0; i < pavail_ents; i++) { 3065 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 3066 3067 if (!res) { 3068 pr_warn("Failed to allocate source.\n"); 3069 break; 3070 } 3071 3072 res->name = "System RAM"; 3073 res->start = pavail[i].phys_addr; 3074 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; 3075 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM; 3076 3077 if (insert_resource(&iomem_resource, res) < 0) { 3078 pr_warn("Resource insertion failed.\n"); 3079 break; 3080 } 3081 3082 insert_resource(res, &code_resource); 3083 insert_resource(res, &data_resource); 3084 insert_resource(res, &bss_resource); 3085 } 3086 3087 return 0; 3088 } 3089 arch_initcall(report_memory); 3090 3091 #ifdef CONFIG_SMP 3092 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range 3093 #else 3094 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range 3095 #endif 3096 3097 void flush_tlb_kernel_range(unsigned long start, unsigned long end) 3098 { 3099 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { 3100 if (start < LOW_OBP_ADDRESS) { 3101 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); 3102 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); 3103 } 3104 if (end > HI_OBP_ADDRESS) { 3105 flush_tsb_kernel_range(HI_OBP_ADDRESS, end); 3106 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end); 3107 } 3108 } else { 3109 flush_tsb_kernel_range(start, end); 3110 do_flush_tlb_kernel_range(start, end); 3111 } 3112 } 3113