1 // SPDX-License-Identifier: GPL-2.0 2 /* time.c: UltraSparc timer and TOD clock support. 3 * 4 * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net) 5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 6 * 7 * Based largely on code which is: 8 * 9 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) 10 */ 11 12 #include <linux/errno.h> 13 #include <linux/export.h> 14 #include <linux/sched.h> 15 #include <linux/kernel.h> 16 #include <linux/param.h> 17 #include <linux/string.h> 18 #include <linux/mm.h> 19 #include <linux/interrupt.h> 20 #include <linux/time.h> 21 #include <linux/timex.h> 22 #include <linux/init.h> 23 #include <linux/ioport.h> 24 #include <linux/mc146818rtc.h> 25 #include <linux/delay.h> 26 #include <linux/profile.h> 27 #include <linux/bcd.h> 28 #include <linux/jiffies.h> 29 #include <linux/cpufreq.h> 30 #include <linux/percpu.h> 31 #include <linux/rtc/m48t59.h> 32 #include <linux/kernel_stat.h> 33 #include <linux/clockchips.h> 34 #include <linux/clocksource.h> 35 #include <linux/platform_device.h> 36 #include <linux/ftrace.h> 37 38 #include <asm/oplib.h> 39 #include <asm/timer.h> 40 #include <asm/irq.h> 41 #include <asm/io.h> 42 #include <asm/prom.h> 43 #include <asm/starfire.h> 44 #include <asm/smp.h> 45 #include <asm/sections.h> 46 #include <asm/cpudata.h> 47 #include <linux/uaccess.h> 48 #include <asm/irq_regs.h> 49 #include <asm/cacheflush.h> 50 51 #include "entry.h" 52 #include "kernel.h" 53 54 DEFINE_SPINLOCK(rtc_lock); 55 56 unsigned int __read_mostly vdso_fix_stick; 57 58 #ifdef CONFIG_SMP 59 unsigned long profile_pc(struct pt_regs *regs) 60 { 61 unsigned long pc = instruction_pointer(regs); 62 63 if (in_lock_functions(pc)) 64 return regs->u_regs[UREG_RETPC]; 65 return pc; 66 } 67 EXPORT_SYMBOL(profile_pc); 68 #endif 69 70 static void tick_disable_protection(void) 71 { 72 /* Set things up so user can access tick register for profiling 73 * purposes. Also workaround BB_ERRATA_1 by doing a dummy 74 * read back of %tick after writing it. 75 */ 76 __asm__ __volatile__( 77 " ba,pt %%xcc, 1f\n" 78 " nop\n" 79 " .align 64\n" 80 "1: rd %%tick, %%g2\n" 81 " add %%g2, 6, %%g2\n" 82 " andn %%g2, %0, %%g2\n" 83 " wrpr %%g2, 0, %%tick\n" 84 " rdpr %%tick, %%g0" 85 : /* no outputs */ 86 : "r" (TICK_PRIV_BIT) 87 : "g2"); 88 } 89 90 static void tick_disable_irq(void) 91 { 92 __asm__ __volatile__( 93 " ba,pt %%xcc, 1f\n" 94 " nop\n" 95 " .align 64\n" 96 "1: wr %0, 0x0, %%tick_cmpr\n" 97 " rd %%tick_cmpr, %%g0" 98 : /* no outputs */ 99 : "r" (TICKCMP_IRQ_BIT)); 100 } 101 102 static void tick_init_tick(void) 103 { 104 tick_disable_protection(); 105 tick_disable_irq(); 106 } 107 108 static unsigned long long tick_get_tick(void) 109 { 110 unsigned long ret; 111 112 __asm__ __volatile__("rd %%tick, %0\n\t" 113 "mov %0, %0" 114 : "=r" (ret)); 115 116 return ret & ~TICK_PRIV_BIT; 117 } 118 119 static int tick_add_compare(unsigned long adj) 120 { 121 unsigned long orig_tick, new_tick, new_compare; 122 123 __asm__ __volatile__("rd %%tick, %0" 124 : "=r" (orig_tick)); 125 126 orig_tick &= ~TICKCMP_IRQ_BIT; 127 128 /* Workaround for Spitfire Errata (#54 I think??), I discovered 129 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch 130 * number 103640. 131 * 132 * On Blackbird writes to %tick_cmpr can fail, the 133 * workaround seems to be to execute the wr instruction 134 * at the start of an I-cache line, and perform a dummy 135 * read back from %tick_cmpr right after writing to it. -DaveM 136 */ 137 __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" 138 " add %1, %2, %0\n\t" 139 ".align 64\n" 140 "1:\n\t" 141 "wr %0, 0, %%tick_cmpr\n\t" 142 "rd %%tick_cmpr, %%g0\n\t" 143 : "=r" (new_compare) 144 : "r" (orig_tick), "r" (adj)); 145 146 __asm__ __volatile__("rd %%tick, %0" 147 : "=r" (new_tick)); 148 new_tick &= ~TICKCMP_IRQ_BIT; 149 150 return ((long)(new_tick - (orig_tick+adj))) > 0L; 151 } 152 153 static unsigned long tick_add_tick(unsigned long adj) 154 { 155 unsigned long new_tick; 156 157 /* Also need to handle Blackbird bug here too. */ 158 __asm__ __volatile__("rd %%tick, %0\n\t" 159 "add %0, %1, %0\n\t" 160 "wrpr %0, 0, %%tick\n\t" 161 : "=&r" (new_tick) 162 : "r" (adj)); 163 164 return new_tick; 165 } 166 167 /* Searches for cpu clock frequency with given cpuid in OpenBoot tree */ 168 static unsigned long cpuid_to_freq(phandle node, int cpuid) 169 { 170 bool is_cpu_node = false; 171 unsigned long freq = 0; 172 char type[128]; 173 174 if (!node) 175 return freq; 176 177 if (prom_getproperty(node, "device_type", type, sizeof(type)) != -1) 178 is_cpu_node = (strcmp(type, "cpu") == 0); 179 180 /* try upa-portid then cpuid to get cpuid, see prom_64.c */ 181 if (is_cpu_node && (prom_getint(node, "upa-portid") == cpuid || 182 prom_getint(node, "cpuid") == cpuid)) 183 freq = prom_getintdefault(node, "clock-frequency", 0); 184 if (!freq) 185 freq = cpuid_to_freq(prom_getchild(node), cpuid); 186 if (!freq) 187 freq = cpuid_to_freq(prom_getsibling(node), cpuid); 188 189 return freq; 190 } 191 192 static unsigned long tick_get_frequency(void) 193 { 194 return cpuid_to_freq(prom_root_node, hard_smp_processor_id()); 195 } 196 197 static struct sparc64_tick_ops tick_operations __cacheline_aligned = { 198 .name = "tick", 199 .init_tick = tick_init_tick, 200 .disable_irq = tick_disable_irq, 201 .get_tick = tick_get_tick, 202 .add_tick = tick_add_tick, 203 .add_compare = tick_add_compare, 204 .get_frequency = tick_get_frequency, 205 .softint_mask = 1UL << 0, 206 }; 207 208 struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations; 209 EXPORT_SYMBOL(tick_ops); 210 211 static void stick_disable_irq(void) 212 { 213 __asm__ __volatile__( 214 "wr %0, 0x0, %%asr25" 215 : /* no outputs */ 216 : "r" (TICKCMP_IRQ_BIT)); 217 } 218 219 static void stick_init_tick(void) 220 { 221 /* Writes to the %tick and %stick register are not 222 * allowed on sun4v. The Hypervisor controls that 223 * bit, per-strand. 224 */ 225 if (tlb_type != hypervisor) { 226 tick_disable_protection(); 227 tick_disable_irq(); 228 229 /* Let the user get at STICK too. */ 230 __asm__ __volatile__( 231 " rd %%asr24, %%g2\n" 232 " andn %%g2, %0, %%g2\n" 233 " wr %%g2, 0, %%asr24" 234 : /* no outputs */ 235 : "r" (TICK_PRIV_BIT) 236 : "g1", "g2"); 237 } 238 239 stick_disable_irq(); 240 } 241 242 static unsigned long long stick_get_tick(void) 243 { 244 unsigned long ret; 245 246 __asm__ __volatile__("rd %%asr24, %0" 247 : "=r" (ret)); 248 249 return ret & ~TICK_PRIV_BIT; 250 } 251 252 static unsigned long stick_add_tick(unsigned long adj) 253 { 254 unsigned long new_tick; 255 256 __asm__ __volatile__("rd %%asr24, %0\n\t" 257 "add %0, %1, %0\n\t" 258 "wr %0, 0, %%asr24\n\t" 259 : "=&r" (new_tick) 260 : "r" (adj)); 261 262 return new_tick; 263 } 264 265 static int stick_add_compare(unsigned long adj) 266 { 267 unsigned long orig_tick, new_tick; 268 269 __asm__ __volatile__("rd %%asr24, %0" 270 : "=r" (orig_tick)); 271 orig_tick &= ~TICKCMP_IRQ_BIT; 272 273 __asm__ __volatile__("wr %0, 0, %%asr25" 274 : /* no outputs */ 275 : "r" (orig_tick + adj)); 276 277 __asm__ __volatile__("rd %%asr24, %0" 278 : "=r" (new_tick)); 279 new_tick &= ~TICKCMP_IRQ_BIT; 280 281 return ((long)(new_tick - (orig_tick+adj))) > 0L; 282 } 283 284 static unsigned long stick_get_frequency(void) 285 { 286 return prom_getintdefault(prom_root_node, "stick-frequency", 0); 287 } 288 289 static struct sparc64_tick_ops stick_operations __read_mostly = { 290 .name = "stick", 291 .init_tick = stick_init_tick, 292 .disable_irq = stick_disable_irq, 293 .get_tick = stick_get_tick, 294 .add_tick = stick_add_tick, 295 .add_compare = stick_add_compare, 296 .get_frequency = stick_get_frequency, 297 .softint_mask = 1UL << 16, 298 }; 299 300 /* On Hummingbird the STICK/STICK_CMPR register is implemented 301 * in I/O space. There are two 64-bit registers each, the 302 * first holds the low 32-bits of the value and the second holds 303 * the high 32-bits. 304 * 305 * Since STICK is constantly updating, we have to access it carefully. 306 * 307 * The sequence we use to read is: 308 * 1) read high 309 * 2) read low 310 * 3) read high again, if it rolled re-read both low and high again. 311 * 312 * Writing STICK safely is also tricky: 313 * 1) write low to zero 314 * 2) write high 315 * 3) write low 316 */ 317 static unsigned long __hbird_read_stick(void) 318 { 319 unsigned long ret, tmp1, tmp2, tmp3; 320 unsigned long addr = HBIRD_STICK_ADDR+8; 321 322 __asm__ __volatile__("ldxa [%1] %5, %2\n" 323 "1:\n\t" 324 "sub %1, 0x8, %1\n\t" 325 "ldxa [%1] %5, %3\n\t" 326 "add %1, 0x8, %1\n\t" 327 "ldxa [%1] %5, %4\n\t" 328 "cmp %4, %2\n\t" 329 "bne,a,pn %%xcc, 1b\n\t" 330 " mov %4, %2\n\t" 331 "sllx %4, 32, %4\n\t" 332 "or %3, %4, %0\n\t" 333 : "=&r" (ret), "=&r" (addr), 334 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3) 335 : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr)); 336 337 return ret; 338 } 339 340 static void __hbird_write_stick(unsigned long val) 341 { 342 unsigned long low = (val & 0xffffffffUL); 343 unsigned long high = (val >> 32UL); 344 unsigned long addr = HBIRD_STICK_ADDR; 345 346 __asm__ __volatile__("stxa %%g0, [%0] %4\n\t" 347 "add %0, 0x8, %0\n\t" 348 "stxa %3, [%0] %4\n\t" 349 "sub %0, 0x8, %0\n\t" 350 "stxa %2, [%0] %4" 351 : "=&r" (addr) 352 : "0" (addr), "r" (low), "r" (high), 353 "i" (ASI_PHYS_BYPASS_EC_E)); 354 } 355 356 static void __hbird_write_compare(unsigned long val) 357 { 358 unsigned long low = (val & 0xffffffffUL); 359 unsigned long high = (val >> 32UL); 360 unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL; 361 362 __asm__ __volatile__("stxa %3, [%0] %4\n\t" 363 "sub %0, 0x8, %0\n\t" 364 "stxa %2, [%0] %4" 365 : "=&r" (addr) 366 : "0" (addr), "r" (low), "r" (high), 367 "i" (ASI_PHYS_BYPASS_EC_E)); 368 } 369 370 static void hbtick_disable_irq(void) 371 { 372 __hbird_write_compare(TICKCMP_IRQ_BIT); 373 } 374 375 static void hbtick_init_tick(void) 376 { 377 tick_disable_protection(); 378 379 /* XXX This seems to be necessary to 'jumpstart' Hummingbird 380 * XXX into actually sending STICK interrupts. I think because 381 * XXX of how we store %tick_cmpr in head.S this somehow resets the 382 * XXX {TICK + STICK} interrupt mux. -DaveM 383 */ 384 __hbird_write_stick(__hbird_read_stick()); 385 386 hbtick_disable_irq(); 387 } 388 389 static unsigned long long hbtick_get_tick(void) 390 { 391 return __hbird_read_stick() & ~TICK_PRIV_BIT; 392 } 393 394 static unsigned long hbtick_add_tick(unsigned long adj) 395 { 396 unsigned long val; 397 398 val = __hbird_read_stick() + adj; 399 __hbird_write_stick(val); 400 401 return val; 402 } 403 404 static int hbtick_add_compare(unsigned long adj) 405 { 406 unsigned long val = __hbird_read_stick(); 407 unsigned long val2; 408 409 val &= ~TICKCMP_IRQ_BIT; 410 val += adj; 411 __hbird_write_compare(val); 412 413 val2 = __hbird_read_stick() & ~TICKCMP_IRQ_BIT; 414 415 return ((long)(val2 - val)) > 0L; 416 } 417 418 static unsigned long hbtick_get_frequency(void) 419 { 420 return prom_getintdefault(prom_root_node, "stick-frequency", 0); 421 } 422 423 static struct sparc64_tick_ops hbtick_operations __read_mostly = { 424 .name = "hbtick", 425 .init_tick = hbtick_init_tick, 426 .disable_irq = hbtick_disable_irq, 427 .get_tick = hbtick_get_tick, 428 .add_tick = hbtick_add_tick, 429 .add_compare = hbtick_add_compare, 430 .get_frequency = hbtick_get_frequency, 431 .softint_mask = 1UL << 0, 432 }; 433 434 unsigned long cmos_regs; 435 EXPORT_SYMBOL(cmos_regs); 436 437 static struct resource rtc_cmos_resource; 438 439 static struct platform_device rtc_cmos_device = { 440 .name = "rtc_cmos", 441 .id = -1, 442 .resource = &rtc_cmos_resource, 443 .num_resources = 1, 444 }; 445 446 static int rtc_probe(struct platform_device *op) 447 { 448 struct resource *r; 449 450 printk(KERN_INFO "%s: RTC regs at 0x%llx\n", 451 op->dev.of_node->full_name, op->resource[0].start); 452 453 /* The CMOS RTC driver only accepts IORESOURCE_IO, so cons 454 * up a fake resource so that the probe works for all cases. 455 * When the RTC is behind an ISA bus it will have IORESOURCE_IO 456 * already, whereas when it's behind EBUS is will be IORESOURCE_MEM. 457 */ 458 459 r = &rtc_cmos_resource; 460 r->flags = IORESOURCE_IO; 461 r->name = op->resource[0].name; 462 r->start = op->resource[0].start; 463 r->end = op->resource[0].end; 464 465 cmos_regs = op->resource[0].start; 466 return platform_device_register(&rtc_cmos_device); 467 } 468 469 static const struct of_device_id rtc_match[] = { 470 { 471 .name = "rtc", 472 .compatible = "m5819", 473 }, 474 { 475 .name = "rtc", 476 .compatible = "isa-m5819p", 477 }, 478 { 479 .name = "rtc", 480 .compatible = "isa-m5823p", 481 }, 482 { 483 .name = "rtc", 484 .compatible = "ds1287", 485 }, 486 {}, 487 }; 488 489 static struct platform_driver rtc_driver = { 490 .probe = rtc_probe, 491 .driver = { 492 .name = "rtc", 493 .of_match_table = rtc_match, 494 }, 495 }; 496 497 static struct platform_device rtc_bq4802_device = { 498 .name = "rtc-bq4802", 499 .id = -1, 500 .num_resources = 1, 501 }; 502 503 static int bq4802_probe(struct platform_device *op) 504 { 505 506 printk(KERN_INFO "%s: BQ4802 regs at 0x%llx\n", 507 op->dev.of_node->full_name, op->resource[0].start); 508 509 rtc_bq4802_device.resource = &op->resource[0]; 510 return platform_device_register(&rtc_bq4802_device); 511 } 512 513 static const struct of_device_id bq4802_match[] = { 514 { 515 .name = "rtc", 516 .compatible = "bq4802", 517 }, 518 {}, 519 }; 520 521 static struct platform_driver bq4802_driver = { 522 .probe = bq4802_probe, 523 .driver = { 524 .name = "bq4802", 525 .of_match_table = bq4802_match, 526 }, 527 }; 528 529 static unsigned char mostek_read_byte(struct device *dev, u32 ofs) 530 { 531 struct platform_device *pdev = to_platform_device(dev); 532 void __iomem *regs = (void __iomem *) pdev->resource[0].start; 533 534 return readb(regs + ofs); 535 } 536 537 static void mostek_write_byte(struct device *dev, u32 ofs, u8 val) 538 { 539 struct platform_device *pdev = to_platform_device(dev); 540 void __iomem *regs = (void __iomem *) pdev->resource[0].start; 541 542 writeb(val, regs + ofs); 543 } 544 545 static struct m48t59_plat_data m48t59_data = { 546 .read_byte = mostek_read_byte, 547 .write_byte = mostek_write_byte, 548 }; 549 550 static struct platform_device m48t59_rtc = { 551 .name = "rtc-m48t59", 552 .id = 0, 553 .num_resources = 1, 554 .dev = { 555 .platform_data = &m48t59_data, 556 }, 557 }; 558 559 static int mostek_probe(struct platform_device *op) 560 { 561 struct device_node *dp = op->dev.of_node; 562 563 /* On an Enterprise system there can be multiple mostek clocks. 564 * We should only match the one that is on the central FHC bus. 565 */ 566 if (!strcmp(dp->parent->name, "fhc") && 567 strcmp(dp->parent->parent->name, "central") != 0) 568 return -ENODEV; 569 570 printk(KERN_INFO "%s: Mostek regs at 0x%llx\n", 571 dp->full_name, op->resource[0].start); 572 573 m48t59_rtc.resource = &op->resource[0]; 574 return platform_device_register(&m48t59_rtc); 575 } 576 577 static const struct of_device_id mostek_match[] = { 578 { 579 .name = "eeprom", 580 }, 581 {}, 582 }; 583 584 static struct platform_driver mostek_driver = { 585 .probe = mostek_probe, 586 .driver = { 587 .name = "mostek", 588 .of_match_table = mostek_match, 589 }, 590 }; 591 592 static struct platform_device rtc_sun4v_device = { 593 .name = "rtc-sun4v", 594 .id = -1, 595 }; 596 597 static struct platform_device rtc_starfire_device = { 598 .name = "rtc-starfire", 599 .id = -1, 600 }; 601 602 static int __init clock_init(void) 603 { 604 if (this_is_starfire) 605 return platform_device_register(&rtc_starfire_device); 606 607 if (tlb_type == hypervisor) 608 return platform_device_register(&rtc_sun4v_device); 609 610 (void) platform_driver_register(&rtc_driver); 611 (void) platform_driver_register(&mostek_driver); 612 (void) platform_driver_register(&bq4802_driver); 613 614 return 0; 615 } 616 617 /* Must be after subsys_initcall() so that busses are probed. Must 618 * be before device_initcall() because things like the RTC driver 619 * need to see the clock registers. 620 */ 621 fs_initcall(clock_init); 622 623 /* Return true if this is Hummingbird, aka Ultra-IIe */ 624 static bool is_hummingbird(void) 625 { 626 unsigned long ver, manuf, impl; 627 628 __asm__ __volatile__ ("rdpr %%ver, %0" 629 : "=&r" (ver)); 630 manuf = ((ver >> 48) & 0xffff); 631 impl = ((ver >> 32) & 0xffff); 632 633 return (manuf == 0x17 && impl == 0x13); 634 } 635 636 struct freq_table { 637 unsigned long clock_tick_ref; 638 unsigned int ref_freq; 639 }; 640 static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0 }; 641 642 unsigned long sparc64_get_clock_tick(unsigned int cpu) 643 { 644 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu); 645 646 if (ft->clock_tick_ref) 647 return ft->clock_tick_ref; 648 return cpu_data(cpu).clock_tick; 649 } 650 EXPORT_SYMBOL(sparc64_get_clock_tick); 651 652 #ifdef CONFIG_CPU_FREQ 653 654 static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 655 void *data) 656 { 657 struct cpufreq_freqs *freq = data; 658 unsigned int cpu = freq->cpu; 659 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu); 660 661 if (!ft->ref_freq) { 662 ft->ref_freq = freq->old; 663 ft->clock_tick_ref = cpu_data(cpu).clock_tick; 664 } 665 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 666 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { 667 cpu_data(cpu).clock_tick = 668 cpufreq_scale(ft->clock_tick_ref, 669 ft->ref_freq, 670 freq->new); 671 } 672 673 return 0; 674 } 675 676 static struct notifier_block sparc64_cpufreq_notifier_block = { 677 .notifier_call = sparc64_cpufreq_notifier 678 }; 679 680 static int __init register_sparc64_cpufreq_notifier(void) 681 { 682 683 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block, 684 CPUFREQ_TRANSITION_NOTIFIER); 685 return 0; 686 } 687 688 core_initcall(register_sparc64_cpufreq_notifier); 689 690 #endif /* CONFIG_CPU_FREQ */ 691 692 static int sparc64_next_event(unsigned long delta, 693 struct clock_event_device *evt) 694 { 695 return tick_operations.add_compare(delta) ? -ETIME : 0; 696 } 697 698 static int sparc64_timer_shutdown(struct clock_event_device *evt) 699 { 700 tick_operations.disable_irq(); 701 return 0; 702 } 703 704 static struct clock_event_device sparc64_clockevent = { 705 .features = CLOCK_EVT_FEAT_ONESHOT, 706 .set_state_shutdown = sparc64_timer_shutdown, 707 .set_next_event = sparc64_next_event, 708 .rating = 100, 709 .shift = 30, 710 .irq = -1, 711 }; 712 static DEFINE_PER_CPU(struct clock_event_device, sparc64_events); 713 714 void __irq_entry timer_interrupt(int irq, struct pt_regs *regs) 715 { 716 struct pt_regs *old_regs = set_irq_regs(regs); 717 unsigned long tick_mask = tick_operations.softint_mask; 718 int cpu = smp_processor_id(); 719 struct clock_event_device *evt = &per_cpu(sparc64_events, cpu); 720 721 clear_softint(tick_mask); 722 723 irq_enter(); 724 725 local_cpu_data().irq0_irqs++; 726 kstat_incr_irq_this_cpu(0); 727 728 if (unlikely(!evt->event_handler)) { 729 printk(KERN_WARNING 730 "Spurious SPARC64 timer interrupt on cpu %d\n", cpu); 731 } else 732 evt->event_handler(evt); 733 734 irq_exit(); 735 736 set_irq_regs(old_regs); 737 } 738 739 void setup_sparc64_timer(void) 740 { 741 struct clock_event_device *sevt; 742 unsigned long pstate; 743 744 /* Guarantee that the following sequences execute 745 * uninterrupted. 746 */ 747 __asm__ __volatile__("rdpr %%pstate, %0\n\t" 748 "wrpr %0, %1, %%pstate" 749 : "=r" (pstate) 750 : "i" (PSTATE_IE)); 751 752 tick_operations.init_tick(); 753 754 /* Restore PSTATE_IE. */ 755 __asm__ __volatile__("wrpr %0, 0x0, %%pstate" 756 : /* no outputs */ 757 : "r" (pstate)); 758 759 sevt = this_cpu_ptr(&sparc64_events); 760 761 memcpy(sevt, &sparc64_clockevent, sizeof(*sevt)); 762 sevt->cpumask = cpumask_of(smp_processor_id()); 763 764 clockevents_register_device(sevt); 765 } 766 767 #define SPARC64_NSEC_PER_CYC_SHIFT 10UL 768 769 static struct clocksource clocksource_tick = { 770 .rating = 100, 771 .mask = CLOCKSOURCE_MASK(64), 772 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 773 }; 774 775 static unsigned long tb_ticks_per_usec __read_mostly; 776 777 void __delay(unsigned long loops) 778 { 779 unsigned long bclock = get_tick(); 780 781 while ((get_tick() - bclock) < loops) 782 ; 783 } 784 EXPORT_SYMBOL(__delay); 785 786 void udelay(unsigned long usecs) 787 { 788 __delay(tb_ticks_per_usec * usecs); 789 } 790 EXPORT_SYMBOL(udelay); 791 792 static u64 clocksource_tick_read(struct clocksource *cs) 793 { 794 return get_tick(); 795 } 796 797 static void __init get_tick_patch(void) 798 { 799 unsigned int *addr, *instr, i; 800 struct get_tick_patch *p; 801 802 if (tlb_type == spitfire && is_hummingbird()) 803 return; 804 805 for (p = &__get_tick_patch; p < &__get_tick_patch_end; p++) { 806 instr = (tlb_type == spitfire) ? p->tick : p->stick; 807 addr = (unsigned int *)(unsigned long)p->addr; 808 for (i = 0; i < GET_TICK_NINSTR; i++) { 809 addr[i] = instr[i]; 810 /* ensure that address is modified before flush */ 811 wmb(); 812 flushi(&addr[i]); 813 } 814 } 815 } 816 817 static void init_tick_ops(struct sparc64_tick_ops *ops) 818 { 819 unsigned long freq, quotient, tick; 820 821 freq = ops->get_frequency(); 822 quotient = clocksource_hz2mult(freq, SPARC64_NSEC_PER_CYC_SHIFT); 823 tick = ops->get_tick(); 824 825 ops->offset = (tick * quotient) >> SPARC64_NSEC_PER_CYC_SHIFT; 826 ops->ticks_per_nsec_quotient = quotient; 827 ops->frequency = freq; 828 tick_operations = *ops; 829 get_tick_patch(); 830 } 831 832 void __init time_init_early(void) 833 { 834 if (tlb_type == spitfire) { 835 if (is_hummingbird()) { 836 init_tick_ops(&hbtick_operations); 837 clocksource_tick.archdata.vclock_mode = VCLOCK_NONE; 838 } else { 839 init_tick_ops(&tick_operations); 840 clocksource_tick.archdata.vclock_mode = VCLOCK_TICK; 841 vdso_fix_stick = 1; 842 } 843 } else { 844 init_tick_ops(&stick_operations); 845 clocksource_tick.archdata.vclock_mode = VCLOCK_STICK; 846 } 847 } 848 849 void __init time_init(void) 850 { 851 unsigned long freq; 852 853 freq = tick_operations.frequency; 854 tb_ticks_per_usec = freq / USEC_PER_SEC; 855 856 clocksource_tick.name = tick_operations.name; 857 clocksource_tick.read = clocksource_tick_read; 858 859 clocksource_register_hz(&clocksource_tick, freq); 860 printk("clocksource: mult[%x] shift[%d]\n", 861 clocksource_tick.mult, clocksource_tick.shift); 862 863 sparc64_clockevent.name = tick_operations.name; 864 clockevents_calc_mult_shift(&sparc64_clockevent, freq, 4); 865 866 sparc64_clockevent.max_delta_ns = 867 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent); 868 sparc64_clockevent.max_delta_ticks = 0x7fffffffffffffffUL; 869 sparc64_clockevent.min_delta_ns = 870 clockevent_delta2ns(0xF, &sparc64_clockevent); 871 sparc64_clockevent.min_delta_ticks = 0xF; 872 873 printk("clockevent: mult[%x] shift[%d]\n", 874 sparc64_clockevent.mult, sparc64_clockevent.shift); 875 876 setup_sparc64_timer(); 877 } 878 879 unsigned long long sched_clock(void) 880 { 881 unsigned long quotient = tick_operations.ticks_per_nsec_quotient; 882 unsigned long offset = tick_operations.offset; 883 884 /* Use barrier so the compiler emits the loads first and overlaps load 885 * latency with reading tick, because reading %tick/%stick is a 886 * post-sync instruction that will flush and restart subsequent 887 * instructions after it commits. 888 */ 889 barrier(); 890 891 return ((get_tick() * quotient) >> SPARC64_NSEC_PER_CYC_SHIFT) - offset; 892 } 893 894 int read_current_timer(unsigned long *timer_val) 895 { 896 *timer_val = get_tick(); 897 return 0; 898 } 899