1 // SPDX-License-Identifier: GPL-2.0 2 /* psycho_common.c: Code common to PSYCHO and derivative PCI controllers. 3 * 4 * Copyright (C) 2008 David S. Miller <davem@davemloft.net> 5 */ 6 #include <linux/kernel.h> 7 #include <linux/interrupt.h> 8 9 #include <asm/upa.h> 10 11 #include "pci_impl.h" 12 #include "iommu_common.h" 13 #include "psycho_common.h" 14 15 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002ULL 16 #define PSYCHO_STCERR_WRITE 0x0000000000000002ULL 17 #define PSYCHO_STCERR_READ 0x0000000000000001ULL 18 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000ULL 19 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000ULL 20 #define PSYCHO_STCTAG_VALID 0x0000000000000002ULL 21 #define PSYCHO_STCTAG_WRITE 0x0000000000000001ULL 22 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000ULL 23 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000ULL 24 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00ULL 25 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcULL 26 #define PSYCHO_STCLINE_VALID 0x0000000000000002ULL 27 #define PSYCHO_STCLINE_FOFN 0x0000000000000001ULL 28 29 static DEFINE_SPINLOCK(stc_buf_lock); 30 static unsigned long stc_error_buf[128]; 31 static unsigned long stc_tag_buf[16]; 32 static unsigned long stc_line_buf[16]; 33 34 static void psycho_check_stc_error(struct pci_pbm_info *pbm) 35 { 36 unsigned long err_base, tag_base, line_base; 37 struct strbuf *strbuf = &pbm->stc; 38 u64 control; 39 int i; 40 41 if (!strbuf->strbuf_control) 42 return; 43 44 err_base = strbuf->strbuf_err_stat; 45 tag_base = strbuf->strbuf_tag_diag; 46 line_base = strbuf->strbuf_line_diag; 47 48 spin_lock(&stc_buf_lock); 49 50 /* This is __REALLY__ dangerous. When we put the streaming 51 * buffer into diagnostic mode to probe it's tags and error 52 * status, we _must_ clear all of the line tag valid bits 53 * before re-enabling the streaming buffer. If any dirty data 54 * lives in the STC when we do this, we will end up 55 * invalidating it before it has a chance to reach main 56 * memory. 57 */ 58 control = upa_readq(strbuf->strbuf_control); 59 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); 60 for (i = 0; i < 128; i++) { 61 u64 val; 62 63 val = upa_readq(err_base + (i * 8UL)); 64 upa_writeq(0UL, err_base + (i * 8UL)); 65 stc_error_buf[i] = val; 66 } 67 for (i = 0; i < 16; i++) { 68 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL)); 69 stc_line_buf[i] = upa_readq(line_base + (i * 8UL)); 70 upa_writeq(0UL, tag_base + (i * 8UL)); 71 upa_writeq(0UL, line_base + (i * 8UL)); 72 } 73 74 /* OK, state is logged, exit diagnostic mode. */ 75 upa_writeq(control, strbuf->strbuf_control); 76 77 for (i = 0; i < 16; i++) { 78 int j, saw_error, first, last; 79 80 saw_error = 0; 81 first = i * 8; 82 last = first + 8; 83 for (j = first; j < last; j++) { 84 u64 errval = stc_error_buf[j]; 85 if (errval != 0) { 86 saw_error++; 87 printk(KERN_ERR "%s: STC_ERR(%d)[wr(%d)" 88 "rd(%d)]\n", 89 pbm->name, 90 j, 91 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0, 92 (errval & PSYCHO_STCERR_READ) ? 1 : 0); 93 } 94 } 95 if (saw_error != 0) { 96 u64 tagval = stc_tag_buf[i]; 97 u64 lineval = stc_line_buf[i]; 98 printk(KERN_ERR "%s: STC_TAG(%d)[PA(%016llx)VA(%08llx)" 99 "V(%d)W(%d)]\n", 100 pbm->name, 101 i, 102 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL), 103 (tagval & PSYCHO_STCTAG_VPN), 104 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0), 105 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0)); 106 printk(KERN_ERR "%s: STC_LINE(%d)[LIDX(%llx)SP(%llx)" 107 "LADDR(%llx)EP(%llx)V(%d)FOFN(%d)]\n", 108 pbm->name, 109 i, 110 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL), 111 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL), 112 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL), 113 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL), 114 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0), 115 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0)); 116 } 117 } 118 119 spin_unlock(&stc_buf_lock); 120 } 121 122 #define PSYCHO_IOMMU_TAG 0xa580UL 123 #define PSYCHO_IOMMU_DATA 0xa600UL 124 125 static void psycho_record_iommu_tags_and_data(struct pci_pbm_info *pbm, 126 u64 *tag, u64 *data) 127 { 128 int i; 129 130 for (i = 0; i < 16; i++) { 131 unsigned long base = pbm->controller_regs; 132 unsigned long off = i * 8UL; 133 134 tag[i] = upa_readq(base + PSYCHO_IOMMU_TAG+off); 135 data[i] = upa_readq(base + PSYCHO_IOMMU_DATA+off); 136 137 /* Now clear out the entry. */ 138 upa_writeq(0, base + PSYCHO_IOMMU_TAG + off); 139 upa_writeq(0, base + PSYCHO_IOMMU_DATA + off); 140 } 141 } 142 143 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL) 144 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL) 145 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL) 146 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL) 147 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL) 148 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffULL 149 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL) 150 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL) 151 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffULL 152 153 static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm, 154 u64 *tag, u64 *data) 155 { 156 int i; 157 158 for (i = 0; i < 16; i++) { 159 u64 tag_val, data_val; 160 const char *type_str; 161 tag_val = tag[i]; 162 if (!(tag_val & PSYCHO_IOMMU_TAG_ERR)) 163 continue; 164 165 data_val = data[i]; 166 switch((tag_val & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) { 167 case 0: 168 type_str = "Protection Error"; 169 break; 170 case 1: 171 type_str = "Invalid Error"; 172 break; 173 case 2: 174 type_str = "TimeOut Error"; 175 break; 176 case 3: 177 default: 178 type_str = "ECC Error"; 179 break; 180 } 181 182 printk(KERN_ERR "%s: IOMMU TAG(%d)[error(%s) wr(%d) " 183 "str(%d) sz(%dK) vpg(%08llx)]\n", 184 pbm->name, i, type_str, 185 ((tag_val & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0), 186 ((tag_val & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0), 187 ((tag_val & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8), 188 (tag_val & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); 189 printk(KERN_ERR "%s: IOMMU DATA(%d)[valid(%d) cache(%d) " 190 "ppg(%016llx)]\n", 191 pbm->name, i, 192 ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0), 193 ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0), 194 (data_val & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); 195 } 196 } 197 198 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL 199 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL 200 201 void psycho_check_iommu_error(struct pci_pbm_info *pbm, 202 unsigned long afsr, 203 unsigned long afar, 204 enum psycho_error_type type) 205 { 206 u64 control, iommu_tag[16], iommu_data[16]; 207 struct iommu *iommu = pbm->iommu; 208 unsigned long flags; 209 210 spin_lock_irqsave(&iommu->lock, flags); 211 control = upa_readq(iommu->iommu_control); 212 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) { 213 const char *type_str; 214 215 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR; 216 upa_writeq(control, iommu->iommu_control); 217 218 switch ((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) { 219 case 0: 220 type_str = "Protection Error"; 221 break; 222 case 1: 223 type_str = "Invalid Error"; 224 break; 225 case 2: 226 type_str = "TimeOut Error"; 227 break; 228 case 3: 229 default: 230 type_str = "ECC Error"; 231 break; 232 } 233 printk(KERN_ERR "%s: IOMMU Error, type[%s]\n", 234 pbm->name, type_str); 235 236 /* It is very possible for another DVMA to occur while 237 * we do this probe, and corrupt the system further. 238 * But we are so screwed at this point that we are 239 * likely to crash hard anyways, so get as much 240 * diagnostic information to the console as we can. 241 */ 242 psycho_record_iommu_tags_and_data(pbm, iommu_tag, iommu_data); 243 psycho_dump_iommu_tags_and_data(pbm, iommu_tag, iommu_data); 244 } 245 psycho_check_stc_error(pbm); 246 spin_unlock_irqrestore(&iommu->lock, flags); 247 } 248 249 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL 250 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL 251 252 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm) 253 { 254 irqreturn_t ret = IRQ_NONE; 255 u64 csr, csr_error_bits; 256 u16 stat, *addr; 257 258 csr = upa_readq(pbm->pci_csr); 259 csr_error_bits = csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR); 260 if (csr_error_bits) { 261 /* Clear the errors. */ 262 upa_writeq(csr, pbm->pci_csr); 263 264 /* Log 'em. */ 265 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR) 266 printk(KERN_ERR "%s: PCI streaming byte hole " 267 "error asserted.\n", pbm->name); 268 if (csr_error_bits & PSYCHO_PCICTRL_SERR) 269 printk(KERN_ERR "%s: PCI SERR signal asserted.\n", 270 pbm->name); 271 ret = IRQ_HANDLED; 272 } 273 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, 274 0, PCI_STATUS); 275 pci_config_read16(addr, &stat); 276 if (stat & (PCI_STATUS_PARITY | 277 PCI_STATUS_SIG_TARGET_ABORT | 278 PCI_STATUS_REC_TARGET_ABORT | 279 PCI_STATUS_REC_MASTER_ABORT | 280 PCI_STATUS_SIG_SYSTEM_ERROR)) { 281 printk(KERN_ERR "%s: PCI bus error, PCI_STATUS[%04x]\n", 282 pbm->name, stat); 283 pci_config_write16(addr, 0xffff); 284 ret = IRQ_HANDLED; 285 } 286 return ret; 287 } 288 289 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000ULL 290 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000ULL 291 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000ULL 292 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000ULL 293 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000ULL 294 #define PSYCHO_PCIAFSR_STA 0x0400000000000000ULL 295 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000ULL 296 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000ULL 297 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000ULL 298 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000ULL 299 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000ULL 300 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000ULL 301 #define PSYCHO_PCIAFSR_MID 0x000000003e000000ULL 302 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffULL 303 304 irqreturn_t psycho_pcierr_intr(int irq, void *dev_id) 305 { 306 struct pci_pbm_info *pbm = dev_id; 307 u64 afsr, afar, error_bits; 308 int reported; 309 310 afsr = upa_readq(pbm->pci_afsr); 311 afar = upa_readq(pbm->pci_afar); 312 error_bits = afsr & 313 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA | 314 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR | 315 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA | 316 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR); 317 if (!error_bits) 318 return psycho_pcierr_intr_other(pbm); 319 upa_writeq(error_bits, pbm->pci_afsr); 320 printk(KERN_ERR "%s: PCI Error, primary error type[%s]\n", 321 pbm->name, 322 (((error_bits & PSYCHO_PCIAFSR_PMA) ? 323 "Master Abort" : 324 ((error_bits & PSYCHO_PCIAFSR_PTA) ? 325 "Target Abort" : 326 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ? 327 "Excessive Retries" : 328 ((error_bits & PSYCHO_PCIAFSR_PPERR) ? 329 "Parity Error" : "???")))))); 330 printk(KERN_ERR "%s: bytemask[%04llx] UPA_MID[%02llx] was_block(%d)\n", 331 pbm->name, 332 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL, 333 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL, 334 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0); 335 printk(KERN_ERR "%s: PCI AFAR [%016llx]\n", pbm->name, afar); 336 printk(KERN_ERR "%s: PCI Secondary errors [", pbm->name); 337 reported = 0; 338 if (afsr & PSYCHO_PCIAFSR_SMA) { 339 reported++; 340 printk("(Master Abort)"); 341 } 342 if (afsr & PSYCHO_PCIAFSR_STA) { 343 reported++; 344 printk("(Target Abort)"); 345 } 346 if (afsr & PSYCHO_PCIAFSR_SRTRY) { 347 reported++; 348 printk("(Excessive Retries)"); 349 } 350 if (afsr & PSYCHO_PCIAFSR_SPERR) { 351 reported++; 352 printk("(Parity Error)"); 353 } 354 if (!reported) 355 printk("(none)"); 356 printk("]\n"); 357 358 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) { 359 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR); 360 pci_scan_for_target_abort(pbm, pbm->pci_bus); 361 } 362 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA)) 363 pci_scan_for_master_abort(pbm, pbm->pci_bus); 364 365 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR)) 366 pci_scan_for_parity_error(pbm, pbm->pci_bus); 367 368 return IRQ_HANDLED; 369 } 370 371 static void psycho_iommu_flush(struct pci_pbm_info *pbm) 372 { 373 int i; 374 375 for (i = 0; i < 16; i++) { 376 unsigned long off = i * 8; 377 378 upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_TAG + off); 379 upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_DATA + off); 380 } 381 } 382 383 #define PSYCHO_IOMMU_CONTROL 0x0200UL 384 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL 385 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL 386 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL 387 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL 388 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL 389 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL 390 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL 391 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL 392 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL 393 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL 394 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL 395 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL 396 #define PSYCHO_IOMMU_FLUSH 0x0210UL 397 #define PSYCHO_IOMMU_TSBBASE 0x0208UL 398 399 int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize, 400 u32 dvma_offset, u32 dma_mask, 401 unsigned long write_complete_offset) 402 { 403 struct iommu *iommu = pbm->iommu; 404 u64 control; 405 int err; 406 407 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL; 408 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE; 409 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH; 410 iommu->iommu_tags = pbm->controller_regs + PSYCHO_IOMMU_TAG; 411 iommu->write_complete_reg = (pbm->controller_regs + 412 write_complete_offset); 413 414 iommu->iommu_ctxflush = 0; 415 416 control = upa_readq(iommu->iommu_control); 417 control |= PSYCHO_IOMMU_CTRL_DENAB; 418 upa_writeq(control, iommu->iommu_control); 419 420 psycho_iommu_flush(pbm); 421 422 /* Leave diag mode enabled for full-flushing done in pci_iommu.c */ 423 err = iommu_table_init(iommu, tsbsize * 1024 * 8, 424 dvma_offset, dma_mask, pbm->numa_node); 425 if (err) 426 return err; 427 428 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); 429 430 control = upa_readq(iommu->iommu_control); 431 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ); 432 control |= PSYCHO_IOMMU_CTRL_ENAB; 433 434 switch (tsbsize) { 435 case 64: 436 control |= PSYCHO_IOMMU_TSBSZ_64K; 437 break; 438 case 128: 439 control |= PSYCHO_IOMMU_TSBSZ_128K; 440 break; 441 default: 442 return -EINVAL; 443 } 444 445 upa_writeq(control, iommu->iommu_control); 446 447 return 0; 448 449 } 450 451 void psycho_pbm_init_common(struct pci_pbm_info *pbm, struct platform_device *op, 452 const char *chip_name, int chip_type) 453 { 454 struct device_node *dp = op->dev.of_node; 455 456 pbm->name = dp->full_name; 457 pbm->numa_node = -1; 458 pbm->chip_type = chip_type; 459 pbm->chip_version = of_getintprop_default(dp, "version#", 0); 460 pbm->chip_revision = of_getintprop_default(dp, "module-revision#", 0); 461 pbm->op = op; 462 pbm->pci_ops = &sun4u_pci_ops; 463 pbm->config_space_reg_bits = 8; 464 pbm->index = pci_num_pbms++; 465 pci_get_pbm_props(pbm); 466 pci_determine_mem_io_space(pbm); 467 468 printk(KERN_INFO "%s: %s PCI Bus Module ver[%x:%x]\n", 469 pbm->name, chip_name, 470 pbm->chip_version, pbm->chip_revision); 471 } 472