1 // SPDX-License-Identifier: GPL-2.0 2 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support. 3 * 4 * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net) 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/init.h> 11 #include <linux/slab.h> 12 #include <linux/export.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/numa.h> 19 20 #include <asm/iommu.h> 21 #include <asm/irq.h> 22 #include <asm/pstate.h> 23 #include <asm/prom.h> 24 #include <asm/upa.h> 25 26 #include "pci_impl.h" 27 #include "iommu_common.h" 28 29 #define DRIVER_NAME "schizo" 30 #define PFX DRIVER_NAME ": " 31 32 /* This is a convention that at least Excalibur and Merlin 33 * follow. I suppose the SCHIZO used in Starcat and friends 34 * will do similar. 35 * 36 * The only way I could see this changing is if the newlink 37 * block requires more space in Schizo's address space than 38 * they predicted, thus requiring an address space reorg when 39 * the newer Schizo is taped out. 40 */ 41 42 /* Streaming buffer control register. */ 43 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ 44 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ 45 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ 46 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ 47 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ 48 49 /* IOMMU control register. */ 50 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ 51 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ 52 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ 53 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ 54 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ 55 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ 56 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ 57 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ 58 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ 59 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ 60 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ 61 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ 62 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ 63 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ 64 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ 65 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ 66 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ 67 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ 68 69 /* Schizo config space address format is nearly identical to 70 * that of PSYCHO: 71 * 72 * 32 24 23 16 15 11 10 8 7 2 1 0 73 * --------------------------------------------------------- 74 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 | 75 * --------------------------------------------------------- 76 */ 77 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space) 78 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ 79 (((unsigned long)(BUS) << 16) | \ 80 ((unsigned long)(DEVFN) << 8) | \ 81 ((unsigned long)(REG))) 82 83 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm, 84 unsigned char bus, 85 unsigned int devfn, 86 int where) 87 { 88 if (!pbm) 89 return NULL; 90 bus -= pbm->pci_first_busno; 91 return (void *) 92 (SCHIZO_CONFIG_BASE(pbm) | 93 SCHIZO_CONFIG_ENCODE(bus, devfn, where)); 94 } 95 96 /* SCHIZO error handling support. */ 97 enum schizo_error_type { 98 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR 99 }; 100 101 static DEFINE_SPINLOCK(stc_buf_lock); 102 static unsigned long stc_error_buf[128]; 103 static unsigned long stc_tag_buf[16]; 104 static unsigned long stc_line_buf[16]; 105 106 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */ 107 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */ 108 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */ 109 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */ 110 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */ 111 112 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ 113 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ 114 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ 115 116 #define SCHIZO_STCERR_WRITE 0x2UL 117 #define SCHIZO_STCERR_READ 0x1UL 118 119 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL 120 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL 121 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL 122 #define SCHIZO_STCTAG_READ 0x4000000000000000UL 123 124 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL 125 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL 126 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL 127 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL 128 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL 129 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL 130 131 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm, 132 enum schizo_error_type type) 133 { 134 struct strbuf *strbuf = &pbm->stc; 135 unsigned long regbase = pbm->pbm_regs; 136 unsigned long err_base, tag_base, line_base; 137 u64 control; 138 int i; 139 140 err_base = regbase + SCHIZO_STC_ERR; 141 tag_base = regbase + SCHIZO_STC_TAG; 142 line_base = regbase + SCHIZO_STC_LINE; 143 144 spin_lock(&stc_buf_lock); 145 146 /* This is __REALLY__ dangerous. When we put the 147 * streaming buffer into diagnostic mode to probe 148 * its tags and error status, we _must_ clear all 149 * of the line tag valid bits before re-enabling 150 * the streaming buffer. If any dirty data lives 151 * in the STC when we do this, we will end up 152 * invalidating it before it has a chance to reach 153 * main memory. 154 */ 155 control = upa_readq(strbuf->strbuf_control); 156 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB), 157 strbuf->strbuf_control); 158 for (i = 0; i < 128; i++) { 159 unsigned long val; 160 161 val = upa_readq(err_base + (i * 8UL)); 162 upa_writeq(0UL, err_base + (i * 8UL)); 163 stc_error_buf[i] = val; 164 } 165 for (i = 0; i < 16; i++) { 166 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL)); 167 stc_line_buf[i] = upa_readq(line_base + (i * 8UL)); 168 upa_writeq(0UL, tag_base + (i * 8UL)); 169 upa_writeq(0UL, line_base + (i * 8UL)); 170 } 171 172 /* OK, state is logged, exit diagnostic mode. */ 173 upa_writeq(control, strbuf->strbuf_control); 174 175 for (i = 0; i < 16; i++) { 176 int j, saw_error, first, last; 177 178 saw_error = 0; 179 first = i * 8; 180 last = first + 8; 181 for (j = first; j < last; j++) { 182 unsigned long errval = stc_error_buf[j]; 183 if (errval != 0) { 184 saw_error++; 185 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n", 186 pbm->name, 187 j, 188 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0, 189 (errval & SCHIZO_STCERR_READ) ? 1 : 0); 190 } 191 } 192 if (saw_error != 0) { 193 unsigned long tagval = stc_tag_buf[i]; 194 unsigned long lineval = stc_line_buf[i]; 195 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n", 196 pbm->name, 197 i, 198 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL), 199 (tagval & SCHIZO_STCTAG_VPN), 200 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0), 201 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0)); 202 203 /* XXX Should spit out per-bank error information... -DaveM */ 204 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" 205 "V(%d)FOFN(%d)]\n", 206 pbm->name, 207 i, 208 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL), 209 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL), 210 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL), 211 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL), 212 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0), 213 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0)); 214 } 215 } 216 217 spin_unlock(&stc_buf_lock); 218 } 219 220 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous 221 * controller level errors. 222 */ 223 224 #define SCHIZO_IOMMU_TAG 0xa580UL 225 #define SCHIZO_IOMMU_DATA 0xa600UL 226 227 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL 228 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL 229 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL 230 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL 231 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL 232 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL 233 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL 234 235 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL 236 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL 237 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL 238 239 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm, 240 enum schizo_error_type type) 241 { 242 struct iommu *iommu = pbm->iommu; 243 unsigned long iommu_tag[16]; 244 unsigned long iommu_data[16]; 245 unsigned long flags; 246 u64 control; 247 int i; 248 249 spin_lock_irqsave(&iommu->lock, flags); 250 control = upa_readq(iommu->iommu_control); 251 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { 252 unsigned long base; 253 char *type_string; 254 255 /* Clear the error encountered bit. */ 256 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; 257 upa_writeq(control, iommu->iommu_control); 258 259 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { 260 case 0: 261 type_string = "Protection Error"; 262 break; 263 case 1: 264 type_string = "Invalid Error"; 265 break; 266 case 2: 267 type_string = "TimeOut Error"; 268 break; 269 case 3: 270 default: 271 type_string = "ECC Error"; 272 break; 273 } 274 printk("%s: IOMMU Error, type[%s]\n", 275 pbm->name, type_string); 276 277 /* Put the IOMMU into diagnostic mode and probe 278 * its TLB for entries with error status. 279 * 280 * It is very possible for another DVMA to occur 281 * while we do this probe, and corrupt the system 282 * further. But we are so screwed at this point 283 * that we are likely to crash hard anyways, so 284 * get as much diagnostic information to the 285 * console as we can. 286 */ 287 upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB, 288 iommu->iommu_control); 289 290 base = pbm->pbm_regs; 291 292 for (i = 0; i < 16; i++) { 293 iommu_tag[i] = 294 upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL)); 295 iommu_data[i] = 296 upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL)); 297 298 /* Now clear out the entry. */ 299 upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL)); 300 upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL)); 301 } 302 303 /* Leave diagnostic mode. */ 304 upa_writeq(control, iommu->iommu_control); 305 306 for (i = 0; i < 16; i++) { 307 unsigned long tag, data; 308 309 tag = iommu_tag[i]; 310 if (!(tag & SCHIZO_IOMMU_TAG_ERR)) 311 continue; 312 313 data = iommu_data[i]; 314 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) { 315 case 0: 316 type_string = "Protection Error"; 317 break; 318 case 1: 319 type_string = "Invalid Error"; 320 break; 321 case 2: 322 type_string = "TimeOut Error"; 323 break; 324 case 3: 325 default: 326 type_string = "ECC Error"; 327 break; 328 } 329 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) " 330 "sz(%dK) vpg(%08lx)]\n", 331 pbm->name, i, type_string, 332 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL), 333 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0), 334 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0), 335 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8), 336 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); 337 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", 338 pbm->name, i, 339 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0), 340 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0), 341 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); 342 } 343 } 344 if (pbm->stc.strbuf_enabled) 345 __schizo_check_stc_error_pbm(pbm, type); 346 spin_unlock_irqrestore(&iommu->lock, flags); 347 } 348 349 static void schizo_check_iommu_error(struct pci_pbm_info *pbm, 350 enum schizo_error_type type) 351 { 352 schizo_check_iommu_error_pbm(pbm, type); 353 if (pbm->sibling) 354 schizo_check_iommu_error_pbm(pbm->sibling, type); 355 } 356 357 /* Uncorrectable ECC error status gathering. */ 358 #define SCHIZO_UE_AFSR 0x10030UL 359 #define SCHIZO_UE_AFAR 0x10038UL 360 361 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */ 362 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */ 363 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */ 364 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */ 365 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */ 366 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */ 367 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */ 368 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */ 369 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */ 370 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */ 371 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */ 372 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */ 373 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */ 374 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */ 375 376 static irqreturn_t schizo_ue_intr(int irq, void *dev_id) 377 { 378 struct pci_pbm_info *pbm = dev_id; 379 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR; 380 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR; 381 unsigned long afsr, afar, error_bits; 382 int reported, limit; 383 384 /* Latch uncorrectable error status. */ 385 afar = upa_readq(afar_reg); 386 387 /* If either of the error pending bits are set in the 388 * AFSR, the error status is being actively updated by 389 * the hardware and we must re-read to get a clean value. 390 */ 391 limit = 1000; 392 do { 393 afsr = upa_readq(afsr_reg); 394 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 395 396 /* Clear the primary/secondary error status bits. */ 397 error_bits = afsr & 398 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR | 399 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); 400 if (!error_bits) 401 return IRQ_NONE; 402 upa_writeq(error_bits, afsr_reg); 403 404 /* Log the error. */ 405 printk("%s: Uncorrectable Error, primary error type[%s]\n", 406 pbm->name, 407 (((error_bits & SCHIZO_UEAFSR_PPIO) ? 408 "PIO" : 409 ((error_bits & SCHIZO_UEAFSR_PDRD) ? 410 "DMA Read" : 411 ((error_bits & SCHIZO_UEAFSR_PDWR) ? 412 "DMA Write" : "???"))))); 413 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 414 pbm->name, 415 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 416 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 417 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 418 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 419 pbm->name, 420 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 421 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 422 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 423 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 424 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 425 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); 426 printk("%s: UE Secondary errors [", pbm->name); 427 reported = 0; 428 if (afsr & SCHIZO_UEAFSR_SPIO) { 429 reported++; 430 printk("(PIO)"); 431 } 432 if (afsr & SCHIZO_UEAFSR_SDMA) { 433 reported++; 434 printk("(DMA)"); 435 } 436 if (!reported) 437 printk("(none)"); 438 printk("]\n"); 439 440 /* Interrogate IOMMU for error status. */ 441 schizo_check_iommu_error(pbm, UE_ERR); 442 443 return IRQ_HANDLED; 444 } 445 446 #define SCHIZO_CE_AFSR 0x10040UL 447 #define SCHIZO_CE_AFAR 0x10048UL 448 449 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL 450 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL 451 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL 452 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL 453 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL 454 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL 455 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL 456 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL 457 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL 458 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL 459 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL 460 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL 461 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL 462 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL 463 464 static irqreturn_t schizo_ce_intr(int irq, void *dev_id) 465 { 466 struct pci_pbm_info *pbm = dev_id; 467 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR; 468 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR; 469 unsigned long afsr, afar, error_bits; 470 int reported, limit; 471 472 /* Latch error status. */ 473 afar = upa_readq(afar_reg); 474 475 /* If either of the error pending bits are set in the 476 * AFSR, the error status is being actively updated by 477 * the hardware and we must re-read to get a clean value. 478 */ 479 limit = 1000; 480 do { 481 afsr = upa_readq(afsr_reg); 482 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 483 484 /* Clear primary/secondary error status bits. */ 485 error_bits = afsr & 486 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR | 487 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); 488 if (!error_bits) 489 return IRQ_NONE; 490 upa_writeq(error_bits, afsr_reg); 491 492 /* Log the error. */ 493 printk("%s: Correctable Error, primary error type[%s]\n", 494 pbm->name, 495 (((error_bits & SCHIZO_CEAFSR_PPIO) ? 496 "PIO" : 497 ((error_bits & SCHIZO_CEAFSR_PDRD) ? 498 "DMA Read" : 499 ((error_bits & SCHIZO_CEAFSR_PDWR) ? 500 "DMA Write" : "???"))))); 501 502 /* XXX Use syndrome and afar to print out module string just like 503 * XXX UDB CE trap handler does... -DaveM 504 */ 505 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 506 pbm->name, 507 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 508 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 509 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 510 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 511 pbm->name, 512 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 513 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 514 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 515 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 516 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 517 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); 518 printk("%s: CE Secondary errors [", pbm->name); 519 reported = 0; 520 if (afsr & SCHIZO_CEAFSR_SPIO) { 521 reported++; 522 printk("(PIO)"); 523 } 524 if (afsr & SCHIZO_CEAFSR_SDMA) { 525 reported++; 526 printk("(DMA)"); 527 } 528 if (!reported) 529 printk("(none)"); 530 printk("]\n"); 531 532 return IRQ_HANDLED; 533 } 534 535 #define SCHIZO_PCI_AFSR 0x2010UL 536 #define SCHIZO_PCI_AFAR 0x2018UL 537 538 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */ 539 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */ 540 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */ 541 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */ 542 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */ 543 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */ 544 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */ 545 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */ 546 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */ 547 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */ 548 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */ 549 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */ 550 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */ 551 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */ 552 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */ 553 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */ 554 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */ 555 556 #define SCHIZO_PCI_CTRL (0x2000UL) 557 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */ 558 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */ 559 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */ 560 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */ 561 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */ 562 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */ 563 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */ 564 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */ 565 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */ 566 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */ 567 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */ 568 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */ 569 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */ 570 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */ 571 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */ 572 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL 573 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */ 574 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */ 575 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */ 576 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */ 577 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */ 578 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */ 579 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */ 580 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */ 581 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */ 582 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */ 583 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */ 584 585 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm) 586 { 587 unsigned long csr_reg, csr, csr_error_bits; 588 irqreturn_t ret = IRQ_NONE; 589 u32 stat; 590 591 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; 592 csr = upa_readq(csr_reg); 593 csr_error_bits = 594 csr & (SCHIZO_PCICTRL_BUS_UNUS | 595 SCHIZO_PCICTRL_TTO_ERR | 596 SCHIZO_PCICTRL_RTRY_ERR | 597 SCHIZO_PCICTRL_DTO_ERR | 598 SCHIZO_PCICTRL_SBH_ERR | 599 SCHIZO_PCICTRL_SERR); 600 if (csr_error_bits) { 601 /* Clear the errors. */ 602 upa_writeq(csr, csr_reg); 603 604 /* Log 'em. */ 605 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) 606 printk("%s: Bus unusable error asserted.\n", 607 pbm->name); 608 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR) 609 printk("%s: PCI TRDY# timeout error asserted.\n", 610 pbm->name); 611 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR) 612 printk("%s: PCI excessive retry error asserted.\n", 613 pbm->name); 614 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR) 615 printk("%s: PCI discard timeout error asserted.\n", 616 pbm->name); 617 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR) 618 printk("%s: PCI streaming byte hole error asserted.\n", 619 pbm->name); 620 if (csr_error_bits & SCHIZO_PCICTRL_SERR) 621 printk("%s: PCI SERR signal asserted.\n", 622 pbm->name); 623 ret = IRQ_HANDLED; 624 } 625 pbm->pci_ops->read(pbm->pci_bus, 0, PCI_STATUS, 2, &stat); 626 if (stat & (PCI_STATUS_PARITY | 627 PCI_STATUS_SIG_TARGET_ABORT | 628 PCI_STATUS_REC_TARGET_ABORT | 629 PCI_STATUS_REC_MASTER_ABORT | 630 PCI_STATUS_SIG_SYSTEM_ERROR)) { 631 printk("%s: PCI bus error, PCI_STATUS[%04x]\n", 632 pbm->name, stat); 633 pbm->pci_ops->write(pbm->pci_bus, 0, PCI_STATUS, 2, 0xffff); 634 ret = IRQ_HANDLED; 635 } 636 return ret; 637 } 638 639 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id) 640 { 641 struct pci_pbm_info *pbm = dev_id; 642 unsigned long afsr_reg, afar_reg, base; 643 unsigned long afsr, afar, error_bits; 644 int reported; 645 646 base = pbm->pbm_regs; 647 648 afsr_reg = base + SCHIZO_PCI_AFSR; 649 afar_reg = base + SCHIZO_PCI_AFAR; 650 651 /* Latch error status. */ 652 afar = upa_readq(afar_reg); 653 afsr = upa_readq(afsr_reg); 654 655 /* Clear primary/secondary error status bits. */ 656 error_bits = afsr & 657 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 658 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 659 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 660 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 661 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 662 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); 663 if (!error_bits) 664 return schizo_pcierr_intr_other(pbm); 665 upa_writeq(error_bits, afsr_reg); 666 667 /* Log the error. */ 668 printk("%s: PCI Error, primary error type[%s]\n", 669 pbm->name, 670 (((error_bits & SCHIZO_PCIAFSR_PMA) ? 671 "Master Abort" : 672 ((error_bits & SCHIZO_PCIAFSR_PTA) ? 673 "Target Abort" : 674 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ? 675 "Excessive Retries" : 676 ((error_bits & SCHIZO_PCIAFSR_PPERR) ? 677 "Parity Error" : 678 ((error_bits & SCHIZO_PCIAFSR_PTTO) ? 679 "Timeout" : 680 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ? 681 "Bus Unusable" : "???")))))))); 682 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n", 683 pbm->name, 684 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL, 685 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0, 686 ((afsr & SCHIZO_PCIAFSR_CFG) ? 687 "Config" : 688 ((afsr & SCHIZO_PCIAFSR_MEM) ? 689 "Memory" : 690 ((afsr & SCHIZO_PCIAFSR_IO) ? 691 "I/O" : "???")))); 692 printk("%s: PCI AFAR [%016lx]\n", 693 pbm->name, afar); 694 printk("%s: PCI Secondary errors [", 695 pbm->name); 696 reported = 0; 697 if (afsr & SCHIZO_PCIAFSR_SMA) { 698 reported++; 699 printk("(Master Abort)"); 700 } 701 if (afsr & SCHIZO_PCIAFSR_STA) { 702 reported++; 703 printk("(Target Abort)"); 704 } 705 if (afsr & SCHIZO_PCIAFSR_SRTRY) { 706 reported++; 707 printk("(Excessive Retries)"); 708 } 709 if (afsr & SCHIZO_PCIAFSR_SPERR) { 710 reported++; 711 printk("(Parity Error)"); 712 } 713 if (afsr & SCHIZO_PCIAFSR_STTO) { 714 reported++; 715 printk("(Timeout)"); 716 } 717 if (afsr & SCHIZO_PCIAFSR_SUNUS) { 718 reported++; 719 printk("(Bus Unusable)"); 720 } 721 if (!reported) 722 printk("(none)"); 723 printk("]\n"); 724 725 /* For the error types shown, scan PBM's PCI bus for devices 726 * which have logged that error type. 727 */ 728 729 /* If we see a Target Abort, this could be the result of an 730 * IOMMU translation error of some sort. It is extremely 731 * useful to log this information as usually it indicates 732 * a bug in the IOMMU support code or a PCI device driver. 733 */ 734 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) { 735 schizo_check_iommu_error(pbm, PCI_ERR); 736 pci_scan_for_target_abort(pbm, pbm->pci_bus); 737 } 738 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA)) 739 pci_scan_for_master_abort(pbm, pbm->pci_bus); 740 741 /* For excessive retries, PSYCHO/PBM will abort the device 742 * and there is no way to specifically check for excessive 743 * retries in the config space status registers. So what 744 * we hope is that we'll catch it via the master/target 745 * abort events. 746 */ 747 748 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR)) 749 pci_scan_for_parity_error(pbm, pbm->pci_bus); 750 751 return IRQ_HANDLED; 752 } 753 754 #define SCHIZO_SAFARI_ERRLOG 0x10018UL 755 756 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL 757 758 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */ 759 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */ 760 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */ 761 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */ 762 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */ 763 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */ 764 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */ 765 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */ 766 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */ 767 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */ 768 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */ 769 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */ 770 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */ 771 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */ 772 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */ 773 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */ 774 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */ 775 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */ 776 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */ 777 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */ 778 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */ 779 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */ 780 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */ 781 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */ 782 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */ 783 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */ 784 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */ 785 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */ 786 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */ 787 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */ 788 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */ 789 790 /* We only expect UNMAP errors here. The rest of the Safari errors 791 * are marked fatal and thus cause a system reset. 792 */ 793 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id) 794 { 795 struct pci_pbm_info *pbm = dev_id; 796 u64 errlog; 797 798 errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 799 upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT), 800 pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 801 802 if (!(errlog & BUS_ERROR_UNMAP)) { 803 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n", 804 pbm->name, errlog); 805 806 return IRQ_HANDLED; 807 } 808 809 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n", 810 pbm->name); 811 schizo_check_iommu_error(pbm, SAFARI_ERR); 812 813 return IRQ_HANDLED; 814 } 815 816 /* Nearly identical to PSYCHO equivalents... */ 817 #define SCHIZO_ECC_CTRL 0x10020UL 818 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 819 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ 820 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ 821 822 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL 823 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL 824 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL 825 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL 826 827 static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino) 828 { 829 ino &= IMAP_INO; 830 831 if (pbm->ino_bitmap & (1UL << ino)) 832 return 1; 833 834 return 0; 835 } 836 837 /* How the Tomatillo IRQs are routed around is pure guesswork here. 838 * 839 * All the Tomatillo devices I see in prtconf dumps seem to have only 840 * a single PCI bus unit attached to it. It would seem they are separate 841 * devices because their PortID (ie. JBUS ID) values are all different 842 * and thus the registers are mapped to totally different locations. 843 * 844 * However, two Tomatillo's look "similar" in that the only difference 845 * in their PortID is the lowest bit. 846 * 847 * So if we were to ignore this lower bit, it certainly looks like two 848 * PCI bus units of the same Tomatillo. I still have not really 849 * figured this out... 850 */ 851 static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm) 852 { 853 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 854 u64 tmp, err_mask, err_no_mask; 855 int err; 856 857 /* Tomatillo IRQ property layout is: 858 * 0: PCIERR 859 * 1: UE ERR 860 * 2: CE ERR 861 * 3: SERR 862 * 4: POWER FAIL? 863 */ 864 865 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 866 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 867 "TOMATILLO_UE", pbm); 868 if (err) 869 printk(KERN_WARNING "%s: Could not register UE, " 870 "err=%d\n", pbm->name, err); 871 } 872 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 873 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 874 "TOMATILLO_CE", pbm); 875 if (err) 876 printk(KERN_WARNING "%s: Could not register CE, " 877 "err=%d\n", pbm->name, err); 878 } 879 err = 0; 880 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 881 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 882 "TOMATILLO_PCIERR", pbm); 883 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 884 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 885 "TOMATILLO_PCIERR", pbm); 886 } 887 if (err) 888 printk(KERN_WARNING "%s: Could not register PCIERR, " 889 "err=%d\n", pbm->name, err); 890 891 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 892 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 893 "TOMATILLO_SERR", pbm); 894 if (err) 895 printk(KERN_WARNING "%s: Could not register SERR, " 896 "err=%d\n", pbm->name, err); 897 } 898 899 /* Enable UE and CE interrupts for controller. */ 900 upa_writeq((SCHIZO_ECCCTRL_EE | 901 SCHIZO_ECCCTRL_UE | 902 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 903 904 /* Enable PCI Error interrupts and clear error 905 * bits. 906 */ 907 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 908 SCHIZO_PCICTRL_TTO_ERR | 909 SCHIZO_PCICTRL_RTRY_ERR | 910 SCHIZO_PCICTRL_SERR | 911 SCHIZO_PCICTRL_EEN); 912 913 err_no_mask = SCHIZO_PCICTRL_DTO_ERR; 914 915 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 916 tmp |= err_mask; 917 tmp &= ~err_no_mask; 918 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 919 920 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 921 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 922 SCHIZO_PCIAFSR_PTTO | 923 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 924 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 925 SCHIZO_PCIAFSR_STTO); 926 927 upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR); 928 929 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | 930 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | 931 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA | 932 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO | 933 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR | 934 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B | 935 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR | 936 BUS_ERROR_APERR | BUS_ERROR_UNMAP | 937 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); 938 939 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 940 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 941 942 upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)), 943 pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL); 944 } 945 946 static void schizo_register_error_handlers(struct pci_pbm_info *pbm) 947 { 948 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 949 u64 tmp, err_mask, err_no_mask; 950 int err; 951 952 /* Schizo IRQ property layout is: 953 * 0: PCIERR 954 * 1: UE ERR 955 * 2: CE ERR 956 * 3: SERR 957 * 4: POWER FAIL? 958 */ 959 960 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 961 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 962 "SCHIZO_UE", pbm); 963 if (err) 964 printk(KERN_WARNING "%s: Could not register UE, " 965 "err=%d\n", pbm->name, err); 966 } 967 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 968 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 969 "SCHIZO_CE", pbm); 970 if (err) 971 printk(KERN_WARNING "%s: Could not register CE, " 972 "err=%d\n", pbm->name, err); 973 } 974 err = 0; 975 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 976 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 977 "SCHIZO_PCIERR", pbm); 978 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 979 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 980 "SCHIZO_PCIERR", pbm); 981 } 982 if (err) 983 printk(KERN_WARNING "%s: Could not register PCIERR, " 984 "err=%d\n", pbm->name, err); 985 986 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 987 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 988 "SCHIZO_SERR", pbm); 989 if (err) 990 printk(KERN_WARNING "%s: Could not register SERR, " 991 "err=%d\n", pbm->name, err); 992 } 993 994 /* Enable UE and CE interrupts for controller. */ 995 upa_writeq((SCHIZO_ECCCTRL_EE | 996 SCHIZO_ECCCTRL_UE | 997 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 998 999 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 1000 SCHIZO_PCICTRL_ESLCK | 1001 SCHIZO_PCICTRL_TTO_ERR | 1002 SCHIZO_PCICTRL_RTRY_ERR | 1003 SCHIZO_PCICTRL_SBH_ERR | 1004 SCHIZO_PCICTRL_SERR | 1005 SCHIZO_PCICTRL_EEN); 1006 1007 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR | 1008 SCHIZO_PCICTRL_SBH_INT); 1009 1010 /* Enable PCI Error interrupts and clear error 1011 * bits for each PBM. 1012 */ 1013 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1014 tmp |= err_mask; 1015 tmp &= ~err_no_mask; 1016 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1017 1018 upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 1019 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 1020 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 1021 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 1022 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 1023 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS), 1024 pbm->pbm_regs + SCHIZO_PCI_AFSR); 1025 1026 /* Make all Safari error conditions fatal except unmapped 1027 * errors which we make generate interrupts. 1028 */ 1029 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS | 1030 BUS_ERROR_BADMA | BUS_ERROR_BADMB | 1031 BUS_ERROR_BADMC | 1032 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1033 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB | 1034 BUS_ERROR_CIQTO | 1035 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO | 1036 BUS_ERROR_UFPQTO | BUS_ERROR_APERR | 1037 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT | 1038 BUS_ERROR_ILL); 1039 #if 1 1040 /* XXX Something wrong with some Excalibur systems 1041 * XXX Sun is shipping. The behavior on a 2-cpu 1042 * XXX machine is that both CPU1 parity error bits 1043 * XXX are set and are immediately set again when 1044 * XXX their error status bits are cleared. Just 1045 * XXX ignore them for now. -DaveM 1046 */ 1047 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1048 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); 1049 #endif 1050 1051 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 1052 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 1053 } 1054 1055 static void pbm_config_busmastering(struct pci_pbm_info *pbm) 1056 { 1057 u8 *addr; 1058 1059 /* Set cache-line size to 64 bytes, this is actually 1060 * a nop but I do it for completeness. 1061 */ 1062 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1063 0, PCI_CACHE_LINE_SIZE); 1064 pci_config_write8(addr, 64 / sizeof(u32)); 1065 1066 /* Set PBM latency timer to 64 PCI clocks. */ 1067 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1068 0, PCI_LATENCY_TIMER); 1069 pci_config_write8(addr, 64); 1070 } 1071 1072 static void schizo_scan_bus(struct pci_pbm_info *pbm, struct device *parent) 1073 { 1074 pbm_config_busmastering(pbm); 1075 pbm->is_66mhz_capable = 1076 (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL) 1077 != NULL); 1078 1079 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); 1080 1081 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1082 tomatillo_register_error_handlers(pbm); 1083 else 1084 schizo_register_error_handlers(pbm); 1085 } 1086 1087 #define SCHIZO_STRBUF_CONTROL (0x02800UL) 1088 #define SCHIZO_STRBUF_FLUSH (0x02808UL) 1089 #define SCHIZO_STRBUF_FSYNC (0x02810UL) 1090 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL) 1091 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL) 1092 1093 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm) 1094 { 1095 unsigned long base = pbm->pbm_regs; 1096 u64 control; 1097 1098 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1099 /* TOMATILLO lacks streaming cache. */ 1100 return; 1101 } 1102 1103 /* SCHIZO has context flushing. */ 1104 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; 1105 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; 1106 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; 1107 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; 1108 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; 1109 1110 pbm->stc.strbuf_flushflag = (volatile unsigned long *) 1111 ((((unsigned long)&pbm->stc.__flushflag_buf[0]) 1112 + 63UL) 1113 & ~63UL); 1114 pbm->stc.strbuf_flushflag_pa = (unsigned long) 1115 __pa(pbm->stc.strbuf_flushflag); 1116 1117 /* Turn off LRU locking and diag mode, enable the 1118 * streaming buffer and leave the rerun-disable 1119 * setting however OBP set it. 1120 */ 1121 control = upa_readq(pbm->stc.strbuf_control); 1122 control &= ~(SCHIZO_STRBUF_CTRL_LPTR | 1123 SCHIZO_STRBUF_CTRL_LENAB | 1124 SCHIZO_STRBUF_CTRL_DENAB); 1125 control |= SCHIZO_STRBUF_CTRL_ENAB; 1126 upa_writeq(control, pbm->stc.strbuf_control); 1127 1128 pbm->stc.strbuf_enabled = 1; 1129 } 1130 1131 #define SCHIZO_IOMMU_CONTROL (0x00200UL) 1132 #define SCHIZO_IOMMU_TSBBASE (0x00208UL) 1133 #define SCHIZO_IOMMU_FLUSH (0x00210UL) 1134 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL) 1135 1136 static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm) 1137 { 1138 static const u32 vdma_default[] = { 0xc0000000, 0x40000000 }; 1139 unsigned long i, tagbase, database; 1140 struct iommu *iommu = pbm->iommu; 1141 int tsbsize, err; 1142 const u32 *vdma; 1143 u32 dma_mask; 1144 u64 control; 1145 1146 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); 1147 if (!vdma) 1148 vdma = vdma_default; 1149 1150 dma_mask = vdma[0]; 1151 switch (vdma[1]) { 1152 case 0x20000000: 1153 dma_mask |= 0x1fffffff; 1154 tsbsize = 64; 1155 break; 1156 1157 case 0x40000000: 1158 dma_mask |= 0x3fffffff; 1159 tsbsize = 128; 1160 break; 1161 1162 case 0x80000000: 1163 dma_mask |= 0x7fffffff; 1164 tsbsize = 128; 1165 break; 1166 1167 default: 1168 printk(KERN_ERR PFX "Strange virtual-dma size.\n"); 1169 return -EINVAL; 1170 } 1171 1172 /* Register addresses, SCHIZO has iommu ctx flushing. */ 1173 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; 1174 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; 1175 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH; 1176 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL); 1177 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH; 1178 1179 /* We use the main control/status register of SCHIZO as the write 1180 * completion register. 1181 */ 1182 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL; 1183 1184 /* 1185 * Invalidate TLB Entries. 1186 */ 1187 control = upa_readq(iommu->iommu_control); 1188 control |= SCHIZO_IOMMU_CTRL_DENAB; 1189 upa_writeq(control, iommu->iommu_control); 1190 1191 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; 1192 1193 for (i = 0; i < 16; i++) { 1194 upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL)); 1195 upa_writeq(0, pbm->pbm_regs + database + (i * 8UL)); 1196 } 1197 1198 /* Leave diag mode enabled for full-flushing done 1199 * in pci_iommu.c 1200 */ 1201 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, 1202 pbm->numa_node); 1203 if (err) { 1204 printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err); 1205 return err; 1206 } 1207 1208 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); 1209 1210 control = upa_readq(iommu->iommu_control); 1211 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); 1212 switch (tsbsize) { 1213 case 64: 1214 control |= SCHIZO_IOMMU_TSBSZ_64K; 1215 break; 1216 case 128: 1217 control |= SCHIZO_IOMMU_TSBSZ_128K; 1218 break; 1219 } 1220 1221 control |= SCHIZO_IOMMU_CTRL_ENAB; 1222 upa_writeq(control, iommu->iommu_control); 1223 1224 return 0; 1225 } 1226 1227 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL) 1228 #define SCHIZO_IRQ_RETRY_INF 0xffUL 1229 1230 #define SCHIZO_PCI_DIAG (0x2020UL) 1231 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */ 1232 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */ 1233 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */ 1234 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */ 1235 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */ 1236 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */ 1237 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */ 1238 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */ 1239 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */ 1240 1241 #define TOMATILLO_PCI_IOC_CSR (0x2248UL) 1242 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL 1243 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL 1244 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL 1245 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL 1246 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL 1247 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL 1248 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL 1249 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL 1250 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL 1251 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL 1252 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL 1253 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL 1254 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL 1255 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL 1256 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL 1257 1258 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL) 1259 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL) 1260 1261 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) 1262 { 1263 u64 tmp; 1264 1265 upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY); 1266 1267 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1268 1269 /* Enable arbiter for all PCI slots. */ 1270 tmp |= 0xff; 1271 1272 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1273 pbm->chip_version >= 0x2) 1274 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; 1275 1276 if (!of_property_read_bool(pbm->op->dev.of_node, "no-bus-parking")) 1277 tmp |= SCHIZO_PCICTRL_PARK; 1278 else 1279 tmp &= ~SCHIZO_PCICTRL_PARK; 1280 1281 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1282 pbm->chip_version <= 0x1) 1283 tmp |= SCHIZO_PCICTRL_DTO_INT; 1284 else 1285 tmp &= ~SCHIZO_PCICTRL_DTO_INT; 1286 1287 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1288 tmp |= (SCHIZO_PCICTRL_MRM_PREF | 1289 SCHIZO_PCICTRL_RDO_PREF | 1290 SCHIZO_PCICTRL_RDL_PREF); 1291 1292 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1293 1294 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG); 1295 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | 1296 SCHIZO_PCIDIAG_D_RETRY | 1297 SCHIZO_PCIDIAG_D_INTSYNC); 1298 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG); 1299 1300 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1301 /* Clear prefetch lengths to workaround a bug in 1302 * Jalapeno... 1303 */ 1304 tmp = (TOMATILLO_IOC_PART_WPENAB | 1305 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) | 1306 TOMATILLO_IOC_RDMULT_CPENAB | 1307 TOMATILLO_IOC_RDONE_CPENAB | 1308 TOMATILLO_IOC_RDLINE_CPENAB); 1309 1310 upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR); 1311 } 1312 } 1313 1314 static int schizo_pbm_init(struct pci_pbm_info *pbm, 1315 struct platform_device *op, u32 portid, 1316 int chip_type) 1317 { 1318 const struct linux_prom64_registers *regs; 1319 struct device_node *dp = op->dev.of_node; 1320 const char *chipset_name; 1321 int err; 1322 1323 switch (chip_type) { 1324 case PBM_CHIP_TYPE_TOMATILLO: 1325 chipset_name = "TOMATILLO"; 1326 break; 1327 1328 case PBM_CHIP_TYPE_SCHIZO_PLUS: 1329 chipset_name = "SCHIZO+"; 1330 break; 1331 1332 case PBM_CHIP_TYPE_SCHIZO: 1333 default: 1334 chipset_name = "SCHIZO"; 1335 break; 1336 } 1337 1338 /* For SCHIZO, three OBP regs: 1339 * 1) PBM controller regs 1340 * 2) Schizo front-end controller regs (same for both PBMs) 1341 * 3) PBM PCI config space 1342 * 1343 * For TOMATILLO, four OBP regs: 1344 * 1) PBM controller regs 1345 * 2) Tomatillo front-end controller regs 1346 * 3) PBM PCI config space 1347 * 4) Ichip regs 1348 */ 1349 regs = of_get_property(dp, "reg", NULL); 1350 1351 pbm->next = pci_pbm_root; 1352 pci_pbm_root = pbm; 1353 1354 pbm->numa_node = NUMA_NO_NODE; 1355 1356 pbm->pci_ops = &sun4u_pci_ops; 1357 pbm->config_space_reg_bits = 8; 1358 1359 pbm->index = pci_num_pbms++; 1360 1361 pbm->portid = portid; 1362 pbm->op = op; 1363 1364 pbm->chip_type = chip_type; 1365 pbm->chip_version = of_getintprop_default(dp, "version#", 0); 1366 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0); 1367 1368 pbm->pbm_regs = regs[0].phys_addr; 1369 pbm->controller_regs = regs[1].phys_addr - 0x10000UL; 1370 1371 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) 1372 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL; 1373 1374 pbm->name = dp->full_name; 1375 1376 printk("%s: %s PCI Bus Module ver[%x:%x]\n", 1377 pbm->name, chipset_name, 1378 pbm->chip_version, pbm->chip_revision); 1379 1380 schizo_pbm_hw_init(pbm); 1381 1382 pci_determine_mem_io_space(pbm); 1383 1384 pci_get_pbm_props(pbm); 1385 1386 err = schizo_pbm_iommu_init(pbm); 1387 if (err) 1388 return err; 1389 1390 schizo_pbm_strbuf_init(pbm); 1391 1392 schizo_scan_bus(pbm, &op->dev); 1393 1394 return 0; 1395 } 1396 1397 static inline int portid_compare(u32 x, u32 y, int chip_type) 1398 { 1399 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1400 if (x == (y ^ 1)) 1401 return 1; 1402 return 0; 1403 } 1404 return (x == y); 1405 } 1406 1407 static struct pci_pbm_info *schizo_find_sibling(u32 portid, int chip_type) 1408 { 1409 struct pci_pbm_info *pbm; 1410 1411 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 1412 if (portid_compare(pbm->portid, portid, chip_type)) 1413 return pbm; 1414 } 1415 return NULL; 1416 } 1417 1418 static int __schizo_init(struct platform_device *op, unsigned long chip_type) 1419 { 1420 struct device_node *dp = op->dev.of_node; 1421 struct pci_pbm_info *pbm; 1422 struct iommu *iommu; 1423 u32 portid; 1424 int err; 1425 1426 portid = of_getintprop_default(dp, "portid", 0xff); 1427 1428 err = -ENOMEM; 1429 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); 1430 if (!pbm) { 1431 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); 1432 goto out_err; 1433 } 1434 1435 pbm->sibling = schizo_find_sibling(portid, chip_type); 1436 1437 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); 1438 if (!iommu) { 1439 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n"); 1440 goto out_free_pbm; 1441 } 1442 1443 pbm->iommu = iommu; 1444 1445 if (schizo_pbm_init(pbm, op, portid, chip_type)) 1446 goto out_free_iommu; 1447 1448 if (pbm->sibling) 1449 pbm->sibling->sibling = pbm; 1450 1451 dev_set_drvdata(&op->dev, pbm); 1452 1453 return 0; 1454 1455 out_free_iommu: 1456 kfree(pbm->iommu); 1457 1458 out_free_pbm: 1459 kfree(pbm); 1460 1461 out_err: 1462 return err; 1463 } 1464 1465 static int schizo_probe(struct platform_device *op) 1466 { 1467 unsigned long chip_type = (unsigned long)device_get_match_data(&op->dev); 1468 1469 if (!chip_type) 1470 return -EINVAL; 1471 return __schizo_init(op, chip_type); 1472 } 1473 1474 /* The ordering of this table is very important. Some Tomatillo 1475 * nodes announce that they are compatible with both pci108e,a801 1476 * and pci108e,8001. So list the chips in reverse chronological 1477 * order. 1478 */ 1479 static const struct of_device_id schizo_match[] = { 1480 { 1481 .name = "pci", 1482 .compatible = "pci108e,a801", 1483 .data = (void *) PBM_CHIP_TYPE_TOMATILLO, 1484 }, 1485 { 1486 .name = "pci", 1487 .compatible = "pci108e,8002", 1488 .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS, 1489 }, 1490 { 1491 .name = "pci", 1492 .compatible = "pci108e,8001", 1493 .data = (void *) PBM_CHIP_TYPE_SCHIZO, 1494 }, 1495 {}, 1496 }; 1497 1498 static struct platform_driver schizo_driver = { 1499 .driver = { 1500 .name = DRIVER_NAME, 1501 .of_match_table = schizo_match, 1502 }, 1503 .probe = schizo_probe, 1504 }; 1505 1506 static int __init schizo_init(void) 1507 { 1508 return platform_driver_register(&schizo_driver); 1509 } 1510 1511 subsys_initcall(schizo_init); 1512