1a88b5ba8SSam Ravnborg /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support. 2a88b5ba8SSam Ravnborg * 3a88b5ba8SSam Ravnborg * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net) 4a88b5ba8SSam Ravnborg */ 5a88b5ba8SSam Ravnborg 6a88b5ba8SSam Ravnborg #include <linux/kernel.h> 7a88b5ba8SSam Ravnborg #include <linux/types.h> 8a88b5ba8SSam Ravnborg #include <linux/pci.h> 9a88b5ba8SSam Ravnborg #include <linux/init.h> 10a88b5ba8SSam Ravnborg #include <linux/slab.h> 11a88b5ba8SSam Ravnborg #include <linux/interrupt.h> 12a88b5ba8SSam Ravnborg #include <linux/of_device.h> 13a88b5ba8SSam Ravnborg 14a88b5ba8SSam Ravnborg #include <asm/iommu.h> 15a88b5ba8SSam Ravnborg #include <asm/irq.h> 16a88b5ba8SSam Ravnborg #include <asm/pstate.h> 17a88b5ba8SSam Ravnborg #include <asm/prom.h> 18a88b5ba8SSam Ravnborg #include <asm/upa.h> 19a88b5ba8SSam Ravnborg 20a88b5ba8SSam Ravnborg #include "pci_impl.h" 21a88b5ba8SSam Ravnborg #include "iommu_common.h" 22a88b5ba8SSam Ravnborg 23a88b5ba8SSam Ravnborg #define DRIVER_NAME "schizo" 24a88b5ba8SSam Ravnborg #define PFX DRIVER_NAME ": " 25a88b5ba8SSam Ravnborg 26a88b5ba8SSam Ravnborg /* This is a convention that at least Excalibur and Merlin 27a88b5ba8SSam Ravnborg * follow. I suppose the SCHIZO used in Starcat and friends 28a88b5ba8SSam Ravnborg * will do similar. 29a88b5ba8SSam Ravnborg * 30a88b5ba8SSam Ravnborg * The only way I could see this changing is if the newlink 31a88b5ba8SSam Ravnborg * block requires more space in Schizo's address space than 32a88b5ba8SSam Ravnborg * they predicted, thus requiring an address space reorg when 33a88b5ba8SSam Ravnborg * the newer Schizo is taped out. 34a88b5ba8SSam Ravnborg */ 35a88b5ba8SSam Ravnborg 36a88b5ba8SSam Ravnborg /* Streaming buffer control register. */ 37a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ 38a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ 39a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ 40a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ 41a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ 42a88b5ba8SSam Ravnborg 43a88b5ba8SSam Ravnborg /* IOMMU control register. */ 44a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ 45a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ 46a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ 47a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ 48a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ 49a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ 50a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ 51a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ 52a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ 53a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ 54a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ 55a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ 56a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ 57a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ 58a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ 59a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ 60a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ 61a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ 62a88b5ba8SSam Ravnborg 63a88b5ba8SSam Ravnborg /* Schizo config space address format is nearly identical to 64a88b5ba8SSam Ravnborg * that of PSYCHO: 65a88b5ba8SSam Ravnborg * 66a88b5ba8SSam Ravnborg * 32 24 23 16 15 11 10 8 7 2 1 0 67a88b5ba8SSam Ravnborg * --------------------------------------------------------- 68a88b5ba8SSam Ravnborg * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 | 69a88b5ba8SSam Ravnborg * --------------------------------------------------------- 70a88b5ba8SSam Ravnborg */ 71a88b5ba8SSam Ravnborg #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space) 72a88b5ba8SSam Ravnborg #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ 73a88b5ba8SSam Ravnborg (((unsigned long)(BUS) << 16) | \ 74a88b5ba8SSam Ravnborg ((unsigned long)(DEVFN) << 8) | \ 75a88b5ba8SSam Ravnborg ((unsigned long)(REG))) 76a88b5ba8SSam Ravnborg 77a88b5ba8SSam Ravnborg static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm, 78a88b5ba8SSam Ravnborg unsigned char bus, 79a88b5ba8SSam Ravnborg unsigned int devfn, 80a88b5ba8SSam Ravnborg int where) 81a88b5ba8SSam Ravnborg { 82a88b5ba8SSam Ravnborg if (!pbm) 83a88b5ba8SSam Ravnborg return NULL; 84a88b5ba8SSam Ravnborg bus -= pbm->pci_first_busno; 85a88b5ba8SSam Ravnborg return (void *) 86a88b5ba8SSam Ravnborg (SCHIZO_CONFIG_BASE(pbm) | 87a88b5ba8SSam Ravnborg SCHIZO_CONFIG_ENCODE(bus, devfn, where)); 88a88b5ba8SSam Ravnborg } 89a88b5ba8SSam Ravnborg 90a88b5ba8SSam Ravnborg /* SCHIZO error handling support. */ 91a88b5ba8SSam Ravnborg enum schizo_error_type { 92a88b5ba8SSam Ravnborg UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR 93a88b5ba8SSam Ravnborg }; 94a88b5ba8SSam Ravnborg 95a88b5ba8SSam Ravnborg static DEFINE_SPINLOCK(stc_buf_lock); 96a88b5ba8SSam Ravnborg static unsigned long stc_error_buf[128]; 97a88b5ba8SSam Ravnborg static unsigned long stc_tag_buf[16]; 98a88b5ba8SSam Ravnborg static unsigned long stc_line_buf[16]; 99a88b5ba8SSam Ravnborg 100a88b5ba8SSam Ravnborg #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */ 101a88b5ba8SSam Ravnborg #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */ 102a88b5ba8SSam Ravnborg #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */ 103a88b5ba8SSam Ravnborg #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */ 104a88b5ba8SSam Ravnborg #define SCHIZO_SERR_INO 0x34 /* Safari interface error */ 105a88b5ba8SSam Ravnborg 106a88b5ba8SSam Ravnborg #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ 107a88b5ba8SSam Ravnborg #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ 108a88b5ba8SSam Ravnborg #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ 109a88b5ba8SSam Ravnborg 110a88b5ba8SSam Ravnborg #define SCHIZO_STCERR_WRITE 0x2UL 111a88b5ba8SSam Ravnborg #define SCHIZO_STCERR_READ 0x1UL 112a88b5ba8SSam Ravnborg 113a88b5ba8SSam Ravnborg #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL 114a88b5ba8SSam Ravnborg #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL 115a88b5ba8SSam Ravnborg #define SCHIZO_STCTAG_VALID 0x8000000000000000UL 116a88b5ba8SSam Ravnborg #define SCHIZO_STCTAG_READ 0x4000000000000000UL 117a88b5ba8SSam Ravnborg 118a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL 119a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL 120a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL 121a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL 122a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_VALID 0x0000000000600000UL 123a88b5ba8SSam Ravnborg #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL 124a88b5ba8SSam Ravnborg 125a88b5ba8SSam Ravnborg static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm, 126a88b5ba8SSam Ravnborg enum schizo_error_type type) 127a88b5ba8SSam Ravnborg { 128a88b5ba8SSam Ravnborg struct strbuf *strbuf = &pbm->stc; 129a88b5ba8SSam Ravnborg unsigned long regbase = pbm->pbm_regs; 130a88b5ba8SSam Ravnborg unsigned long err_base, tag_base, line_base; 131a88b5ba8SSam Ravnborg u64 control; 132a88b5ba8SSam Ravnborg int i; 133a88b5ba8SSam Ravnborg 134a88b5ba8SSam Ravnborg err_base = regbase + SCHIZO_STC_ERR; 135a88b5ba8SSam Ravnborg tag_base = regbase + SCHIZO_STC_TAG; 136a88b5ba8SSam Ravnborg line_base = regbase + SCHIZO_STC_LINE; 137a88b5ba8SSam Ravnborg 138a88b5ba8SSam Ravnborg spin_lock(&stc_buf_lock); 139a88b5ba8SSam Ravnborg 140a88b5ba8SSam Ravnborg /* This is __REALLY__ dangerous. When we put the 141a88b5ba8SSam Ravnborg * streaming buffer into diagnostic mode to probe 142a88b5ba8SSam Ravnborg * it's tags and error status, we _must_ clear all 143a88b5ba8SSam Ravnborg * of the line tag valid bits before re-enabling 144a88b5ba8SSam Ravnborg * the streaming buffer. If any dirty data lives 145a88b5ba8SSam Ravnborg * in the STC when we do this, we will end up 146a88b5ba8SSam Ravnborg * invalidating it before it has a chance to reach 147a88b5ba8SSam Ravnborg * main memory. 148a88b5ba8SSam Ravnborg */ 149a88b5ba8SSam Ravnborg control = upa_readq(strbuf->strbuf_control); 150a88b5ba8SSam Ravnborg upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB), 151a88b5ba8SSam Ravnborg strbuf->strbuf_control); 152a88b5ba8SSam Ravnborg for (i = 0; i < 128; i++) { 153a88b5ba8SSam Ravnborg unsigned long val; 154a88b5ba8SSam Ravnborg 155a88b5ba8SSam Ravnborg val = upa_readq(err_base + (i * 8UL)); 156a88b5ba8SSam Ravnborg upa_writeq(0UL, err_base + (i * 8UL)); 157a88b5ba8SSam Ravnborg stc_error_buf[i] = val; 158a88b5ba8SSam Ravnborg } 159a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) { 160a88b5ba8SSam Ravnborg stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL)); 161a88b5ba8SSam Ravnborg stc_line_buf[i] = upa_readq(line_base + (i * 8UL)); 162a88b5ba8SSam Ravnborg upa_writeq(0UL, tag_base + (i * 8UL)); 163a88b5ba8SSam Ravnborg upa_writeq(0UL, line_base + (i * 8UL)); 164a88b5ba8SSam Ravnborg } 165a88b5ba8SSam Ravnborg 166a88b5ba8SSam Ravnborg /* OK, state is logged, exit diagnostic mode. */ 167a88b5ba8SSam Ravnborg upa_writeq(control, strbuf->strbuf_control); 168a88b5ba8SSam Ravnborg 169a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) { 170a88b5ba8SSam Ravnborg int j, saw_error, first, last; 171a88b5ba8SSam Ravnborg 172a88b5ba8SSam Ravnborg saw_error = 0; 173a88b5ba8SSam Ravnborg first = i * 8; 174a88b5ba8SSam Ravnborg last = first + 8; 175a88b5ba8SSam Ravnborg for (j = first; j < last; j++) { 176a88b5ba8SSam Ravnborg unsigned long errval = stc_error_buf[j]; 177a88b5ba8SSam Ravnborg if (errval != 0) { 178a88b5ba8SSam Ravnborg saw_error++; 179a88b5ba8SSam Ravnborg printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n", 180a88b5ba8SSam Ravnborg pbm->name, 181a88b5ba8SSam Ravnborg j, 182a88b5ba8SSam Ravnborg (errval & SCHIZO_STCERR_WRITE) ? 1 : 0, 183a88b5ba8SSam Ravnborg (errval & SCHIZO_STCERR_READ) ? 1 : 0); 184a88b5ba8SSam Ravnborg } 185a88b5ba8SSam Ravnborg } 186a88b5ba8SSam Ravnborg if (saw_error != 0) { 187a88b5ba8SSam Ravnborg unsigned long tagval = stc_tag_buf[i]; 188a88b5ba8SSam Ravnborg unsigned long lineval = stc_line_buf[i]; 189a88b5ba8SSam Ravnborg printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n", 190a88b5ba8SSam Ravnborg pbm->name, 191a88b5ba8SSam Ravnborg i, 192a88b5ba8SSam Ravnborg ((tagval & SCHIZO_STCTAG_PPN) >> 19UL), 193a88b5ba8SSam Ravnborg (tagval & SCHIZO_STCTAG_VPN), 194a88b5ba8SSam Ravnborg ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0), 195a88b5ba8SSam Ravnborg ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0)); 196a88b5ba8SSam Ravnborg 197a88b5ba8SSam Ravnborg /* XXX Should spit out per-bank error information... -DaveM */ 198a88b5ba8SSam Ravnborg printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" 199a88b5ba8SSam Ravnborg "V(%d)FOFN(%d)]\n", 200a88b5ba8SSam Ravnborg pbm->name, 201a88b5ba8SSam Ravnborg i, 202a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL), 203a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL), 204a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL), 205a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL), 206a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0), 207a88b5ba8SSam Ravnborg ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0)); 208a88b5ba8SSam Ravnborg } 209a88b5ba8SSam Ravnborg } 210a88b5ba8SSam Ravnborg 211a88b5ba8SSam Ravnborg spin_unlock(&stc_buf_lock); 212a88b5ba8SSam Ravnborg } 213a88b5ba8SSam Ravnborg 214a88b5ba8SSam Ravnborg /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous 215a88b5ba8SSam Ravnborg * controller level errors. 216a88b5ba8SSam Ravnborg */ 217a88b5ba8SSam Ravnborg 218a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG 0xa580UL 219a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_DATA 0xa600UL 220a88b5ba8SSam Ravnborg 221a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL 222a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL 223a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL 224a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL 225a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL 226a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL 227a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL 228a88b5ba8SSam Ravnborg 229a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL 230a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL 231a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL 232a88b5ba8SSam Ravnborg 233a88b5ba8SSam Ravnborg static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm, 234a88b5ba8SSam Ravnborg enum schizo_error_type type) 235a88b5ba8SSam Ravnborg { 236a88b5ba8SSam Ravnborg struct iommu *iommu = pbm->iommu; 237a88b5ba8SSam Ravnborg unsigned long iommu_tag[16]; 238a88b5ba8SSam Ravnborg unsigned long iommu_data[16]; 239a88b5ba8SSam Ravnborg unsigned long flags; 240a88b5ba8SSam Ravnborg u64 control; 241a88b5ba8SSam Ravnborg int i; 242a88b5ba8SSam Ravnborg 243a88b5ba8SSam Ravnborg spin_lock_irqsave(&iommu->lock, flags); 244a88b5ba8SSam Ravnborg control = upa_readq(iommu->iommu_control); 245a88b5ba8SSam Ravnborg if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { 246a88b5ba8SSam Ravnborg unsigned long base; 247a88b5ba8SSam Ravnborg char *type_string; 248a88b5ba8SSam Ravnborg 249a88b5ba8SSam Ravnborg /* Clear the error encountered bit. */ 250a88b5ba8SSam Ravnborg control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; 251a88b5ba8SSam Ravnborg upa_writeq(control, iommu->iommu_control); 252a88b5ba8SSam Ravnborg 253a88b5ba8SSam Ravnborg switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { 254a88b5ba8SSam Ravnborg case 0: 255a88b5ba8SSam Ravnborg type_string = "Protection Error"; 256a88b5ba8SSam Ravnborg break; 257a88b5ba8SSam Ravnborg case 1: 258a88b5ba8SSam Ravnborg type_string = "Invalid Error"; 259a88b5ba8SSam Ravnborg break; 260a88b5ba8SSam Ravnborg case 2: 261a88b5ba8SSam Ravnborg type_string = "TimeOut Error"; 262a88b5ba8SSam Ravnborg break; 263a88b5ba8SSam Ravnborg case 3: 264a88b5ba8SSam Ravnborg default: 265a88b5ba8SSam Ravnborg type_string = "ECC Error"; 266a88b5ba8SSam Ravnborg break; 267a88b5ba8SSam Ravnborg }; 268a88b5ba8SSam Ravnborg printk("%s: IOMMU Error, type[%s]\n", 269a88b5ba8SSam Ravnborg pbm->name, type_string); 270a88b5ba8SSam Ravnborg 271a88b5ba8SSam Ravnborg /* Put the IOMMU into diagnostic mode and probe 272a88b5ba8SSam Ravnborg * it's TLB for entries with error status. 273a88b5ba8SSam Ravnborg * 274a88b5ba8SSam Ravnborg * It is very possible for another DVMA to occur 275a88b5ba8SSam Ravnborg * while we do this probe, and corrupt the system 276a88b5ba8SSam Ravnborg * further. But we are so screwed at this point 277a88b5ba8SSam Ravnborg * that we are likely to crash hard anyways, so 278a88b5ba8SSam Ravnborg * get as much diagnostic information to the 279a88b5ba8SSam Ravnborg * console as we can. 280a88b5ba8SSam Ravnborg */ 281a88b5ba8SSam Ravnborg upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB, 282a88b5ba8SSam Ravnborg iommu->iommu_control); 283a88b5ba8SSam Ravnborg 284a88b5ba8SSam Ravnborg base = pbm->pbm_regs; 285a88b5ba8SSam Ravnborg 286a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) { 287a88b5ba8SSam Ravnborg iommu_tag[i] = 288a88b5ba8SSam Ravnborg upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL)); 289a88b5ba8SSam Ravnborg iommu_data[i] = 290a88b5ba8SSam Ravnborg upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL)); 291a88b5ba8SSam Ravnborg 292a88b5ba8SSam Ravnborg /* Now clear out the entry. */ 293a88b5ba8SSam Ravnborg upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL)); 294a88b5ba8SSam Ravnborg upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL)); 295a88b5ba8SSam Ravnborg } 296a88b5ba8SSam Ravnborg 297a88b5ba8SSam Ravnborg /* Leave diagnostic mode. */ 298a88b5ba8SSam Ravnborg upa_writeq(control, iommu->iommu_control); 299a88b5ba8SSam Ravnborg 300a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) { 301a88b5ba8SSam Ravnborg unsigned long tag, data; 302a88b5ba8SSam Ravnborg 303a88b5ba8SSam Ravnborg tag = iommu_tag[i]; 304a88b5ba8SSam Ravnborg if (!(tag & SCHIZO_IOMMU_TAG_ERR)) 305a88b5ba8SSam Ravnborg continue; 306a88b5ba8SSam Ravnborg 307a88b5ba8SSam Ravnborg data = iommu_data[i]; 308a88b5ba8SSam Ravnborg switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) { 309a88b5ba8SSam Ravnborg case 0: 310a88b5ba8SSam Ravnborg type_string = "Protection Error"; 311a88b5ba8SSam Ravnborg break; 312a88b5ba8SSam Ravnborg case 1: 313a88b5ba8SSam Ravnborg type_string = "Invalid Error"; 314a88b5ba8SSam Ravnborg break; 315a88b5ba8SSam Ravnborg case 2: 316a88b5ba8SSam Ravnborg type_string = "TimeOut Error"; 317a88b5ba8SSam Ravnborg break; 318a88b5ba8SSam Ravnborg case 3: 319a88b5ba8SSam Ravnborg default: 320a88b5ba8SSam Ravnborg type_string = "ECC Error"; 321a88b5ba8SSam Ravnborg break; 322a88b5ba8SSam Ravnborg }; 323a88b5ba8SSam Ravnborg printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) " 324a88b5ba8SSam Ravnborg "sz(%dK) vpg(%08lx)]\n", 325a88b5ba8SSam Ravnborg pbm->name, i, type_string, 326a88b5ba8SSam Ravnborg (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL), 327a88b5ba8SSam Ravnborg ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0), 328a88b5ba8SSam Ravnborg ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0), 329a88b5ba8SSam Ravnborg ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8), 330a88b5ba8SSam Ravnborg (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); 331a88b5ba8SSam Ravnborg printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", 332a88b5ba8SSam Ravnborg pbm->name, i, 333a88b5ba8SSam Ravnborg ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0), 334a88b5ba8SSam Ravnborg ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0), 335a88b5ba8SSam Ravnborg (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); 336a88b5ba8SSam Ravnborg } 337a88b5ba8SSam Ravnborg } 338a88b5ba8SSam Ravnborg if (pbm->stc.strbuf_enabled) 339a88b5ba8SSam Ravnborg __schizo_check_stc_error_pbm(pbm, type); 340a88b5ba8SSam Ravnborg spin_unlock_irqrestore(&iommu->lock, flags); 341a88b5ba8SSam Ravnborg } 342a88b5ba8SSam Ravnborg 343a88b5ba8SSam Ravnborg static void schizo_check_iommu_error(struct pci_pbm_info *pbm, 344a88b5ba8SSam Ravnborg enum schizo_error_type type) 345a88b5ba8SSam Ravnborg { 346a88b5ba8SSam Ravnborg schizo_check_iommu_error_pbm(pbm, type); 347a88b5ba8SSam Ravnborg if (pbm->sibling) 348a88b5ba8SSam Ravnborg schizo_check_iommu_error_pbm(pbm->sibling, type); 349a88b5ba8SSam Ravnborg } 350a88b5ba8SSam Ravnborg 351a88b5ba8SSam Ravnborg /* Uncorrectable ECC error status gathering. */ 352a88b5ba8SSam Ravnborg #define SCHIZO_UE_AFSR 0x10030UL 353a88b5ba8SSam Ravnborg #define SCHIZO_UE_AFAR 0x10038UL 354a88b5ba8SSam Ravnborg 355a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */ 356a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */ 357a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */ 358a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */ 359a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */ 360a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */ 361a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */ 362a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */ 363a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */ 364a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */ 365a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */ 366a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */ 367a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */ 368a88b5ba8SSam Ravnborg #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */ 369a88b5ba8SSam Ravnborg 370a88b5ba8SSam Ravnborg static irqreturn_t schizo_ue_intr(int irq, void *dev_id) 371a88b5ba8SSam Ravnborg { 372a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm = dev_id; 373a88b5ba8SSam Ravnborg unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR; 374a88b5ba8SSam Ravnborg unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR; 375a88b5ba8SSam Ravnborg unsigned long afsr, afar, error_bits; 376a88b5ba8SSam Ravnborg int reported, limit; 377a88b5ba8SSam Ravnborg 378a88b5ba8SSam Ravnborg /* Latch uncorrectable error status. */ 379a88b5ba8SSam Ravnborg afar = upa_readq(afar_reg); 380a88b5ba8SSam Ravnborg 381a88b5ba8SSam Ravnborg /* If either of the error pending bits are set in the 382a88b5ba8SSam Ravnborg * AFSR, the error status is being actively updated by 383a88b5ba8SSam Ravnborg * the hardware and we must re-read to get a clean value. 384a88b5ba8SSam Ravnborg */ 385a88b5ba8SSam Ravnborg limit = 1000; 386a88b5ba8SSam Ravnborg do { 387a88b5ba8SSam Ravnborg afsr = upa_readq(afsr_reg); 388a88b5ba8SSam Ravnborg } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 389a88b5ba8SSam Ravnborg 390a88b5ba8SSam Ravnborg /* Clear the primary/secondary error status bits. */ 391a88b5ba8SSam Ravnborg error_bits = afsr & 392a88b5ba8SSam Ravnborg (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR | 393a88b5ba8SSam Ravnborg SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); 394a88b5ba8SSam Ravnborg if (!error_bits) 395a88b5ba8SSam Ravnborg return IRQ_NONE; 396a88b5ba8SSam Ravnborg upa_writeq(error_bits, afsr_reg); 397a88b5ba8SSam Ravnborg 398a88b5ba8SSam Ravnborg /* Log the error. */ 399a88b5ba8SSam Ravnborg printk("%s: Uncorrectable Error, primary error type[%s]\n", 400a88b5ba8SSam Ravnborg pbm->name, 401a88b5ba8SSam Ravnborg (((error_bits & SCHIZO_UEAFSR_PPIO) ? 402a88b5ba8SSam Ravnborg "PIO" : 403a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_UEAFSR_PDRD) ? 404a88b5ba8SSam Ravnborg "DMA Read" : 405a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_UEAFSR_PDWR) ? 406a88b5ba8SSam Ravnborg "DMA Write" : "???"))))); 407a88b5ba8SSam Ravnborg printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 408a88b5ba8SSam Ravnborg pbm->name, 409a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 410a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 411a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 412a88b5ba8SSam Ravnborg printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 413a88b5ba8SSam Ravnborg pbm->name, 414a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 415a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 416a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 417a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 418a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 419a88b5ba8SSam Ravnborg printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); 420a88b5ba8SSam Ravnborg printk("%s: UE Secondary errors [", pbm->name); 421a88b5ba8SSam Ravnborg reported = 0; 422a88b5ba8SSam Ravnborg if (afsr & SCHIZO_UEAFSR_SPIO) { 423a88b5ba8SSam Ravnborg reported++; 424a88b5ba8SSam Ravnborg printk("(PIO)"); 425a88b5ba8SSam Ravnborg } 426a88b5ba8SSam Ravnborg if (afsr & SCHIZO_UEAFSR_SDMA) { 427a88b5ba8SSam Ravnborg reported++; 428a88b5ba8SSam Ravnborg printk("(DMA)"); 429a88b5ba8SSam Ravnborg } 430a88b5ba8SSam Ravnborg if (!reported) 431a88b5ba8SSam Ravnborg printk("(none)"); 432a88b5ba8SSam Ravnborg printk("]\n"); 433a88b5ba8SSam Ravnborg 434a88b5ba8SSam Ravnborg /* Interrogate IOMMU for error status. */ 435a88b5ba8SSam Ravnborg schizo_check_iommu_error(pbm, UE_ERR); 436a88b5ba8SSam Ravnborg 437a88b5ba8SSam Ravnborg return IRQ_HANDLED; 438a88b5ba8SSam Ravnborg } 439a88b5ba8SSam Ravnborg 440a88b5ba8SSam Ravnborg #define SCHIZO_CE_AFSR 0x10040UL 441a88b5ba8SSam Ravnborg #define SCHIZO_CE_AFAR 0x10048UL 442a88b5ba8SSam Ravnborg 443a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL 444a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL 445a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL 446a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL 447a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL 448a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL 449a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL 450a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL 451a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_AID 0x000000001f000000UL 452a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL 453a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL 454a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL 455a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL 456a88b5ba8SSam Ravnborg #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL 457a88b5ba8SSam Ravnborg 458a88b5ba8SSam Ravnborg static irqreturn_t schizo_ce_intr(int irq, void *dev_id) 459a88b5ba8SSam Ravnborg { 460a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm = dev_id; 461a88b5ba8SSam Ravnborg unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR; 462a88b5ba8SSam Ravnborg unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR; 463a88b5ba8SSam Ravnborg unsigned long afsr, afar, error_bits; 464a88b5ba8SSam Ravnborg int reported, limit; 465a88b5ba8SSam Ravnborg 466a88b5ba8SSam Ravnborg /* Latch error status. */ 467a88b5ba8SSam Ravnborg afar = upa_readq(afar_reg); 468a88b5ba8SSam Ravnborg 469a88b5ba8SSam Ravnborg /* If either of the error pending bits are set in the 470a88b5ba8SSam Ravnborg * AFSR, the error status is being actively updated by 471a88b5ba8SSam Ravnborg * the hardware and we must re-read to get a clean value. 472a88b5ba8SSam Ravnborg */ 473a88b5ba8SSam Ravnborg limit = 1000; 474a88b5ba8SSam Ravnborg do { 475a88b5ba8SSam Ravnborg afsr = upa_readq(afsr_reg); 476a88b5ba8SSam Ravnborg } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 477a88b5ba8SSam Ravnborg 478a88b5ba8SSam Ravnborg /* Clear primary/secondary error status bits. */ 479a88b5ba8SSam Ravnborg error_bits = afsr & 480a88b5ba8SSam Ravnborg (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR | 481a88b5ba8SSam Ravnborg SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); 482a88b5ba8SSam Ravnborg if (!error_bits) 483a88b5ba8SSam Ravnborg return IRQ_NONE; 484a88b5ba8SSam Ravnborg upa_writeq(error_bits, afsr_reg); 485a88b5ba8SSam Ravnborg 486a88b5ba8SSam Ravnborg /* Log the error. */ 487a88b5ba8SSam Ravnborg printk("%s: Correctable Error, primary error type[%s]\n", 488a88b5ba8SSam Ravnborg pbm->name, 489a88b5ba8SSam Ravnborg (((error_bits & SCHIZO_CEAFSR_PPIO) ? 490a88b5ba8SSam Ravnborg "PIO" : 491a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_CEAFSR_PDRD) ? 492a88b5ba8SSam Ravnborg "DMA Read" : 493a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_CEAFSR_PDWR) ? 494a88b5ba8SSam Ravnborg "DMA Write" : "???"))))); 495a88b5ba8SSam Ravnborg 496a88b5ba8SSam Ravnborg /* XXX Use syndrome and afar to print out module string just like 497a88b5ba8SSam Ravnborg * XXX UDB CE trap handler does... -DaveM 498a88b5ba8SSam Ravnborg */ 499a88b5ba8SSam Ravnborg printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 500a88b5ba8SSam Ravnborg pbm->name, 501a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 502a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 503a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 504a88b5ba8SSam Ravnborg printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 505a88b5ba8SSam Ravnborg pbm->name, 506a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 507a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 508a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 509a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 510a88b5ba8SSam Ravnborg (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 511a88b5ba8SSam Ravnborg printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); 512a88b5ba8SSam Ravnborg printk("%s: CE Secondary errors [", pbm->name); 513a88b5ba8SSam Ravnborg reported = 0; 514a88b5ba8SSam Ravnborg if (afsr & SCHIZO_CEAFSR_SPIO) { 515a88b5ba8SSam Ravnborg reported++; 516a88b5ba8SSam Ravnborg printk("(PIO)"); 517a88b5ba8SSam Ravnborg } 518a88b5ba8SSam Ravnborg if (afsr & SCHIZO_CEAFSR_SDMA) { 519a88b5ba8SSam Ravnborg reported++; 520a88b5ba8SSam Ravnborg printk("(DMA)"); 521a88b5ba8SSam Ravnborg } 522a88b5ba8SSam Ravnborg if (!reported) 523a88b5ba8SSam Ravnborg printk("(none)"); 524a88b5ba8SSam Ravnborg printk("]\n"); 525a88b5ba8SSam Ravnborg 526a88b5ba8SSam Ravnborg return IRQ_HANDLED; 527a88b5ba8SSam Ravnborg } 528a88b5ba8SSam Ravnborg 529a88b5ba8SSam Ravnborg #define SCHIZO_PCI_AFSR 0x2010UL 530a88b5ba8SSam Ravnborg #define SCHIZO_PCI_AFAR 0x2018UL 531a88b5ba8SSam Ravnborg 532a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */ 533a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */ 534a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */ 535a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */ 536a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */ 537a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */ 538a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */ 539a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */ 540a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */ 541a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */ 542a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */ 543a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */ 544a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */ 545a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */ 546a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */ 547a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */ 548a88b5ba8SSam Ravnborg #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */ 549a88b5ba8SSam Ravnborg 550a88b5ba8SSam Ravnborg #define SCHIZO_PCI_CTRL (0x2000UL) 551a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */ 552a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */ 553a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */ 554a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */ 555a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */ 556a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */ 557a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */ 558a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */ 559a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */ 560a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */ 561a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */ 562a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */ 563a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */ 564a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */ 565a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */ 566a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PTO_SHIFT 24UL 567a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */ 568a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */ 569a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */ 570a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */ 571a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */ 572a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */ 573a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */ 574a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */ 575a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */ 576a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */ 577a88b5ba8SSam Ravnborg #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */ 578a88b5ba8SSam Ravnborg 579a88b5ba8SSam Ravnborg static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm) 580a88b5ba8SSam Ravnborg { 581a88b5ba8SSam Ravnborg unsigned long csr_reg, csr, csr_error_bits; 582a88b5ba8SSam Ravnborg irqreturn_t ret = IRQ_NONE; 583a88b5ba8SSam Ravnborg u16 stat; 584a88b5ba8SSam Ravnborg 585a88b5ba8SSam Ravnborg csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; 586a88b5ba8SSam Ravnborg csr = upa_readq(csr_reg); 587a88b5ba8SSam Ravnborg csr_error_bits = 588a88b5ba8SSam Ravnborg csr & (SCHIZO_PCICTRL_BUS_UNUS | 589a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_TTO_ERR | 590a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RTRY_ERR | 591a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_DTO_ERR | 592a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SBH_ERR | 593a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SERR); 594a88b5ba8SSam Ravnborg if (csr_error_bits) { 595a88b5ba8SSam Ravnborg /* Clear the errors. */ 596a88b5ba8SSam Ravnborg upa_writeq(csr, csr_reg); 597a88b5ba8SSam Ravnborg 598a88b5ba8SSam Ravnborg /* Log 'em. */ 599a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) 600a88b5ba8SSam Ravnborg printk("%s: Bus unusable error asserted.\n", 601a88b5ba8SSam Ravnborg pbm->name); 602a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR) 603a88b5ba8SSam Ravnborg printk("%s: PCI TRDY# timeout error asserted.\n", 604a88b5ba8SSam Ravnborg pbm->name); 605a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR) 606a88b5ba8SSam Ravnborg printk("%s: PCI excessive retry error asserted.\n", 607a88b5ba8SSam Ravnborg pbm->name); 608a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR) 609a88b5ba8SSam Ravnborg printk("%s: PCI discard timeout error asserted.\n", 610a88b5ba8SSam Ravnborg pbm->name); 611a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR) 612a88b5ba8SSam Ravnborg printk("%s: PCI streaming byte hole error asserted.\n", 613a88b5ba8SSam Ravnborg pbm->name); 614a88b5ba8SSam Ravnborg if (csr_error_bits & SCHIZO_PCICTRL_SERR) 615a88b5ba8SSam Ravnborg printk("%s: PCI SERR signal asserted.\n", 616a88b5ba8SSam Ravnborg pbm->name); 617a88b5ba8SSam Ravnborg ret = IRQ_HANDLED; 618a88b5ba8SSam Ravnborg } 619a88b5ba8SSam Ravnborg pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat); 620a88b5ba8SSam Ravnborg if (stat & (PCI_STATUS_PARITY | 621a88b5ba8SSam Ravnborg PCI_STATUS_SIG_TARGET_ABORT | 622a88b5ba8SSam Ravnborg PCI_STATUS_REC_TARGET_ABORT | 623a88b5ba8SSam Ravnborg PCI_STATUS_REC_MASTER_ABORT | 624a88b5ba8SSam Ravnborg PCI_STATUS_SIG_SYSTEM_ERROR)) { 625a88b5ba8SSam Ravnborg printk("%s: PCI bus error, PCI_STATUS[%04x]\n", 626a88b5ba8SSam Ravnborg pbm->name, stat); 627a88b5ba8SSam Ravnborg pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff); 628a88b5ba8SSam Ravnborg ret = IRQ_HANDLED; 629a88b5ba8SSam Ravnborg } 630a88b5ba8SSam Ravnborg return ret; 631a88b5ba8SSam Ravnborg } 632a88b5ba8SSam Ravnborg 633a88b5ba8SSam Ravnborg static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id) 634a88b5ba8SSam Ravnborg { 635a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm = dev_id; 636a88b5ba8SSam Ravnborg unsigned long afsr_reg, afar_reg, base; 637a88b5ba8SSam Ravnborg unsigned long afsr, afar, error_bits; 638a88b5ba8SSam Ravnborg int reported; 639a88b5ba8SSam Ravnborg 640a88b5ba8SSam Ravnborg base = pbm->pbm_regs; 641a88b5ba8SSam Ravnborg 642a88b5ba8SSam Ravnborg afsr_reg = base + SCHIZO_PCI_AFSR; 643a88b5ba8SSam Ravnborg afar_reg = base + SCHIZO_PCI_AFAR; 644a88b5ba8SSam Ravnborg 645a88b5ba8SSam Ravnborg /* Latch error status. */ 646a88b5ba8SSam Ravnborg afar = upa_readq(afar_reg); 647a88b5ba8SSam Ravnborg afsr = upa_readq(afsr_reg); 648a88b5ba8SSam Ravnborg 649a88b5ba8SSam Ravnborg /* Clear primary/secondary error status bits. */ 650a88b5ba8SSam Ravnborg error_bits = afsr & 651a88b5ba8SSam Ravnborg (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 652a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 653a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 654a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 655a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 656a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); 657a88b5ba8SSam Ravnborg if (!error_bits) 658a88b5ba8SSam Ravnborg return schizo_pcierr_intr_other(pbm); 659a88b5ba8SSam Ravnborg upa_writeq(error_bits, afsr_reg); 660a88b5ba8SSam Ravnborg 661a88b5ba8SSam Ravnborg /* Log the error. */ 662a88b5ba8SSam Ravnborg printk("%s: PCI Error, primary error type[%s]\n", 663a88b5ba8SSam Ravnborg pbm->name, 664a88b5ba8SSam Ravnborg (((error_bits & SCHIZO_PCIAFSR_PMA) ? 665a88b5ba8SSam Ravnborg "Master Abort" : 666a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PTA) ? 667a88b5ba8SSam Ravnborg "Target Abort" : 668a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PRTRY) ? 669a88b5ba8SSam Ravnborg "Excessive Retries" : 670a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PPERR) ? 671a88b5ba8SSam Ravnborg "Parity Error" : 672a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PTTO) ? 673a88b5ba8SSam Ravnborg "Timeout" : 674a88b5ba8SSam Ravnborg ((error_bits & SCHIZO_PCIAFSR_PUNUS) ? 675a88b5ba8SSam Ravnborg "Bus Unusable" : "???")))))))); 676a88b5ba8SSam Ravnborg printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n", 677a88b5ba8SSam Ravnborg pbm->name, 678a88b5ba8SSam Ravnborg (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL, 679a88b5ba8SSam Ravnborg (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0, 680a88b5ba8SSam Ravnborg ((afsr & SCHIZO_PCIAFSR_CFG) ? 681a88b5ba8SSam Ravnborg "Config" : 682a88b5ba8SSam Ravnborg ((afsr & SCHIZO_PCIAFSR_MEM) ? 683a88b5ba8SSam Ravnborg "Memory" : 684a88b5ba8SSam Ravnborg ((afsr & SCHIZO_PCIAFSR_IO) ? 685a88b5ba8SSam Ravnborg "I/O" : "???")))); 686a88b5ba8SSam Ravnborg printk("%s: PCI AFAR [%016lx]\n", 687a88b5ba8SSam Ravnborg pbm->name, afar); 688a88b5ba8SSam Ravnborg printk("%s: PCI Secondary errors [", 689a88b5ba8SSam Ravnborg pbm->name); 690a88b5ba8SSam Ravnborg reported = 0; 691a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_SMA) { 692a88b5ba8SSam Ravnborg reported++; 693a88b5ba8SSam Ravnborg printk("(Master Abort)"); 694a88b5ba8SSam Ravnborg } 695a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_STA) { 696a88b5ba8SSam Ravnborg reported++; 697a88b5ba8SSam Ravnborg printk("(Target Abort)"); 698a88b5ba8SSam Ravnborg } 699a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_SRTRY) { 700a88b5ba8SSam Ravnborg reported++; 701a88b5ba8SSam Ravnborg printk("(Excessive Retries)"); 702a88b5ba8SSam Ravnborg } 703a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_SPERR) { 704a88b5ba8SSam Ravnborg reported++; 705a88b5ba8SSam Ravnborg printk("(Parity Error)"); 706a88b5ba8SSam Ravnborg } 707a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_STTO) { 708a88b5ba8SSam Ravnborg reported++; 709a88b5ba8SSam Ravnborg printk("(Timeout)"); 710a88b5ba8SSam Ravnborg } 711a88b5ba8SSam Ravnborg if (afsr & SCHIZO_PCIAFSR_SUNUS) { 712a88b5ba8SSam Ravnborg reported++; 713a88b5ba8SSam Ravnborg printk("(Bus Unusable)"); 714a88b5ba8SSam Ravnborg } 715a88b5ba8SSam Ravnborg if (!reported) 716a88b5ba8SSam Ravnborg printk("(none)"); 717a88b5ba8SSam Ravnborg printk("]\n"); 718a88b5ba8SSam Ravnborg 719a88b5ba8SSam Ravnborg /* For the error types shown, scan PBM's PCI bus for devices 720a88b5ba8SSam Ravnborg * which have logged that error type. 721a88b5ba8SSam Ravnborg */ 722a88b5ba8SSam Ravnborg 723a88b5ba8SSam Ravnborg /* If we see a Target Abort, this could be the result of an 724a88b5ba8SSam Ravnborg * IOMMU translation error of some sort. It is extremely 725a88b5ba8SSam Ravnborg * useful to log this information as usually it indicates 726a88b5ba8SSam Ravnborg * a bug in the IOMMU support code or a PCI device driver. 727a88b5ba8SSam Ravnborg */ 728a88b5ba8SSam Ravnborg if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) { 729a88b5ba8SSam Ravnborg schizo_check_iommu_error(pbm, PCI_ERR); 730a88b5ba8SSam Ravnborg pci_scan_for_target_abort(pbm, pbm->pci_bus); 731a88b5ba8SSam Ravnborg } 732a88b5ba8SSam Ravnborg if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA)) 733a88b5ba8SSam Ravnborg pci_scan_for_master_abort(pbm, pbm->pci_bus); 734a88b5ba8SSam Ravnborg 735a88b5ba8SSam Ravnborg /* For excessive retries, PSYCHO/PBM will abort the device 736a88b5ba8SSam Ravnborg * and there is no way to specifically check for excessive 737a88b5ba8SSam Ravnborg * retries in the config space status registers. So what 738a88b5ba8SSam Ravnborg * we hope is that we'll catch it via the master/target 739a88b5ba8SSam Ravnborg * abort events. 740a88b5ba8SSam Ravnborg */ 741a88b5ba8SSam Ravnborg 742a88b5ba8SSam Ravnborg if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR)) 743a88b5ba8SSam Ravnborg pci_scan_for_parity_error(pbm, pbm->pci_bus); 744a88b5ba8SSam Ravnborg 745a88b5ba8SSam Ravnborg return IRQ_HANDLED; 746a88b5ba8SSam Ravnborg } 747a88b5ba8SSam Ravnborg 748a88b5ba8SSam Ravnborg #define SCHIZO_SAFARI_ERRLOG 0x10018UL 749a88b5ba8SSam Ravnborg 750a88b5ba8SSam Ravnborg #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL 751a88b5ba8SSam Ravnborg 752a88b5ba8SSam Ravnborg #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */ 753a88b5ba8SSam Ravnborg #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */ 754a88b5ba8SSam Ravnborg #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */ 755a88b5ba8SSam Ravnborg #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */ 756a88b5ba8SSam Ravnborg #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */ 757a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */ 758a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */ 759a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */ 760a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */ 761a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */ 762a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */ 763a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */ 764a88b5ba8SSam Ravnborg #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */ 765a88b5ba8SSam Ravnborg #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */ 766a88b5ba8SSam Ravnborg #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */ 767a88b5ba8SSam Ravnborg #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */ 768a88b5ba8SSam Ravnborg #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */ 769a88b5ba8SSam Ravnborg #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */ 770a88b5ba8SSam Ravnborg #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */ 771a88b5ba8SSam Ravnborg #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */ 772a88b5ba8SSam Ravnborg #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */ 773a88b5ba8SSam Ravnborg #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */ 774a88b5ba8SSam Ravnborg #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */ 775a88b5ba8SSam Ravnborg #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */ 776a88b5ba8SSam Ravnborg #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */ 777a88b5ba8SSam Ravnborg #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */ 778a88b5ba8SSam Ravnborg #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */ 779a88b5ba8SSam Ravnborg #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */ 780a88b5ba8SSam Ravnborg #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */ 781a88b5ba8SSam Ravnborg #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */ 782a88b5ba8SSam Ravnborg #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */ 783a88b5ba8SSam Ravnborg 784a88b5ba8SSam Ravnborg /* We only expect UNMAP errors here. The rest of the Safari errors 785a88b5ba8SSam Ravnborg * are marked fatal and thus cause a system reset. 786a88b5ba8SSam Ravnborg */ 787a88b5ba8SSam Ravnborg static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id) 788a88b5ba8SSam Ravnborg { 789a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm = dev_id; 790a88b5ba8SSam Ravnborg u64 errlog; 791a88b5ba8SSam Ravnborg 792a88b5ba8SSam Ravnborg errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 793a88b5ba8SSam Ravnborg upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT), 794a88b5ba8SSam Ravnborg pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 795a88b5ba8SSam Ravnborg 796a88b5ba8SSam Ravnborg if (!(errlog & BUS_ERROR_UNMAP)) { 79790181136SSam Ravnborg printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n", 798a88b5ba8SSam Ravnborg pbm->name, errlog); 799a88b5ba8SSam Ravnborg 800a88b5ba8SSam Ravnborg return IRQ_HANDLED; 801a88b5ba8SSam Ravnborg } 802a88b5ba8SSam Ravnborg 803a88b5ba8SSam Ravnborg printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n", 804a88b5ba8SSam Ravnborg pbm->name); 805a88b5ba8SSam Ravnborg schizo_check_iommu_error(pbm, SAFARI_ERR); 806a88b5ba8SSam Ravnborg 807a88b5ba8SSam Ravnborg return IRQ_HANDLED; 808a88b5ba8SSam Ravnborg } 809a88b5ba8SSam Ravnborg 810a88b5ba8SSam Ravnborg /* Nearly identical to PSYCHO equivalents... */ 811a88b5ba8SSam Ravnborg #define SCHIZO_ECC_CTRL 0x10020UL 812a88b5ba8SSam Ravnborg #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 813a88b5ba8SSam Ravnborg #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ 814a88b5ba8SSam Ravnborg #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ 815a88b5ba8SSam Ravnborg 816a88b5ba8SSam Ravnborg #define SCHIZO_SAFARI_ERRCTRL 0x10008UL 817a88b5ba8SSam Ravnborg #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL 818a88b5ba8SSam Ravnborg #define SCHIZO_SAFARI_IRQCTRL 0x10010UL 819a88b5ba8SSam Ravnborg #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL 820a88b5ba8SSam Ravnborg 821a88b5ba8SSam Ravnborg static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino) 822a88b5ba8SSam Ravnborg { 823a88b5ba8SSam Ravnborg ino &= IMAP_INO; 824a88b5ba8SSam Ravnborg 825a88b5ba8SSam Ravnborg if (pbm->ino_bitmap & (1UL << ino)) 826a88b5ba8SSam Ravnborg return 1; 827a88b5ba8SSam Ravnborg 828a88b5ba8SSam Ravnborg return 0; 829a88b5ba8SSam Ravnborg } 830a88b5ba8SSam Ravnborg 831a88b5ba8SSam Ravnborg /* How the Tomatillo IRQs are routed around is pure guesswork here. 832a88b5ba8SSam Ravnborg * 833a88b5ba8SSam Ravnborg * All the Tomatillo devices I see in prtconf dumps seem to have only 834a88b5ba8SSam Ravnborg * a single PCI bus unit attached to it. It would seem they are separate 835a88b5ba8SSam Ravnborg * devices because their PortID (ie. JBUS ID) values are all different 836a88b5ba8SSam Ravnborg * and thus the registers are mapped to totally different locations. 837a88b5ba8SSam Ravnborg * 838a88b5ba8SSam Ravnborg * However, two Tomatillo's look "similar" in that the only difference 839a88b5ba8SSam Ravnborg * in their PortID is the lowest bit. 840a88b5ba8SSam Ravnborg * 841a88b5ba8SSam Ravnborg * So if we were to ignore this lower bit, it certainly looks like two 842a88b5ba8SSam Ravnborg * PCI bus units of the same Tomatillo. I still have not really 843a88b5ba8SSam Ravnborg * figured this out... 844a88b5ba8SSam Ravnborg */ 845a88b5ba8SSam Ravnborg static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm) 846a88b5ba8SSam Ravnborg { 847cd4cd730SGrant Likely struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 848a88b5ba8SSam Ravnborg u64 tmp, err_mask, err_no_mask; 849a88b5ba8SSam Ravnborg int err; 850a88b5ba8SSam Ravnborg 851a88b5ba8SSam Ravnborg /* Tomatillo IRQ property layout is: 852a88b5ba8SSam Ravnborg * 0: PCIERR 853a88b5ba8SSam Ravnborg * 1: UE ERR 854a88b5ba8SSam Ravnborg * 2: CE ERR 855a88b5ba8SSam Ravnborg * 3: SERR 856a88b5ba8SSam Ravnborg * 4: POWER FAIL? 857a88b5ba8SSam Ravnborg */ 858a88b5ba8SSam Ravnborg 859a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 8601636f8acSGrant Likely err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 861a88b5ba8SSam Ravnborg "TOMATILLO_UE", pbm); 862a88b5ba8SSam Ravnborg if (err) 863a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register UE, " 864a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err); 865a88b5ba8SSam Ravnborg } 866a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 8671636f8acSGrant Likely err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 868a88b5ba8SSam Ravnborg "TOMATILLO_CE", pbm); 869a88b5ba8SSam Ravnborg if (err) 870a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register CE, " 871a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err); 872a88b5ba8SSam Ravnborg } 873a88b5ba8SSam Ravnborg err = 0; 874a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 8751636f8acSGrant Likely err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 876a88b5ba8SSam Ravnborg "TOMATILLO_PCIERR", pbm); 877a88b5ba8SSam Ravnborg } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 8781636f8acSGrant Likely err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 879a88b5ba8SSam Ravnborg "TOMATILLO_PCIERR", pbm); 880a88b5ba8SSam Ravnborg } 881a88b5ba8SSam Ravnborg if (err) 882a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register PCIERR, " 883a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err); 884a88b5ba8SSam Ravnborg 885a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 8861636f8acSGrant Likely err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 887a88b5ba8SSam Ravnborg "TOMATILLO_SERR", pbm); 888a88b5ba8SSam Ravnborg if (err) 889a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register SERR, " 890a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err); 891a88b5ba8SSam Ravnborg } 892a88b5ba8SSam Ravnborg 893a88b5ba8SSam Ravnborg /* Enable UE and CE interrupts for controller. */ 894a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_ECCCTRL_EE | 895a88b5ba8SSam Ravnborg SCHIZO_ECCCTRL_UE | 896a88b5ba8SSam Ravnborg SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 897a88b5ba8SSam Ravnborg 898a88b5ba8SSam Ravnborg /* Enable PCI Error interrupts and clear error 899a88b5ba8SSam Ravnborg * bits. 900a88b5ba8SSam Ravnborg */ 901a88b5ba8SSam Ravnborg err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 902a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_TTO_ERR | 903a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RTRY_ERR | 904a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SERR | 905a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_EEN); 906a88b5ba8SSam Ravnborg 907a88b5ba8SSam Ravnborg err_no_mask = SCHIZO_PCICTRL_DTO_ERR; 908a88b5ba8SSam Ravnborg 909a88b5ba8SSam Ravnborg tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 910a88b5ba8SSam Ravnborg tmp |= err_mask; 911a88b5ba8SSam Ravnborg tmp &= ~err_no_mask; 912a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 913a88b5ba8SSam Ravnborg 914a88b5ba8SSam Ravnborg err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 915a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 916a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PTTO | 917a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 918a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 919a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_STTO); 920a88b5ba8SSam Ravnborg 921a88b5ba8SSam Ravnborg upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR); 922a88b5ba8SSam Ravnborg 923a88b5ba8SSam Ravnborg err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | 924a88b5ba8SSam Ravnborg BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | 925a88b5ba8SSam Ravnborg BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA | 926a88b5ba8SSam Ravnborg BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO | 927a88b5ba8SSam Ravnborg BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR | 928a88b5ba8SSam Ravnborg BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B | 929a88b5ba8SSam Ravnborg BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR | 930a88b5ba8SSam Ravnborg BUS_ERROR_APERR | BUS_ERROR_UNMAP | 931a88b5ba8SSam Ravnborg BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); 932a88b5ba8SSam Ravnborg 933a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 934a88b5ba8SSam Ravnborg pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 935a88b5ba8SSam Ravnborg 936a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)), 937a88b5ba8SSam Ravnborg pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL); 938a88b5ba8SSam Ravnborg } 939a88b5ba8SSam Ravnborg 940a88b5ba8SSam Ravnborg static void schizo_register_error_handlers(struct pci_pbm_info *pbm) 941a88b5ba8SSam Ravnborg { 942cd4cd730SGrant Likely struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 943a88b5ba8SSam Ravnborg u64 tmp, err_mask, err_no_mask; 944a88b5ba8SSam Ravnborg int err; 945a88b5ba8SSam Ravnborg 946a88b5ba8SSam Ravnborg /* Schizo IRQ property layout is: 947a88b5ba8SSam Ravnborg * 0: PCIERR 948a88b5ba8SSam Ravnborg * 1: UE ERR 949a88b5ba8SSam Ravnborg * 2: CE ERR 950a88b5ba8SSam Ravnborg * 3: SERR 951a88b5ba8SSam Ravnborg * 4: POWER FAIL? 952a88b5ba8SSam Ravnborg */ 953a88b5ba8SSam Ravnborg 954a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 9551636f8acSGrant Likely err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 956a88b5ba8SSam Ravnborg "SCHIZO_UE", pbm); 957a88b5ba8SSam Ravnborg if (err) 958a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register UE, " 959a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err); 960a88b5ba8SSam Ravnborg } 961a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 9621636f8acSGrant Likely err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 963a88b5ba8SSam Ravnborg "SCHIZO_CE", pbm); 964a88b5ba8SSam Ravnborg if (err) 965a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register CE, " 966a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err); 967a88b5ba8SSam Ravnborg } 968a88b5ba8SSam Ravnborg err = 0; 969a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 9701636f8acSGrant Likely err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 971a88b5ba8SSam Ravnborg "SCHIZO_PCIERR", pbm); 972a88b5ba8SSam Ravnborg } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 9731636f8acSGrant Likely err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 974a88b5ba8SSam Ravnborg "SCHIZO_PCIERR", pbm); 975a88b5ba8SSam Ravnborg } 976a88b5ba8SSam Ravnborg if (err) 977a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register PCIERR, " 978a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err); 979a88b5ba8SSam Ravnborg 980a88b5ba8SSam Ravnborg if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 9811636f8acSGrant Likely err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 982a88b5ba8SSam Ravnborg "SCHIZO_SERR", pbm); 983a88b5ba8SSam Ravnborg if (err) 984a88b5ba8SSam Ravnborg printk(KERN_WARNING "%s: Could not register SERR, " 985a88b5ba8SSam Ravnborg "err=%d\n", pbm->name, err); 986a88b5ba8SSam Ravnborg } 987a88b5ba8SSam Ravnborg 988a88b5ba8SSam Ravnborg /* Enable UE and CE interrupts for controller. */ 989a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_ECCCTRL_EE | 990a88b5ba8SSam Ravnborg SCHIZO_ECCCTRL_UE | 991a88b5ba8SSam Ravnborg SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 992a88b5ba8SSam Ravnborg 993a88b5ba8SSam Ravnborg err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 994a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_ESLCK | 995a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_TTO_ERR | 996a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RTRY_ERR | 997a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SBH_ERR | 998a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SERR | 999a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_EEN); 1000a88b5ba8SSam Ravnborg 1001a88b5ba8SSam Ravnborg err_no_mask = (SCHIZO_PCICTRL_DTO_ERR | 1002a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_SBH_INT); 1003a88b5ba8SSam Ravnborg 1004a88b5ba8SSam Ravnborg /* Enable PCI Error interrupts and clear error 1005a88b5ba8SSam Ravnborg * bits for each PBM. 1006a88b5ba8SSam Ravnborg */ 1007a88b5ba8SSam Ravnborg tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1008a88b5ba8SSam Ravnborg tmp |= err_mask; 1009a88b5ba8SSam Ravnborg tmp &= ~err_no_mask; 1010a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1011a88b5ba8SSam Ravnborg 1012a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 1013a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 1014a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 1015a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 1016a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 1017a88b5ba8SSam Ravnborg SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS), 1018a88b5ba8SSam Ravnborg pbm->pbm_regs + SCHIZO_PCI_AFSR); 1019a88b5ba8SSam Ravnborg 1020a88b5ba8SSam Ravnborg /* Make all Safari error conditions fatal except unmapped 1021a88b5ba8SSam Ravnborg * errors which we make generate interrupts. 1022a88b5ba8SSam Ravnborg */ 1023a88b5ba8SSam Ravnborg err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS | 1024a88b5ba8SSam Ravnborg BUS_ERROR_BADMA | BUS_ERROR_BADMB | 1025a88b5ba8SSam Ravnborg BUS_ERROR_BADMC | 1026a88b5ba8SSam Ravnborg BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1027a88b5ba8SSam Ravnborg BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB | 1028a88b5ba8SSam Ravnborg BUS_ERROR_CIQTO | 1029a88b5ba8SSam Ravnborg BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO | 1030a88b5ba8SSam Ravnborg BUS_ERROR_UFPQTO | BUS_ERROR_APERR | 1031a88b5ba8SSam Ravnborg BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT | 1032a88b5ba8SSam Ravnborg BUS_ERROR_ILL); 1033a88b5ba8SSam Ravnborg #if 1 1034a88b5ba8SSam Ravnborg /* XXX Something wrong with some Excalibur systems 1035a88b5ba8SSam Ravnborg * XXX Sun is shipping. The behavior on a 2-cpu 1036a88b5ba8SSam Ravnborg * XXX machine is that both CPU1 parity error bits 1037a88b5ba8SSam Ravnborg * XXX are set and are immediately set again when 1038a88b5ba8SSam Ravnborg * XXX their error status bits are cleared. Just 1039a88b5ba8SSam Ravnborg * XXX ignore them for now. -DaveM 1040a88b5ba8SSam Ravnborg */ 1041a88b5ba8SSam Ravnborg err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1042a88b5ba8SSam Ravnborg BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); 1043a88b5ba8SSam Ravnborg #endif 1044a88b5ba8SSam Ravnborg 1045a88b5ba8SSam Ravnborg upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 1046a88b5ba8SSam Ravnborg pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 1047a88b5ba8SSam Ravnborg } 1048a88b5ba8SSam Ravnborg 1049a88b5ba8SSam Ravnborg static void pbm_config_busmastering(struct pci_pbm_info *pbm) 1050a88b5ba8SSam Ravnborg { 1051a88b5ba8SSam Ravnborg u8 *addr; 1052a88b5ba8SSam Ravnborg 1053a88b5ba8SSam Ravnborg /* Set cache-line size to 64 bytes, this is actually 1054a88b5ba8SSam Ravnborg * a nop but I do it for completeness. 1055a88b5ba8SSam Ravnborg */ 1056a88b5ba8SSam Ravnborg addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1057a88b5ba8SSam Ravnborg 0, PCI_CACHE_LINE_SIZE); 1058a88b5ba8SSam Ravnborg pci_config_write8(addr, 64 / sizeof(u32)); 1059a88b5ba8SSam Ravnborg 1060a88b5ba8SSam Ravnborg /* Set PBM latency timer to 64 PCI clocks. */ 1061a88b5ba8SSam Ravnborg addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1062a88b5ba8SSam Ravnborg 0, PCI_LATENCY_TIMER); 1063a88b5ba8SSam Ravnborg pci_config_write8(addr, 64); 1064a88b5ba8SSam Ravnborg } 1065a88b5ba8SSam Ravnborg 1066a88b5ba8SSam Ravnborg static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm, 1067a88b5ba8SSam Ravnborg struct device *parent) 1068a88b5ba8SSam Ravnborg { 1069a88b5ba8SSam Ravnborg pbm_config_busmastering(pbm); 1070a88b5ba8SSam Ravnborg pbm->is_66mhz_capable = 107161c7a080SGrant Likely (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL) 1072a88b5ba8SSam Ravnborg != NULL); 1073a88b5ba8SSam Ravnborg 1074a88b5ba8SSam Ravnborg pbm->pci_bus = pci_scan_one_pbm(pbm, parent); 1075a88b5ba8SSam Ravnborg 1076a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1077a88b5ba8SSam Ravnborg tomatillo_register_error_handlers(pbm); 1078a88b5ba8SSam Ravnborg else 1079a88b5ba8SSam Ravnborg schizo_register_error_handlers(pbm); 1080a88b5ba8SSam Ravnborg } 1081a88b5ba8SSam Ravnborg 1082a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CONTROL (0x02800UL) 1083a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_FLUSH (0x02808UL) 1084a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_FSYNC (0x02810UL) 1085a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL) 1086a88b5ba8SSam Ravnborg #define SCHIZO_STRBUF_CTXMATCH (0x10000UL) 1087a88b5ba8SSam Ravnborg 1088a88b5ba8SSam Ravnborg static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm) 1089a88b5ba8SSam Ravnborg { 1090a88b5ba8SSam Ravnborg unsigned long base = pbm->pbm_regs; 1091a88b5ba8SSam Ravnborg u64 control; 1092a88b5ba8SSam Ravnborg 1093a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1094a88b5ba8SSam Ravnborg /* TOMATILLO lacks streaming cache. */ 1095a88b5ba8SSam Ravnborg return; 1096a88b5ba8SSam Ravnborg } 1097a88b5ba8SSam Ravnborg 1098a88b5ba8SSam Ravnborg /* SCHIZO has context flushing. */ 1099a88b5ba8SSam Ravnborg pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; 1100a88b5ba8SSam Ravnborg pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; 1101a88b5ba8SSam Ravnborg pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; 1102a88b5ba8SSam Ravnborg pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; 1103a88b5ba8SSam Ravnborg pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; 1104a88b5ba8SSam Ravnborg 1105a88b5ba8SSam Ravnborg pbm->stc.strbuf_flushflag = (volatile unsigned long *) 1106a88b5ba8SSam Ravnborg ((((unsigned long)&pbm->stc.__flushflag_buf[0]) 1107a88b5ba8SSam Ravnborg + 63UL) 1108a88b5ba8SSam Ravnborg & ~63UL); 1109a88b5ba8SSam Ravnborg pbm->stc.strbuf_flushflag_pa = (unsigned long) 1110a88b5ba8SSam Ravnborg __pa(pbm->stc.strbuf_flushflag); 1111a88b5ba8SSam Ravnborg 1112a88b5ba8SSam Ravnborg /* Turn off LRU locking and diag mode, enable the 1113a88b5ba8SSam Ravnborg * streaming buffer and leave the rerun-disable 1114a88b5ba8SSam Ravnborg * setting however OBP set it. 1115a88b5ba8SSam Ravnborg */ 1116a88b5ba8SSam Ravnborg control = upa_readq(pbm->stc.strbuf_control); 1117a88b5ba8SSam Ravnborg control &= ~(SCHIZO_STRBUF_CTRL_LPTR | 1118a88b5ba8SSam Ravnborg SCHIZO_STRBUF_CTRL_LENAB | 1119a88b5ba8SSam Ravnborg SCHIZO_STRBUF_CTRL_DENAB); 1120a88b5ba8SSam Ravnborg control |= SCHIZO_STRBUF_CTRL_ENAB; 1121a88b5ba8SSam Ravnborg upa_writeq(control, pbm->stc.strbuf_control); 1122a88b5ba8SSam Ravnborg 1123a88b5ba8SSam Ravnborg pbm->stc.strbuf_enabled = 1; 1124a88b5ba8SSam Ravnborg } 1125a88b5ba8SSam Ravnborg 1126a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CONTROL (0x00200UL) 1127a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_TSBBASE (0x00208UL) 1128a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_FLUSH (0x00210UL) 1129a88b5ba8SSam Ravnborg #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL) 1130a88b5ba8SSam Ravnborg 1131a88b5ba8SSam Ravnborg static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm) 1132a88b5ba8SSam Ravnborg { 1133a88b5ba8SSam Ravnborg static const u32 vdma_default[] = { 0xc0000000, 0x40000000 }; 1134a88b5ba8SSam Ravnborg unsigned long i, tagbase, database; 1135a88b5ba8SSam Ravnborg struct iommu *iommu = pbm->iommu; 1136a88b5ba8SSam Ravnborg int tsbsize, err; 1137a88b5ba8SSam Ravnborg const u32 *vdma; 1138a88b5ba8SSam Ravnborg u32 dma_mask; 1139a88b5ba8SSam Ravnborg u64 control; 1140a88b5ba8SSam Ravnborg 114161c7a080SGrant Likely vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); 1142a88b5ba8SSam Ravnborg if (!vdma) 1143a88b5ba8SSam Ravnborg vdma = vdma_default; 1144a88b5ba8SSam Ravnborg 1145a88b5ba8SSam Ravnborg dma_mask = vdma[0]; 1146a88b5ba8SSam Ravnborg switch (vdma[1]) { 1147a88b5ba8SSam Ravnborg case 0x20000000: 1148a88b5ba8SSam Ravnborg dma_mask |= 0x1fffffff; 1149a88b5ba8SSam Ravnborg tsbsize = 64; 1150a88b5ba8SSam Ravnborg break; 1151a88b5ba8SSam Ravnborg 1152a88b5ba8SSam Ravnborg case 0x40000000: 1153a88b5ba8SSam Ravnborg dma_mask |= 0x3fffffff; 1154a88b5ba8SSam Ravnborg tsbsize = 128; 1155a88b5ba8SSam Ravnborg break; 1156a88b5ba8SSam Ravnborg 1157a88b5ba8SSam Ravnborg case 0x80000000: 1158a88b5ba8SSam Ravnborg dma_mask |= 0x7fffffff; 1159a88b5ba8SSam Ravnborg tsbsize = 128; 1160a88b5ba8SSam Ravnborg break; 1161a88b5ba8SSam Ravnborg 1162a88b5ba8SSam Ravnborg default: 1163a88b5ba8SSam Ravnborg printk(KERN_ERR PFX "Strange virtual-dma size.\n"); 1164a88b5ba8SSam Ravnborg return -EINVAL; 1165a88b5ba8SSam Ravnborg } 1166a88b5ba8SSam Ravnborg 1167a88b5ba8SSam Ravnborg /* Register addresses, SCHIZO has iommu ctx flushing. */ 1168a88b5ba8SSam Ravnborg iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; 1169a88b5ba8SSam Ravnborg iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; 1170a88b5ba8SSam Ravnborg iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH; 1171a88b5ba8SSam Ravnborg iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL); 1172a88b5ba8SSam Ravnborg iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH; 1173a88b5ba8SSam Ravnborg 1174a88b5ba8SSam Ravnborg /* We use the main control/status register of SCHIZO as the write 1175a88b5ba8SSam Ravnborg * completion register. 1176a88b5ba8SSam Ravnborg */ 1177a88b5ba8SSam Ravnborg iommu->write_complete_reg = pbm->controller_regs + 0x10000UL; 1178a88b5ba8SSam Ravnborg 1179a88b5ba8SSam Ravnborg /* 1180a88b5ba8SSam Ravnborg * Invalidate TLB Entries. 1181a88b5ba8SSam Ravnborg */ 1182a88b5ba8SSam Ravnborg control = upa_readq(iommu->iommu_control); 1183a88b5ba8SSam Ravnborg control |= SCHIZO_IOMMU_CTRL_DENAB; 1184a88b5ba8SSam Ravnborg upa_writeq(control, iommu->iommu_control); 1185a88b5ba8SSam Ravnborg 1186a88b5ba8SSam Ravnborg tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; 1187a88b5ba8SSam Ravnborg 1188a88b5ba8SSam Ravnborg for (i = 0; i < 16; i++) { 1189a88b5ba8SSam Ravnborg upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL)); 1190a88b5ba8SSam Ravnborg upa_writeq(0, pbm->pbm_regs + database + (i * 8UL)); 1191a88b5ba8SSam Ravnborg } 1192a88b5ba8SSam Ravnborg 1193a88b5ba8SSam Ravnborg /* Leave diag mode enabled for full-flushing done 1194a88b5ba8SSam Ravnborg * in pci_iommu.c 1195a88b5ba8SSam Ravnborg */ 1196a88b5ba8SSam Ravnborg err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, 1197a88b5ba8SSam Ravnborg pbm->numa_node); 1198a88b5ba8SSam Ravnborg if (err) { 1199a88b5ba8SSam Ravnborg printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err); 1200a88b5ba8SSam Ravnborg return err; 1201a88b5ba8SSam Ravnborg } 1202a88b5ba8SSam Ravnborg 1203a88b5ba8SSam Ravnborg upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); 1204a88b5ba8SSam Ravnborg 1205a88b5ba8SSam Ravnborg control = upa_readq(iommu->iommu_control); 1206a88b5ba8SSam Ravnborg control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); 1207a88b5ba8SSam Ravnborg switch (tsbsize) { 1208a88b5ba8SSam Ravnborg case 64: 1209a88b5ba8SSam Ravnborg control |= SCHIZO_IOMMU_TSBSZ_64K; 1210a88b5ba8SSam Ravnborg break; 1211a88b5ba8SSam Ravnborg case 128: 1212a88b5ba8SSam Ravnborg control |= SCHIZO_IOMMU_TSBSZ_128K; 1213a88b5ba8SSam Ravnborg break; 1214a88b5ba8SSam Ravnborg } 1215a88b5ba8SSam Ravnborg 1216a88b5ba8SSam Ravnborg control |= SCHIZO_IOMMU_CTRL_ENAB; 1217a88b5ba8SSam Ravnborg upa_writeq(control, iommu->iommu_control); 1218a88b5ba8SSam Ravnborg 1219a88b5ba8SSam Ravnborg return 0; 1220a88b5ba8SSam Ravnborg } 1221a88b5ba8SSam Ravnborg 1222a88b5ba8SSam Ravnborg #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL) 1223a88b5ba8SSam Ravnborg #define SCHIZO_IRQ_RETRY_INF 0xffUL 1224a88b5ba8SSam Ravnborg 1225a88b5ba8SSam Ravnborg #define SCHIZO_PCI_DIAG (0x2020UL) 1226a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */ 1227a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */ 1228a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */ 1229a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */ 1230a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */ 1231a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */ 1232a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */ 1233a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */ 1234a88b5ba8SSam Ravnborg #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */ 1235a88b5ba8SSam Ravnborg 1236a88b5ba8SSam Ravnborg #define TOMATILLO_PCI_IOC_CSR (0x2248UL) 1237a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL 1238a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL 1239a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL 1240a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL 1241a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL 1242a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL 1243a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL 1244a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL 1245a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL 1246a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL 1247a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL 1248a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL 1249a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL 1250a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL 1251a88b5ba8SSam Ravnborg #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL 1252a88b5ba8SSam Ravnborg 1253a88b5ba8SSam Ravnborg #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL) 1254a88b5ba8SSam Ravnborg #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL) 1255a88b5ba8SSam Ravnborg 1256a88b5ba8SSam Ravnborg static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) 1257a88b5ba8SSam Ravnborg { 1258a88b5ba8SSam Ravnborg u64 tmp; 1259a88b5ba8SSam Ravnborg 1260a88b5ba8SSam Ravnborg upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY); 1261a88b5ba8SSam Ravnborg 1262a88b5ba8SSam Ravnborg tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1263a88b5ba8SSam Ravnborg 1264a88b5ba8SSam Ravnborg /* Enable arbiter for all PCI slots. */ 1265a88b5ba8SSam Ravnborg tmp |= 0xff; 1266a88b5ba8SSam Ravnborg 1267a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1268a88b5ba8SSam Ravnborg pbm->chip_version >= 0x2) 1269a88b5ba8SSam Ravnborg tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; 1270a88b5ba8SSam Ravnborg 127161c7a080SGrant Likely if (!of_find_property(pbm->op->dev.of_node, "no-bus-parking", NULL)) 1272a88b5ba8SSam Ravnborg tmp |= SCHIZO_PCICTRL_PARK; 1273a88b5ba8SSam Ravnborg else 1274a88b5ba8SSam Ravnborg tmp &= ~SCHIZO_PCICTRL_PARK; 1275a88b5ba8SSam Ravnborg 1276a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1277a88b5ba8SSam Ravnborg pbm->chip_version <= 0x1) 1278a88b5ba8SSam Ravnborg tmp |= SCHIZO_PCICTRL_DTO_INT; 1279a88b5ba8SSam Ravnborg else 1280a88b5ba8SSam Ravnborg tmp &= ~SCHIZO_PCICTRL_DTO_INT; 1281a88b5ba8SSam Ravnborg 1282a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1283a88b5ba8SSam Ravnborg tmp |= (SCHIZO_PCICTRL_MRM_PREF | 1284a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RDO_PREF | 1285a88b5ba8SSam Ravnborg SCHIZO_PCICTRL_RDL_PREF); 1286a88b5ba8SSam Ravnborg 1287a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1288a88b5ba8SSam Ravnborg 1289a88b5ba8SSam Ravnborg tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG); 1290a88b5ba8SSam Ravnborg tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | 1291a88b5ba8SSam Ravnborg SCHIZO_PCIDIAG_D_RETRY | 1292a88b5ba8SSam Ravnborg SCHIZO_PCIDIAG_D_INTSYNC); 1293a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG); 1294a88b5ba8SSam Ravnborg 1295a88b5ba8SSam Ravnborg if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1296a88b5ba8SSam Ravnborg /* Clear prefetch lengths to workaround a bug in 1297a88b5ba8SSam Ravnborg * Jalapeno... 1298a88b5ba8SSam Ravnborg */ 1299a88b5ba8SSam Ravnborg tmp = (TOMATILLO_IOC_PART_WPENAB | 1300a88b5ba8SSam Ravnborg (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) | 1301a88b5ba8SSam Ravnborg TOMATILLO_IOC_RDMULT_CPENAB | 1302a88b5ba8SSam Ravnborg TOMATILLO_IOC_RDONE_CPENAB | 1303a88b5ba8SSam Ravnborg TOMATILLO_IOC_RDLINE_CPENAB); 1304a88b5ba8SSam Ravnborg 1305a88b5ba8SSam Ravnborg upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR); 1306a88b5ba8SSam Ravnborg } 1307a88b5ba8SSam Ravnborg } 1308a88b5ba8SSam Ravnborg 1309a88b5ba8SSam Ravnborg static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm, 1310cd4cd730SGrant Likely struct platform_device *op, u32 portid, 1311a88b5ba8SSam Ravnborg int chip_type) 1312a88b5ba8SSam Ravnborg { 1313a88b5ba8SSam Ravnborg const struct linux_prom64_registers *regs; 131461c7a080SGrant Likely struct device_node *dp = op->dev.of_node; 1315a88b5ba8SSam Ravnborg const char *chipset_name; 1316c6fee081SDavid S. Miller int err; 1317a88b5ba8SSam Ravnborg 1318a88b5ba8SSam Ravnborg switch (chip_type) { 1319a88b5ba8SSam Ravnborg case PBM_CHIP_TYPE_TOMATILLO: 1320a88b5ba8SSam Ravnborg chipset_name = "TOMATILLO"; 1321a88b5ba8SSam Ravnborg break; 1322a88b5ba8SSam Ravnborg 1323a88b5ba8SSam Ravnborg case PBM_CHIP_TYPE_SCHIZO_PLUS: 1324a88b5ba8SSam Ravnborg chipset_name = "SCHIZO+"; 1325a88b5ba8SSam Ravnborg break; 1326a88b5ba8SSam Ravnborg 1327a88b5ba8SSam Ravnborg case PBM_CHIP_TYPE_SCHIZO: 1328a88b5ba8SSam Ravnborg default: 1329a88b5ba8SSam Ravnborg chipset_name = "SCHIZO"; 1330a88b5ba8SSam Ravnborg break; 1331a88b5ba8SSam Ravnborg }; 1332a88b5ba8SSam Ravnborg 1333a88b5ba8SSam Ravnborg /* For SCHIZO, three OBP regs: 1334a88b5ba8SSam Ravnborg * 1) PBM controller regs 1335a88b5ba8SSam Ravnborg * 2) Schizo front-end controller regs (same for both PBMs) 1336a88b5ba8SSam Ravnborg * 3) PBM PCI config space 1337a88b5ba8SSam Ravnborg * 1338a88b5ba8SSam Ravnborg * For TOMATILLO, four OBP regs: 1339a88b5ba8SSam Ravnborg * 1) PBM controller regs 1340a88b5ba8SSam Ravnborg * 2) Tomatillo front-end controller regs 1341a88b5ba8SSam Ravnborg * 3) PBM PCI config space 1342a88b5ba8SSam Ravnborg * 4) Ichip regs 1343a88b5ba8SSam Ravnborg */ 1344a88b5ba8SSam Ravnborg regs = of_get_property(dp, "reg", NULL); 1345a88b5ba8SSam Ravnborg 1346a88b5ba8SSam Ravnborg pbm->next = pci_pbm_root; 1347a88b5ba8SSam Ravnborg pci_pbm_root = pbm; 1348a88b5ba8SSam Ravnborg 1349a88b5ba8SSam Ravnborg pbm->numa_node = -1; 1350a88b5ba8SSam Ravnborg 1351a88b5ba8SSam Ravnborg pbm->pci_ops = &sun4u_pci_ops; 1352a88b5ba8SSam Ravnborg pbm->config_space_reg_bits = 8; 1353a88b5ba8SSam Ravnborg 1354a88b5ba8SSam Ravnborg pbm->index = pci_num_pbms++; 1355a88b5ba8SSam Ravnborg 1356a88b5ba8SSam Ravnborg pbm->portid = portid; 1357a88b5ba8SSam Ravnborg pbm->op = op; 1358a88b5ba8SSam Ravnborg 1359a88b5ba8SSam Ravnborg pbm->chip_type = chip_type; 1360a88b5ba8SSam Ravnborg pbm->chip_version = of_getintprop_default(dp, "version#", 0); 1361a88b5ba8SSam Ravnborg pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0); 1362a88b5ba8SSam Ravnborg 1363a88b5ba8SSam Ravnborg pbm->pbm_regs = regs[0].phys_addr; 1364a88b5ba8SSam Ravnborg pbm->controller_regs = regs[1].phys_addr - 0x10000UL; 1365a88b5ba8SSam Ravnborg 1366a88b5ba8SSam Ravnborg if (chip_type == PBM_CHIP_TYPE_TOMATILLO) 1367a88b5ba8SSam Ravnborg pbm->sync_reg = regs[3].phys_addr + 0x1a18UL; 1368a88b5ba8SSam Ravnborg 1369a88b5ba8SSam Ravnborg pbm->name = dp->full_name; 1370a88b5ba8SSam Ravnborg 1371a88b5ba8SSam Ravnborg printk("%s: %s PCI Bus Module ver[%x:%x]\n", 1372a88b5ba8SSam Ravnborg pbm->name, chipset_name, 1373a88b5ba8SSam Ravnborg pbm->chip_version, pbm->chip_revision); 1374a88b5ba8SSam Ravnborg 1375a88b5ba8SSam Ravnborg schizo_pbm_hw_init(pbm); 1376a88b5ba8SSam Ravnborg 1377a88b5ba8SSam Ravnborg pci_determine_mem_io_space(pbm); 1378a88b5ba8SSam Ravnborg 1379a88b5ba8SSam Ravnborg pci_get_pbm_props(pbm); 1380a88b5ba8SSam Ravnborg 1381a88b5ba8SSam Ravnborg err = schizo_pbm_iommu_init(pbm); 1382a88b5ba8SSam Ravnborg if (err) 1383a88b5ba8SSam Ravnborg return err; 1384a88b5ba8SSam Ravnborg 1385a88b5ba8SSam Ravnborg schizo_pbm_strbuf_init(pbm); 1386a88b5ba8SSam Ravnborg 1387a88b5ba8SSam Ravnborg schizo_scan_bus(pbm, &op->dev); 1388a88b5ba8SSam Ravnborg 1389a88b5ba8SSam Ravnborg return 0; 1390a88b5ba8SSam Ravnborg } 1391a88b5ba8SSam Ravnborg 1392a88b5ba8SSam Ravnborg static inline int portid_compare(u32 x, u32 y, int chip_type) 1393a88b5ba8SSam Ravnborg { 1394a88b5ba8SSam Ravnborg if (chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1395a88b5ba8SSam Ravnborg if (x == (y ^ 1)) 1396a88b5ba8SSam Ravnborg return 1; 1397a88b5ba8SSam Ravnborg return 0; 1398a88b5ba8SSam Ravnborg } 1399a88b5ba8SSam Ravnborg return (x == y); 1400a88b5ba8SSam Ravnborg } 1401a88b5ba8SSam Ravnborg 1402a88b5ba8SSam Ravnborg static struct pci_pbm_info * __devinit schizo_find_sibling(u32 portid, 1403a88b5ba8SSam Ravnborg int chip_type) 1404a88b5ba8SSam Ravnborg { 1405a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm; 1406a88b5ba8SSam Ravnborg 1407a88b5ba8SSam Ravnborg for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 1408a88b5ba8SSam Ravnborg if (portid_compare(pbm->portid, portid, chip_type)) 1409a88b5ba8SSam Ravnborg return pbm; 1410a88b5ba8SSam Ravnborg } 1411a88b5ba8SSam Ravnborg return NULL; 1412a88b5ba8SSam Ravnborg } 1413a88b5ba8SSam Ravnborg 1414cd4cd730SGrant Likely static int __devinit __schizo_init(struct platform_device *op, unsigned long chip_type) 1415a88b5ba8SSam Ravnborg { 141661c7a080SGrant Likely struct device_node *dp = op->dev.of_node; 1417a88b5ba8SSam Ravnborg struct pci_pbm_info *pbm; 1418a88b5ba8SSam Ravnborg struct iommu *iommu; 1419a88b5ba8SSam Ravnborg u32 portid; 1420a88b5ba8SSam Ravnborg int err; 1421a88b5ba8SSam Ravnborg 1422a88b5ba8SSam Ravnborg portid = of_getintprop_default(dp, "portid", 0xff); 1423a88b5ba8SSam Ravnborg 1424a88b5ba8SSam Ravnborg err = -ENOMEM; 1425a88b5ba8SSam Ravnborg pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); 1426a88b5ba8SSam Ravnborg if (!pbm) { 1427a88b5ba8SSam Ravnborg printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); 1428a88b5ba8SSam Ravnborg goto out_err; 1429a88b5ba8SSam Ravnborg } 1430a88b5ba8SSam Ravnborg 1431a88b5ba8SSam Ravnborg pbm->sibling = schizo_find_sibling(portid, chip_type); 1432a88b5ba8SSam Ravnborg 1433a88b5ba8SSam Ravnborg iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); 1434a88b5ba8SSam Ravnborg if (!iommu) { 1435a88b5ba8SSam Ravnborg printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n"); 1436a88b5ba8SSam Ravnborg goto out_free_pbm; 1437a88b5ba8SSam Ravnborg } 1438a88b5ba8SSam Ravnborg 1439a88b5ba8SSam Ravnborg pbm->iommu = iommu; 1440a88b5ba8SSam Ravnborg 1441a88b5ba8SSam Ravnborg if (schizo_pbm_init(pbm, op, portid, chip_type)) 1442a88b5ba8SSam Ravnborg goto out_free_iommu; 1443a88b5ba8SSam Ravnborg 1444a88b5ba8SSam Ravnborg if (pbm->sibling) 1445a88b5ba8SSam Ravnborg pbm->sibling->sibling = pbm; 1446a88b5ba8SSam Ravnborg 1447a88b5ba8SSam Ravnborg dev_set_drvdata(&op->dev, pbm); 1448a88b5ba8SSam Ravnborg 1449a88b5ba8SSam Ravnborg return 0; 1450a88b5ba8SSam Ravnborg 1451a88b5ba8SSam Ravnborg out_free_iommu: 1452a88b5ba8SSam Ravnborg kfree(pbm->iommu); 1453a88b5ba8SSam Ravnborg 1454a88b5ba8SSam Ravnborg out_free_pbm: 1455a88b5ba8SSam Ravnborg kfree(pbm); 1456a88b5ba8SSam Ravnborg 1457a88b5ba8SSam Ravnborg out_err: 1458a88b5ba8SSam Ravnborg return err; 1459a88b5ba8SSam Ravnborg } 1460a88b5ba8SSam Ravnborg 14614ebb24f7SGrant Likely static int __devinit schizo_probe(struct platform_device *op) 1462a88b5ba8SSam Ravnborg { 14634ebb24f7SGrant Likely if (!op->dev.of_match) 14644ebb24f7SGrant Likely return -EINVAL; 14654ebb24f7SGrant Likely return __schizo_init(op, (unsigned long) op->dev.of_match->data); 1466a88b5ba8SSam Ravnborg } 1467a88b5ba8SSam Ravnborg 1468a88b5ba8SSam Ravnborg /* The ordering of this table is very important. Some Tomatillo 1469a88b5ba8SSam Ravnborg * nodes announce that they are compatible with both pci108e,a801 1470a88b5ba8SSam Ravnborg * and pci108e,8001. So list the chips in reverse chronological 1471a88b5ba8SSam Ravnborg * order. 1472a88b5ba8SSam Ravnborg */ 1473*3628aa06SDavid S. Miller static const struct of_device_id schizo_match[] = { 1474a88b5ba8SSam Ravnborg { 1475a88b5ba8SSam Ravnborg .name = "pci", 1476a88b5ba8SSam Ravnborg .compatible = "pci108e,a801", 1477a88b5ba8SSam Ravnborg .data = (void *) PBM_CHIP_TYPE_TOMATILLO, 1478a88b5ba8SSam Ravnborg }, 1479a88b5ba8SSam Ravnborg { 1480a88b5ba8SSam Ravnborg .name = "pci", 1481a88b5ba8SSam Ravnborg .compatible = "pci108e,8002", 1482a88b5ba8SSam Ravnborg .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS, 1483a88b5ba8SSam Ravnborg }, 1484a88b5ba8SSam Ravnborg { 1485a88b5ba8SSam Ravnborg .name = "pci", 1486a88b5ba8SSam Ravnborg .compatible = "pci108e,8001", 1487a88b5ba8SSam Ravnborg .data = (void *) PBM_CHIP_TYPE_SCHIZO, 1488a88b5ba8SSam Ravnborg }, 1489a88b5ba8SSam Ravnborg {}, 1490a88b5ba8SSam Ravnborg }; 1491a88b5ba8SSam Ravnborg 14924ebb24f7SGrant Likely static struct platform_driver schizo_driver = { 14934018294bSGrant Likely .driver = { 1494a88b5ba8SSam Ravnborg .name = DRIVER_NAME, 14954018294bSGrant Likely .owner = THIS_MODULE, 14964018294bSGrant Likely .of_match_table = schizo_match, 14974018294bSGrant Likely }, 1498a88b5ba8SSam Ravnborg .probe = schizo_probe, 1499a88b5ba8SSam Ravnborg }; 1500a88b5ba8SSam Ravnborg 1501a88b5ba8SSam Ravnborg static int __init schizo_init(void) 1502a88b5ba8SSam Ravnborg { 15034ebb24f7SGrant Likely return platform_driver_register(&schizo_driver); 1504a88b5ba8SSam Ravnborg } 1505a88b5ba8SSam Ravnborg 1506a88b5ba8SSam Ravnborg subsys_initcall(schizo_init); 1507