xref: /linux/arch/sparc/kernel/pci.c (revision b889fcf63cb62e7fdb7816565e28f44dbe4a76a5)
1 /* pci.c: UltraSparc PCI controller support.
2  *
3  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
5  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
6  *
7  * OF tree based PCI bus probing taken from the PowerPC port
8  * with minor modifications, see there for credits.
9  */
10 
11 #include <linux/export.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 
24 #include <asm/uaccess.h>
25 #include <asm/pgtable.h>
26 #include <asm/irq.h>
27 #include <asm/prom.h>
28 #include <asm/apb.h>
29 
30 #include "pci_impl.h"
31 
32 /* List of all PCI controllers found in the system. */
33 struct pci_pbm_info *pci_pbm_root = NULL;
34 
35 /* Each PBM found gets a unique index. */
36 int pci_num_pbms = 0;
37 
38 volatile int pci_poke_in_progress;
39 volatile int pci_poke_cpu = -1;
40 volatile int pci_poke_faulted;
41 
42 static DEFINE_SPINLOCK(pci_poke_lock);
43 
44 void pci_config_read8(u8 *addr, u8 *ret)
45 {
46 	unsigned long flags;
47 	u8 byte;
48 
49 	spin_lock_irqsave(&pci_poke_lock, flags);
50 	pci_poke_cpu = smp_processor_id();
51 	pci_poke_in_progress = 1;
52 	pci_poke_faulted = 0;
53 	__asm__ __volatile__("membar #Sync\n\t"
54 			     "lduba [%1] %2, %0\n\t"
55 			     "membar #Sync"
56 			     : "=r" (byte)
57 			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
58 			     : "memory");
59 	pci_poke_in_progress = 0;
60 	pci_poke_cpu = -1;
61 	if (!pci_poke_faulted)
62 		*ret = byte;
63 	spin_unlock_irqrestore(&pci_poke_lock, flags);
64 }
65 
66 void pci_config_read16(u16 *addr, u16 *ret)
67 {
68 	unsigned long flags;
69 	u16 word;
70 
71 	spin_lock_irqsave(&pci_poke_lock, flags);
72 	pci_poke_cpu = smp_processor_id();
73 	pci_poke_in_progress = 1;
74 	pci_poke_faulted = 0;
75 	__asm__ __volatile__("membar #Sync\n\t"
76 			     "lduha [%1] %2, %0\n\t"
77 			     "membar #Sync"
78 			     : "=r" (word)
79 			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
80 			     : "memory");
81 	pci_poke_in_progress = 0;
82 	pci_poke_cpu = -1;
83 	if (!pci_poke_faulted)
84 		*ret = word;
85 	spin_unlock_irqrestore(&pci_poke_lock, flags);
86 }
87 
88 void pci_config_read32(u32 *addr, u32 *ret)
89 {
90 	unsigned long flags;
91 	u32 dword;
92 
93 	spin_lock_irqsave(&pci_poke_lock, flags);
94 	pci_poke_cpu = smp_processor_id();
95 	pci_poke_in_progress = 1;
96 	pci_poke_faulted = 0;
97 	__asm__ __volatile__("membar #Sync\n\t"
98 			     "lduwa [%1] %2, %0\n\t"
99 			     "membar #Sync"
100 			     : "=r" (dword)
101 			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
102 			     : "memory");
103 	pci_poke_in_progress = 0;
104 	pci_poke_cpu = -1;
105 	if (!pci_poke_faulted)
106 		*ret = dword;
107 	spin_unlock_irqrestore(&pci_poke_lock, flags);
108 }
109 
110 void pci_config_write8(u8 *addr, u8 val)
111 {
112 	unsigned long flags;
113 
114 	spin_lock_irqsave(&pci_poke_lock, flags);
115 	pci_poke_cpu = smp_processor_id();
116 	pci_poke_in_progress = 1;
117 	pci_poke_faulted = 0;
118 	__asm__ __volatile__("membar #Sync\n\t"
119 			     "stba %0, [%1] %2\n\t"
120 			     "membar #Sync"
121 			     : /* no outputs */
122 			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
123 			     : "memory");
124 	pci_poke_in_progress = 0;
125 	pci_poke_cpu = -1;
126 	spin_unlock_irqrestore(&pci_poke_lock, flags);
127 }
128 
129 void pci_config_write16(u16 *addr, u16 val)
130 {
131 	unsigned long flags;
132 
133 	spin_lock_irqsave(&pci_poke_lock, flags);
134 	pci_poke_cpu = smp_processor_id();
135 	pci_poke_in_progress = 1;
136 	pci_poke_faulted = 0;
137 	__asm__ __volatile__("membar #Sync\n\t"
138 			     "stha %0, [%1] %2\n\t"
139 			     "membar #Sync"
140 			     : /* no outputs */
141 			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 			     : "memory");
143 	pci_poke_in_progress = 0;
144 	pci_poke_cpu = -1;
145 	spin_unlock_irqrestore(&pci_poke_lock, flags);
146 }
147 
148 void pci_config_write32(u32 *addr, u32 val)
149 {
150 	unsigned long flags;
151 
152 	spin_lock_irqsave(&pci_poke_lock, flags);
153 	pci_poke_cpu = smp_processor_id();
154 	pci_poke_in_progress = 1;
155 	pci_poke_faulted = 0;
156 	__asm__ __volatile__("membar #Sync\n\t"
157 			     "stwa %0, [%1] %2\n\t"
158 			     "membar #Sync"
159 			     : /* no outputs */
160 			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 			     : "memory");
162 	pci_poke_in_progress = 0;
163 	pci_poke_cpu = -1;
164 	spin_unlock_irqrestore(&pci_poke_lock, flags);
165 }
166 
167 static int ofpci_verbose;
168 
169 static int __init ofpci_debug(char *str)
170 {
171 	int val = 0;
172 
173 	get_option(&str, &val);
174 	if (val)
175 		ofpci_verbose = 1;
176 	return 1;
177 }
178 
179 __setup("ofpci_debug=", ofpci_debug);
180 
181 static unsigned long pci_parse_of_flags(u32 addr0)
182 {
183 	unsigned long flags = 0;
184 
185 	if (addr0 & 0x02000000) {
186 		flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
187 		flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
188 		flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
189 		if (addr0 & 0x40000000)
190 			flags |= IORESOURCE_PREFETCH
191 				 | PCI_BASE_ADDRESS_MEM_PREFETCH;
192 	} else if (addr0 & 0x01000000)
193 		flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
194 	return flags;
195 }
196 
197 /* The of_device layer has translated all of the assigned-address properties
198  * into physical address resources, we only have to figure out the register
199  * mapping.
200  */
201 static void pci_parse_of_addrs(struct platform_device *op,
202 			       struct device_node *node,
203 			       struct pci_dev *dev)
204 {
205 	struct resource *op_res;
206 	const u32 *addrs;
207 	int proplen;
208 
209 	addrs = of_get_property(node, "assigned-addresses", &proplen);
210 	if (!addrs)
211 		return;
212 	if (ofpci_verbose)
213 		printk("    parse addresses (%d bytes) @ %p\n",
214 		       proplen, addrs);
215 	op_res = &op->resource[0];
216 	for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
217 		struct resource *res;
218 		unsigned long flags;
219 		int i;
220 
221 		flags = pci_parse_of_flags(addrs[0]);
222 		if (!flags)
223 			continue;
224 		i = addrs[0] & 0xff;
225 		if (ofpci_verbose)
226 			printk("  start: %llx, end: %llx, i: %x\n",
227 			       op_res->start, op_res->end, i);
228 
229 		if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
230 			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
231 		} else if (i == dev->rom_base_reg) {
232 			res = &dev->resource[PCI_ROM_RESOURCE];
233 			flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE
234 			      | IORESOURCE_SIZEALIGN;
235 		} else {
236 			printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
237 			continue;
238 		}
239 		res->start = op_res->start;
240 		res->end = op_res->end;
241 		res->flags = flags;
242 		res->name = pci_name(dev);
243 	}
244 }
245 
246 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
247 					 struct device_node *node,
248 					 struct pci_bus *bus, int devfn)
249 {
250 	struct dev_archdata *sd;
251 	struct pci_slot *slot;
252 	struct platform_device *op;
253 	struct pci_dev *dev;
254 	const char *type;
255 	u32 class;
256 
257 	dev = alloc_pci_dev();
258 	if (!dev)
259 		return NULL;
260 
261 	sd = &dev->dev.archdata;
262 	sd->iommu = pbm->iommu;
263 	sd->stc = &pbm->stc;
264 	sd->host_controller = pbm;
265 	sd->op = op = of_find_device_by_node(node);
266 	sd->numa_node = pbm->numa_node;
267 
268 	sd = &op->dev.archdata;
269 	sd->iommu = pbm->iommu;
270 	sd->stc = &pbm->stc;
271 	sd->numa_node = pbm->numa_node;
272 
273 	if (!strcmp(node->name, "ebus"))
274 		of_propagate_archdata(op);
275 
276 	type = of_get_property(node, "device_type", NULL);
277 	if (type == NULL)
278 		type = "";
279 
280 	if (ofpci_verbose)
281 		printk("    create device, devfn: %x, type: %s\n",
282 		       devfn, type);
283 
284 	dev->bus = bus;
285 	dev->sysdata = node;
286 	dev->dev.parent = bus->bridge;
287 	dev->dev.bus = &pci_bus_type;
288 	dev->dev.of_node = of_node_get(node);
289 	dev->devfn = devfn;
290 	dev->multifunction = 0;		/* maybe a lie? */
291 	set_pcie_port_type(dev);
292 
293 	list_for_each_entry(slot, &dev->bus->slots, list)
294 		if (PCI_SLOT(dev->devfn) == slot->number)
295 			dev->slot = slot;
296 
297 	dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
298 	dev->device = of_getintprop_default(node, "device-id", 0xffff);
299 	dev->subsystem_vendor =
300 		of_getintprop_default(node, "subsystem-vendor-id", 0);
301 	dev->subsystem_device =
302 		of_getintprop_default(node, "subsystem-id", 0);
303 
304 	dev->cfg_size = pci_cfg_space_size(dev);
305 
306 	/* We can't actually use the firmware value, we have
307 	 * to read what is in the register right now.  One
308 	 * reason is that in the case of IDE interfaces the
309 	 * firmware can sample the value before the the IDE
310 	 * interface is programmed into native mode.
311 	 */
312 	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
313 	dev->class = class >> 8;
314 	dev->revision = class & 0xff;
315 
316 	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
317 		dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
318 
319 	if (ofpci_verbose)
320 		printk("    class: 0x%x device name: %s\n",
321 		       dev->class, pci_name(dev));
322 
323 	/* I have seen IDE devices which will not respond to
324 	 * the bmdma simplex check reads if bus mastering is
325 	 * disabled.
326 	 */
327 	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
328 		pci_set_master(dev);
329 
330 	dev->current_state = 4;		/* unknown power state */
331 	dev->error_state = pci_channel_io_normal;
332 	dev->dma_mask = 0xffffffff;
333 
334 	if (!strcmp(node->name, "pci")) {
335 		/* a PCI-PCI bridge */
336 		dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
337 		dev->rom_base_reg = PCI_ROM_ADDRESS1;
338 	} else if (!strcmp(type, "cardbus")) {
339 		dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
340 	} else {
341 		dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
342 		dev->rom_base_reg = PCI_ROM_ADDRESS;
343 
344 		dev->irq = sd->op->archdata.irqs[0];
345 		if (dev->irq == 0xffffffff)
346 			dev->irq = PCI_IRQ_NONE;
347 	}
348 
349 	pci_parse_of_addrs(sd->op, node, dev);
350 
351 	if (ofpci_verbose)
352 		printk("    adding to system ...\n");
353 
354 	pci_device_add(dev, bus);
355 
356 	return dev;
357 }
358 
359 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
360 {
361 	u32 idx, first, last;
362 
363 	first = 8;
364 	last = 0;
365 	for (idx = 0; idx < 8; idx++) {
366 		if ((map & (1 << idx)) != 0) {
367 			if (first > idx)
368 				first = idx;
369 			if (last < idx)
370 				last = idx;
371 		}
372 	}
373 
374 	*first_p = first;
375 	*last_p = last;
376 }
377 
378 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
379  * a proper 'ranges' property.
380  */
381 static void __devinit apb_fake_ranges(struct pci_dev *dev,
382 				      struct pci_bus *bus,
383 				      struct pci_pbm_info *pbm)
384 {
385 	struct pci_bus_region region;
386 	struct resource *res;
387 	u32 first, last;
388 	u8 map;
389 
390 	pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
391 	apb_calc_first_last(map, &first, &last);
392 	res = bus->resource[0];
393 	res->flags = IORESOURCE_IO;
394 	region.start = (first << 21);
395 	region.end = (last << 21) + ((1 << 21) - 1);
396 	pcibios_bus_to_resource(dev, res, &region);
397 
398 	pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
399 	apb_calc_first_last(map, &first, &last);
400 	res = bus->resource[1];
401 	res->flags = IORESOURCE_MEM;
402 	region.start = (first << 21);
403 	region.end = (last << 21) + ((1 << 21) - 1);
404 	pcibios_bus_to_resource(dev, res, &region);
405 }
406 
407 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
408 				      struct device_node *node,
409 				      struct pci_bus *bus);
410 
411 #define GET_64BIT(prop, i)	((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
412 
413 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
414 					 struct device_node *node,
415 					 struct pci_dev *dev)
416 {
417 	struct pci_bus *bus;
418 	const u32 *busrange, *ranges;
419 	int len, i, simba;
420 	struct pci_bus_region region;
421 	struct resource *res;
422 	unsigned int flags;
423 	u64 size;
424 
425 	if (ofpci_verbose)
426 		printk("of_scan_pci_bridge(%s)\n", node->full_name);
427 
428 	/* parse bus-range property */
429 	busrange = of_get_property(node, "bus-range", &len);
430 	if (busrange == NULL || len != 8) {
431 		printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
432 		       node->full_name);
433 		return;
434 	}
435 	ranges = of_get_property(node, "ranges", &len);
436 	simba = 0;
437 	if (ranges == NULL) {
438 		const char *model = of_get_property(node, "model", NULL);
439 		if (model && !strcmp(model, "SUNW,simba"))
440 			simba = 1;
441 	}
442 
443 	bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
444 	if (!bus) {
445 		printk(KERN_ERR "Failed to create pci bus for %s\n",
446 		       node->full_name);
447 		return;
448 	}
449 
450 	bus->primary = dev->bus->number;
451 	pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
452 	bus->bridge_ctl = 0;
453 
454 	/* parse ranges property, or cook one up by hand for Simba */
455 	/* PCI #address-cells == 3 and #size-cells == 2 always */
456 	res = &dev->resource[PCI_BRIDGE_RESOURCES];
457 	for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
458 		res->flags = 0;
459 		bus->resource[i] = res;
460 		++res;
461 	}
462 	if (simba) {
463 		apb_fake_ranges(dev, bus, pbm);
464 		goto after_ranges;
465 	} else if (ranges == NULL) {
466 		pci_read_bridge_bases(bus);
467 		goto after_ranges;
468 	}
469 	i = 1;
470 	for (; len >= 32; len -= 32, ranges += 8) {
471 		flags = pci_parse_of_flags(ranges[0]);
472 		size = GET_64BIT(ranges, 6);
473 		if (flags == 0 || size == 0)
474 			continue;
475 		if (flags & IORESOURCE_IO) {
476 			res = bus->resource[0];
477 			if (res->flags) {
478 				printk(KERN_ERR "PCI: ignoring extra I/O range"
479 				       " for bridge %s\n", node->full_name);
480 				continue;
481 			}
482 		} else {
483 			if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
484 				printk(KERN_ERR "PCI: too many memory ranges"
485 				       " for bridge %s\n", node->full_name);
486 				continue;
487 			}
488 			res = bus->resource[i];
489 			++i;
490 		}
491 
492 		res->flags = flags;
493 		region.start = GET_64BIT(ranges, 1);
494 		region.end = region.start + size - 1;
495 		pcibios_bus_to_resource(dev, res, &region);
496 	}
497 after_ranges:
498 	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
499 		bus->number);
500 	if (ofpci_verbose)
501 		printk("    bus name: %s\n", bus->name);
502 
503 	pci_of_scan_bus(pbm, node, bus);
504 }
505 
506 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
507 				      struct device_node *node,
508 				      struct pci_bus *bus)
509 {
510 	struct device_node *child;
511 	const u32 *reg;
512 	int reglen, devfn, prev_devfn;
513 	struct pci_dev *dev;
514 
515 	if (ofpci_verbose)
516 		printk("PCI: scan_bus[%s] bus no %d\n",
517 		       node->full_name, bus->number);
518 
519 	child = NULL;
520 	prev_devfn = -1;
521 	while ((child = of_get_next_child(node, child)) != NULL) {
522 		if (ofpci_verbose)
523 			printk("  * %s\n", child->full_name);
524 		reg = of_get_property(child, "reg", &reglen);
525 		if (reg == NULL || reglen < 20)
526 			continue;
527 
528 		devfn = (reg[0] >> 8) & 0xff;
529 
530 		/* This is a workaround for some device trees
531 		 * which list PCI devices twice.  On the V100
532 		 * for example, device number 3 is listed twice.
533 		 * Once as "pm" and once again as "lomp".
534 		 */
535 		if (devfn == prev_devfn)
536 			continue;
537 		prev_devfn = devfn;
538 
539 		/* create a new pci_dev for this device */
540 		dev = of_create_pci_dev(pbm, child, bus, devfn);
541 		if (!dev)
542 			continue;
543 		if (ofpci_verbose)
544 			printk("PCI: dev header type: %x\n",
545 			       dev->hdr_type);
546 
547 		if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
548 		    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
549 			of_scan_pci_bridge(pbm, child, dev);
550 	}
551 }
552 
553 static ssize_t
554 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
555 {
556 	struct pci_dev *pdev;
557 	struct device_node *dp;
558 
559 	pdev = to_pci_dev(dev);
560 	dp = pdev->dev.of_node;
561 
562 	return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
563 }
564 
565 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
566 
567 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
568 {
569 	struct pci_dev *dev;
570 	struct pci_bus *child_bus;
571 	int err;
572 
573 	list_for_each_entry(dev, &bus->devices, bus_list) {
574 		/* we don't really care if we can create this file or
575 		 * not, but we need to assign the result of the call
576 		 * or the world will fall under alien invasion and
577 		 * everybody will be frozen on a spaceship ready to be
578 		 * eaten on alpha centauri by some green and jelly
579 		 * humanoid.
580 		 */
581 		err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
582 		(void) err;
583 	}
584 	list_for_each_entry(child_bus, &bus->children, node)
585 		pci_bus_register_of_sysfs(child_bus);
586 }
587 
588 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
589 					    struct device *parent)
590 {
591 	LIST_HEAD(resources);
592 	struct device_node *node = pbm->op->dev.of_node;
593 	struct pci_bus *bus;
594 
595 	printk("PCI: Scanning PBM %s\n", node->full_name);
596 
597 	pci_add_resource_offset(&resources, &pbm->io_space,
598 				pbm->io_space.start);
599 	pci_add_resource_offset(&resources, &pbm->mem_space,
600 				pbm->mem_space.start);
601 	pbm->busn.start = pbm->pci_first_busno;
602 	pbm->busn.end	= pbm->pci_last_busno;
603 	pbm->busn.flags	= IORESOURCE_BUS;
604 	pci_add_resource(&resources, &pbm->busn);
605 	bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
606 				  pbm, &resources);
607 	if (!bus) {
608 		printk(KERN_ERR "Failed to create bus for %s\n",
609 		       node->full_name);
610 		pci_free_resource_list(&resources);
611 		return NULL;
612 	}
613 
614 	pci_of_scan_bus(pbm, node, bus);
615 	pci_bus_add_devices(bus);
616 	pci_bus_register_of_sysfs(bus);
617 
618 	return bus;
619 }
620 
621 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
622 {
623 }
624 
625 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
626 				resource_size_t size, resource_size_t align)
627 {
628 	return res->start;
629 }
630 
631 int pcibios_enable_device(struct pci_dev *dev, int mask)
632 {
633 	u16 cmd, oldcmd;
634 	int i;
635 
636 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
637 	oldcmd = cmd;
638 
639 	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
640 		struct resource *res = &dev->resource[i];
641 
642 		/* Only set up the requested stuff */
643 		if (!(mask & (1<<i)))
644 			continue;
645 
646 		if (res->flags & IORESOURCE_IO)
647 			cmd |= PCI_COMMAND_IO;
648 		if (res->flags & IORESOURCE_MEM)
649 			cmd |= PCI_COMMAND_MEMORY;
650 	}
651 
652 	if (cmd != oldcmd) {
653 		printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
654 		       pci_name(dev), cmd);
655                 /* Enable the appropriate bits in the PCI command register.  */
656 		pci_write_config_word(dev, PCI_COMMAND, cmd);
657 	}
658 	return 0;
659 }
660 
661 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
662 
663 /* If the user uses a host-bridge as the PCI device, he may use
664  * this to perform a raw mmap() of the I/O or MEM space behind
665  * that controller.
666  *
667  * This can be useful for execution of x86 PCI bios initialization code
668  * on a PCI card, like the xfree86 int10 stuff does.
669  */
670 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
671 				      enum pci_mmap_state mmap_state)
672 {
673 	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
674 	unsigned long space_size, user_offset, user_size;
675 
676 	if (mmap_state == pci_mmap_io) {
677 		space_size = resource_size(&pbm->io_space);
678 	} else {
679 		space_size = resource_size(&pbm->mem_space);
680 	}
681 
682 	/* Make sure the request is in range. */
683 	user_offset = vma->vm_pgoff << PAGE_SHIFT;
684 	user_size = vma->vm_end - vma->vm_start;
685 
686 	if (user_offset >= space_size ||
687 	    (user_offset + user_size) > space_size)
688 		return -EINVAL;
689 
690 	if (mmap_state == pci_mmap_io) {
691 		vma->vm_pgoff = (pbm->io_space.start +
692 				 user_offset) >> PAGE_SHIFT;
693 	} else {
694 		vma->vm_pgoff = (pbm->mem_space.start +
695 				 user_offset) >> PAGE_SHIFT;
696 	}
697 
698 	return 0;
699 }
700 
701 /* Adjust vm_pgoff of VMA such that it is the physical page offset
702  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
703  *
704  * Basically, the user finds the base address for his device which he wishes
705  * to mmap.  They read the 32-bit value from the config space base register,
706  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
707  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
708  *
709  * Returns negative error code on failure, zero on success.
710  */
711 static int __pci_mmap_make_offset(struct pci_dev *pdev,
712 				  struct vm_area_struct *vma,
713 				  enum pci_mmap_state mmap_state)
714 {
715 	unsigned long user_paddr, user_size;
716 	int i, err;
717 
718 	/* First compute the physical address in vma->vm_pgoff,
719 	 * making sure the user offset is within range in the
720 	 * appropriate PCI space.
721 	 */
722 	err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
723 	if (err)
724 		return err;
725 
726 	/* If this is a mapping on a host bridge, any address
727 	 * is OK.
728 	 */
729 	if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
730 		return err;
731 
732 	/* Otherwise make sure it's in the range for one of the
733 	 * device's resources.
734 	 */
735 	user_paddr = vma->vm_pgoff << PAGE_SHIFT;
736 	user_size = vma->vm_end - vma->vm_start;
737 
738 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
739 		struct resource *rp = &pdev->resource[i];
740 		resource_size_t aligned_end;
741 
742 		/* Active? */
743 		if (!rp->flags)
744 			continue;
745 
746 		/* Same type? */
747 		if (i == PCI_ROM_RESOURCE) {
748 			if (mmap_state != pci_mmap_mem)
749 				continue;
750 		} else {
751 			if ((mmap_state == pci_mmap_io &&
752 			     (rp->flags & IORESOURCE_IO) == 0) ||
753 			    (mmap_state == pci_mmap_mem &&
754 			     (rp->flags & IORESOURCE_MEM) == 0))
755 				continue;
756 		}
757 
758 		/* Align the resource end to the next page address.
759 		 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
760 		 * because actually we need the address of the next byte
761 		 * after rp->end.
762 		 */
763 		aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
764 
765 		if ((rp->start <= user_paddr) &&
766 		    (user_paddr + user_size) <= aligned_end)
767 			break;
768 	}
769 
770 	if (i > PCI_ROM_RESOURCE)
771 		return -EINVAL;
772 
773 	return 0;
774 }
775 
776 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
777  * mapping.
778  */
779 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
780 					    enum pci_mmap_state mmap_state)
781 {
782 	vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
783 }
784 
785 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
786  * device mapping.
787  */
788 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
789 					     enum pci_mmap_state mmap_state)
790 {
791 	/* Our io_remap_pfn_range takes care of this, do nothing.  */
792 }
793 
794 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
795  * for this architecture.  The region in the process to map is described by vm_start
796  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
797  * The pci device structure is provided so that architectures may make mapping
798  * decisions on a per-device or per-bus basis.
799  *
800  * Returns a negative error code on failure, zero on success.
801  */
802 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
803 			enum pci_mmap_state mmap_state,
804 			int write_combine)
805 {
806 	int ret;
807 
808 	ret = __pci_mmap_make_offset(dev, vma, mmap_state);
809 	if (ret < 0)
810 		return ret;
811 
812 	__pci_mmap_set_flags(dev, vma, mmap_state);
813 	__pci_mmap_set_pgprot(dev, vma, mmap_state);
814 
815 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
816 	ret = io_remap_pfn_range(vma, vma->vm_start,
817 				 vma->vm_pgoff,
818 				 vma->vm_end - vma->vm_start,
819 				 vma->vm_page_prot);
820 	if (ret)
821 		return ret;
822 
823 	return 0;
824 }
825 
826 #ifdef CONFIG_NUMA
827 int pcibus_to_node(struct pci_bus *pbus)
828 {
829 	struct pci_pbm_info *pbm = pbus->sysdata;
830 
831 	return pbm->numa_node;
832 }
833 EXPORT_SYMBOL(pcibus_to_node);
834 #endif
835 
836 /* Return the domain number for this pci bus */
837 
838 int pci_domain_nr(struct pci_bus *pbus)
839 {
840 	struct pci_pbm_info *pbm = pbus->sysdata;
841 	int ret;
842 
843 	if (!pbm) {
844 		ret = -ENXIO;
845 	} else {
846 		ret = pbm->index;
847 	}
848 
849 	return ret;
850 }
851 EXPORT_SYMBOL(pci_domain_nr);
852 
853 #ifdef CONFIG_PCI_MSI
854 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
855 {
856 	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
857 	unsigned int irq;
858 
859 	if (!pbm->setup_msi_irq)
860 		return -EINVAL;
861 
862 	return pbm->setup_msi_irq(&irq, pdev, desc);
863 }
864 
865 void arch_teardown_msi_irq(unsigned int irq)
866 {
867 	struct msi_desc *entry = irq_get_msi_desc(irq);
868 	struct pci_dev *pdev = entry->dev;
869 	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
870 
871 	if (pbm->teardown_msi_irq)
872 		pbm->teardown_msi_irq(irq, pdev);
873 }
874 #endif /* !(CONFIG_PCI_MSI) */
875 
876 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
877 {
878 	struct pci_dev *ali_isa_bridge;
879 	u8 val;
880 
881 	/* ALI sound chips generate 31-bits of DMA, a special register
882 	 * determines what bit 31 is emitted as.
883 	 */
884 	ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
885 					 PCI_DEVICE_ID_AL_M1533,
886 					 NULL);
887 
888 	pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
889 	if (set_bit)
890 		val |= 0x01;
891 	else
892 		val &= ~0x01;
893 	pci_write_config_byte(ali_isa_bridge, 0x7e, val);
894 	pci_dev_put(ali_isa_bridge);
895 }
896 
897 int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
898 {
899 	u64 dma_addr_mask;
900 
901 	if (pdev == NULL) {
902 		dma_addr_mask = 0xffffffff;
903 	} else {
904 		struct iommu *iommu = pdev->dev.archdata.iommu;
905 
906 		dma_addr_mask = iommu->dma_addr_mask;
907 
908 		if (pdev->vendor == PCI_VENDOR_ID_AL &&
909 		    pdev->device == PCI_DEVICE_ID_AL_M5451 &&
910 		    device_mask == 0x7fffffff) {
911 			ali_sound_dma_hack(pdev,
912 					   (dma_addr_mask & 0x80000000) != 0);
913 			return 1;
914 		}
915 	}
916 
917 	if (device_mask >= (1UL << 32UL))
918 		return 0;
919 
920 	return (device_mask & dma_addr_mask) == dma_addr_mask;
921 }
922 
923 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
924 			  const struct resource *rp, resource_size_t *start,
925 			  resource_size_t *end)
926 {
927 	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
928 	unsigned long offset;
929 
930 	if (rp->flags & IORESOURCE_IO)
931 		offset = pbm->io_space.start;
932 	else
933 		offset = pbm->mem_space.start;
934 
935 	*start = rp->start - offset;
936 	*end = rp->end - offset;
937 }
938 
939 void pcibios_set_master(struct pci_dev *dev)
940 {
941 	/* No special bus mastering setup handling */
942 }
943 
944 static int __init pcibios_init(void)
945 {
946 	pci_dfl_cache_line_size = 64 >> 2;
947 	return 0;
948 }
949 subsys_initcall(pcibios_init);
950 
951 #ifdef CONFIG_SYSFS
952 static void __devinit pci_bus_slot_names(struct device_node *node,
953 					 struct pci_bus *bus)
954 {
955 	const struct pci_slot_names {
956 		u32	slot_mask;
957 		char	names[0];
958 	} *prop;
959 	const char *sp;
960 	int len, i;
961 	u32 mask;
962 
963 	prop = of_get_property(node, "slot-names", &len);
964 	if (!prop)
965 		return;
966 
967 	mask = prop->slot_mask;
968 	sp = prop->names;
969 
970 	if (ofpci_verbose)
971 		printk("PCI: Making slots for [%s] mask[0x%02x]\n",
972 		       node->full_name, mask);
973 
974 	i = 0;
975 	while (mask) {
976 		struct pci_slot *pci_slot;
977 		u32 this_bit = 1 << i;
978 
979 		if (!(mask & this_bit)) {
980 			i++;
981 			continue;
982 		}
983 
984 		if (ofpci_verbose)
985 			printk("PCI: Making slot [%s]\n", sp);
986 
987 		pci_slot = pci_create_slot(bus, i, sp, NULL);
988 		if (IS_ERR(pci_slot))
989 			printk(KERN_ERR "PCI: pci_create_slot returned %ld\n",
990 			       PTR_ERR(pci_slot));
991 
992 		sp += strlen(sp) + 1;
993 		mask &= ~this_bit;
994 		i++;
995 	}
996 }
997 
998 static int __init of_pci_slot_init(void)
999 {
1000 	struct pci_bus *pbus = NULL;
1001 
1002 	while ((pbus = pci_find_next_bus(pbus)) != NULL) {
1003 		struct device_node *node;
1004 
1005 		if (pbus->self) {
1006 			/* PCI->PCI bridge */
1007 			node = pbus->self->dev.of_node;
1008 		} else {
1009 			struct pci_pbm_info *pbm = pbus->sysdata;
1010 
1011 			/* Host PCI controller */
1012 			node = pbm->op->dev.of_node;
1013 		}
1014 
1015 		pci_bus_slot_names(node, pbus);
1016 	}
1017 
1018 	return 0;
1019 }
1020 
1021 module_init(of_pci_slot_init);
1022 #endif
1023