1 /* pci.c: UltraSparc PCI controller support. 2 * 3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) 6 * 7 * OF tree based PCI bus probing taken from the PowerPC port 8 * with minor modifications, see there for credits. 9 */ 10 11 #include <linux/export.h> 12 #include <linux/kernel.h> 13 #include <linux/string.h> 14 #include <linux/sched.h> 15 #include <linux/capability.h> 16 #include <linux/errno.h> 17 #include <linux/pci.h> 18 #include <linux/msi.h> 19 #include <linux/irq.h> 20 #include <linux/init.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 24 #include <asm/uaccess.h> 25 #include <asm/pgtable.h> 26 #include <asm/irq.h> 27 #include <asm/prom.h> 28 #include <asm/apb.h> 29 30 #include "pci_impl.h" 31 32 /* List of all PCI controllers found in the system. */ 33 struct pci_pbm_info *pci_pbm_root = NULL; 34 35 /* Each PBM found gets a unique index. */ 36 int pci_num_pbms = 0; 37 38 volatile int pci_poke_in_progress; 39 volatile int pci_poke_cpu = -1; 40 volatile int pci_poke_faulted; 41 42 static DEFINE_SPINLOCK(pci_poke_lock); 43 44 void pci_config_read8(u8 *addr, u8 *ret) 45 { 46 unsigned long flags; 47 u8 byte; 48 49 spin_lock_irqsave(&pci_poke_lock, flags); 50 pci_poke_cpu = smp_processor_id(); 51 pci_poke_in_progress = 1; 52 pci_poke_faulted = 0; 53 __asm__ __volatile__("membar #Sync\n\t" 54 "lduba [%1] %2, %0\n\t" 55 "membar #Sync" 56 : "=r" (byte) 57 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 58 : "memory"); 59 pci_poke_in_progress = 0; 60 pci_poke_cpu = -1; 61 if (!pci_poke_faulted) 62 *ret = byte; 63 spin_unlock_irqrestore(&pci_poke_lock, flags); 64 } 65 66 void pci_config_read16(u16 *addr, u16 *ret) 67 { 68 unsigned long flags; 69 u16 word; 70 71 spin_lock_irqsave(&pci_poke_lock, flags); 72 pci_poke_cpu = smp_processor_id(); 73 pci_poke_in_progress = 1; 74 pci_poke_faulted = 0; 75 __asm__ __volatile__("membar #Sync\n\t" 76 "lduha [%1] %2, %0\n\t" 77 "membar #Sync" 78 : "=r" (word) 79 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 80 : "memory"); 81 pci_poke_in_progress = 0; 82 pci_poke_cpu = -1; 83 if (!pci_poke_faulted) 84 *ret = word; 85 spin_unlock_irqrestore(&pci_poke_lock, flags); 86 } 87 88 void pci_config_read32(u32 *addr, u32 *ret) 89 { 90 unsigned long flags; 91 u32 dword; 92 93 spin_lock_irqsave(&pci_poke_lock, flags); 94 pci_poke_cpu = smp_processor_id(); 95 pci_poke_in_progress = 1; 96 pci_poke_faulted = 0; 97 __asm__ __volatile__("membar #Sync\n\t" 98 "lduwa [%1] %2, %0\n\t" 99 "membar #Sync" 100 : "=r" (dword) 101 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 102 : "memory"); 103 pci_poke_in_progress = 0; 104 pci_poke_cpu = -1; 105 if (!pci_poke_faulted) 106 *ret = dword; 107 spin_unlock_irqrestore(&pci_poke_lock, flags); 108 } 109 110 void pci_config_write8(u8 *addr, u8 val) 111 { 112 unsigned long flags; 113 114 spin_lock_irqsave(&pci_poke_lock, flags); 115 pci_poke_cpu = smp_processor_id(); 116 pci_poke_in_progress = 1; 117 pci_poke_faulted = 0; 118 __asm__ __volatile__("membar #Sync\n\t" 119 "stba %0, [%1] %2\n\t" 120 "membar #Sync" 121 : /* no outputs */ 122 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 123 : "memory"); 124 pci_poke_in_progress = 0; 125 pci_poke_cpu = -1; 126 spin_unlock_irqrestore(&pci_poke_lock, flags); 127 } 128 129 void pci_config_write16(u16 *addr, u16 val) 130 { 131 unsigned long flags; 132 133 spin_lock_irqsave(&pci_poke_lock, flags); 134 pci_poke_cpu = smp_processor_id(); 135 pci_poke_in_progress = 1; 136 pci_poke_faulted = 0; 137 __asm__ __volatile__("membar #Sync\n\t" 138 "stha %0, [%1] %2\n\t" 139 "membar #Sync" 140 : /* no outputs */ 141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 142 : "memory"); 143 pci_poke_in_progress = 0; 144 pci_poke_cpu = -1; 145 spin_unlock_irqrestore(&pci_poke_lock, flags); 146 } 147 148 void pci_config_write32(u32 *addr, u32 val) 149 { 150 unsigned long flags; 151 152 spin_lock_irqsave(&pci_poke_lock, flags); 153 pci_poke_cpu = smp_processor_id(); 154 pci_poke_in_progress = 1; 155 pci_poke_faulted = 0; 156 __asm__ __volatile__("membar #Sync\n\t" 157 "stwa %0, [%1] %2\n\t" 158 "membar #Sync" 159 : /* no outputs */ 160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 161 : "memory"); 162 pci_poke_in_progress = 0; 163 pci_poke_cpu = -1; 164 spin_unlock_irqrestore(&pci_poke_lock, flags); 165 } 166 167 static int ofpci_verbose; 168 169 static int __init ofpci_debug(char *str) 170 { 171 int val = 0; 172 173 get_option(&str, &val); 174 if (val) 175 ofpci_verbose = 1; 176 return 1; 177 } 178 179 __setup("ofpci_debug=", ofpci_debug); 180 181 static unsigned long pci_parse_of_flags(u32 addr0) 182 { 183 unsigned long flags = 0; 184 185 if (addr0 & 0x02000000) { 186 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; 187 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; 188 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; 189 if (addr0 & 0x40000000) 190 flags |= IORESOURCE_PREFETCH 191 | PCI_BASE_ADDRESS_MEM_PREFETCH; 192 } else if (addr0 & 0x01000000) 193 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; 194 return flags; 195 } 196 197 /* The of_device layer has translated all of the assigned-address properties 198 * into physical address resources, we only have to figure out the register 199 * mapping. 200 */ 201 static void pci_parse_of_addrs(struct platform_device *op, 202 struct device_node *node, 203 struct pci_dev *dev) 204 { 205 struct resource *op_res; 206 const u32 *addrs; 207 int proplen; 208 209 addrs = of_get_property(node, "assigned-addresses", &proplen); 210 if (!addrs) 211 return; 212 if (ofpci_verbose) 213 printk(" parse addresses (%d bytes) @ %p\n", 214 proplen, addrs); 215 op_res = &op->resource[0]; 216 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { 217 struct resource *res; 218 unsigned long flags; 219 int i; 220 221 flags = pci_parse_of_flags(addrs[0]); 222 if (!flags) 223 continue; 224 i = addrs[0] & 0xff; 225 if (ofpci_verbose) 226 printk(" start: %llx, end: %llx, i: %x\n", 227 op_res->start, op_res->end, i); 228 229 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { 230 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; 231 } else if (i == dev->rom_base_reg) { 232 res = &dev->resource[PCI_ROM_RESOURCE]; 233 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE 234 | IORESOURCE_SIZEALIGN; 235 } else { 236 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); 237 continue; 238 } 239 res->start = op_res->start; 240 res->end = op_res->end; 241 res->flags = flags; 242 res->name = pci_name(dev); 243 } 244 } 245 246 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, 247 struct device_node *node, 248 struct pci_bus *bus, int devfn) 249 { 250 struct dev_archdata *sd; 251 struct pci_slot *slot; 252 struct platform_device *op; 253 struct pci_dev *dev; 254 const char *type; 255 u32 class; 256 257 dev = alloc_pci_dev(); 258 if (!dev) 259 return NULL; 260 261 sd = &dev->dev.archdata; 262 sd->iommu = pbm->iommu; 263 sd->stc = &pbm->stc; 264 sd->host_controller = pbm; 265 sd->op = op = of_find_device_by_node(node); 266 sd->numa_node = pbm->numa_node; 267 268 sd = &op->dev.archdata; 269 sd->iommu = pbm->iommu; 270 sd->stc = &pbm->stc; 271 sd->numa_node = pbm->numa_node; 272 273 if (!strcmp(node->name, "ebus")) 274 of_propagate_archdata(op); 275 276 type = of_get_property(node, "device_type", NULL); 277 if (type == NULL) 278 type = ""; 279 280 if (ofpci_verbose) 281 printk(" create device, devfn: %x, type: %s\n", 282 devfn, type); 283 284 dev->bus = bus; 285 dev->sysdata = node; 286 dev->dev.parent = bus->bridge; 287 dev->dev.bus = &pci_bus_type; 288 dev->dev.of_node = of_node_get(node); 289 dev->devfn = devfn; 290 dev->multifunction = 0; /* maybe a lie? */ 291 set_pcie_port_type(dev); 292 293 list_for_each_entry(slot, &dev->bus->slots, list) 294 if (PCI_SLOT(dev->devfn) == slot->number) 295 dev->slot = slot; 296 297 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); 298 dev->device = of_getintprop_default(node, "device-id", 0xffff); 299 dev->subsystem_vendor = 300 of_getintprop_default(node, "subsystem-vendor-id", 0); 301 dev->subsystem_device = 302 of_getintprop_default(node, "subsystem-id", 0); 303 304 dev->cfg_size = pci_cfg_space_size(dev); 305 306 /* We can't actually use the firmware value, we have 307 * to read what is in the register right now. One 308 * reason is that in the case of IDE interfaces the 309 * firmware can sample the value before the the IDE 310 * interface is programmed into native mode. 311 */ 312 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 313 dev->class = class >> 8; 314 dev->revision = class & 0xff; 315 316 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), 317 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 318 319 if (ofpci_verbose) 320 printk(" class: 0x%x device name: %s\n", 321 dev->class, pci_name(dev)); 322 323 /* I have seen IDE devices which will not respond to 324 * the bmdma simplex check reads if bus mastering is 325 * disabled. 326 */ 327 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) 328 pci_set_master(dev); 329 330 dev->current_state = 4; /* unknown power state */ 331 dev->error_state = pci_channel_io_normal; 332 dev->dma_mask = 0xffffffff; 333 334 if (!strcmp(node->name, "pci")) { 335 /* a PCI-PCI bridge */ 336 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; 337 dev->rom_base_reg = PCI_ROM_ADDRESS1; 338 } else if (!strcmp(type, "cardbus")) { 339 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; 340 } else { 341 dev->hdr_type = PCI_HEADER_TYPE_NORMAL; 342 dev->rom_base_reg = PCI_ROM_ADDRESS; 343 344 dev->irq = sd->op->archdata.irqs[0]; 345 if (dev->irq == 0xffffffff) 346 dev->irq = PCI_IRQ_NONE; 347 } 348 349 pci_parse_of_addrs(sd->op, node, dev); 350 351 if (ofpci_verbose) 352 printk(" adding to system ...\n"); 353 354 pci_device_add(dev, bus); 355 356 return dev; 357 } 358 359 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) 360 { 361 u32 idx, first, last; 362 363 first = 8; 364 last = 0; 365 for (idx = 0; idx < 8; idx++) { 366 if ((map & (1 << idx)) != 0) { 367 if (first > idx) 368 first = idx; 369 if (last < idx) 370 last = idx; 371 } 372 } 373 374 *first_p = first; 375 *last_p = last; 376 } 377 378 static void pci_resource_adjust(struct resource *res, 379 struct resource *root) 380 { 381 res->start += root->start; 382 res->end += root->start; 383 } 384 385 /* For PCI bus devices which lack a 'ranges' property we interrogate 386 * the config space values to set the resources, just like the generic 387 * Linux PCI probing code does. 388 */ 389 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev, 390 struct pci_bus *bus, 391 struct pci_pbm_info *pbm) 392 { 393 struct resource *res; 394 u8 io_base_lo, io_limit_lo; 395 u16 mem_base_lo, mem_limit_lo; 396 unsigned long base, limit; 397 398 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 399 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 400 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 401 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 402 403 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 404 u16 io_base_hi, io_limit_hi; 405 406 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 407 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 408 base |= (io_base_hi << 16); 409 limit |= (io_limit_hi << 16); 410 } 411 412 res = bus->resource[0]; 413 if (base <= limit) { 414 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 415 if (!res->start) 416 res->start = base; 417 if (!res->end) 418 res->end = limit + 0xfff; 419 pci_resource_adjust(res, &pbm->io_space); 420 } 421 422 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 423 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 424 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 425 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 426 427 res = bus->resource[1]; 428 if (base <= limit) { 429 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | 430 IORESOURCE_MEM); 431 res->start = base; 432 res->end = limit + 0xfffff; 433 pci_resource_adjust(res, &pbm->mem_space); 434 } 435 436 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 437 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 438 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 439 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 440 441 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 442 u32 mem_base_hi, mem_limit_hi; 443 444 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 445 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 446 447 /* 448 * Some bridges set the base > limit by default, and some 449 * (broken) BIOSes do not initialize them. If we find 450 * this, just assume they are not being used. 451 */ 452 if (mem_base_hi <= mem_limit_hi) { 453 base |= ((long) mem_base_hi) << 32; 454 limit |= ((long) mem_limit_hi) << 32; 455 } 456 } 457 458 res = bus->resource[2]; 459 if (base <= limit) { 460 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | 461 IORESOURCE_MEM | IORESOURCE_PREFETCH); 462 res->start = base; 463 res->end = limit + 0xfffff; 464 pci_resource_adjust(res, &pbm->mem_space); 465 } 466 } 467 468 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack 469 * a proper 'ranges' property. 470 */ 471 static void __devinit apb_fake_ranges(struct pci_dev *dev, 472 struct pci_bus *bus, 473 struct pci_pbm_info *pbm) 474 { 475 struct resource *res; 476 u32 first, last; 477 u8 map; 478 479 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); 480 apb_calc_first_last(map, &first, &last); 481 res = bus->resource[0]; 482 res->start = (first << 21); 483 res->end = (last << 21) + ((1 << 21) - 1); 484 res->flags = IORESOURCE_IO; 485 pci_resource_adjust(res, &pbm->io_space); 486 487 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); 488 apb_calc_first_last(map, &first, &last); 489 res = bus->resource[1]; 490 res->start = (first << 21); 491 res->end = (last << 21) + ((1 << 21) - 1); 492 res->flags = IORESOURCE_MEM; 493 pci_resource_adjust(res, &pbm->mem_space); 494 } 495 496 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, 497 struct device_node *node, 498 struct pci_bus *bus); 499 500 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) 501 502 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, 503 struct device_node *node, 504 struct pci_dev *dev) 505 { 506 struct pci_bus *bus; 507 const u32 *busrange, *ranges; 508 int len, i, simba; 509 struct resource *res; 510 unsigned int flags; 511 u64 size; 512 513 if (ofpci_verbose) 514 printk("of_scan_pci_bridge(%s)\n", node->full_name); 515 516 /* parse bus-range property */ 517 busrange = of_get_property(node, "bus-range", &len); 518 if (busrange == NULL || len != 8) { 519 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", 520 node->full_name); 521 return; 522 } 523 ranges = of_get_property(node, "ranges", &len); 524 simba = 0; 525 if (ranges == NULL) { 526 const char *model = of_get_property(node, "model", NULL); 527 if (model && !strcmp(model, "SUNW,simba")) 528 simba = 1; 529 } 530 531 bus = pci_add_new_bus(dev->bus, dev, busrange[0]); 532 if (!bus) { 533 printk(KERN_ERR "Failed to create pci bus for %s\n", 534 node->full_name); 535 return; 536 } 537 538 bus->primary = dev->bus->number; 539 bus->subordinate = busrange[1]; 540 bus->bridge_ctl = 0; 541 542 /* parse ranges property, or cook one up by hand for Simba */ 543 /* PCI #address-cells == 3 and #size-cells == 2 always */ 544 res = &dev->resource[PCI_BRIDGE_RESOURCES]; 545 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { 546 res->flags = 0; 547 bus->resource[i] = res; 548 ++res; 549 } 550 if (simba) { 551 apb_fake_ranges(dev, bus, pbm); 552 goto after_ranges; 553 } else if (ranges == NULL) { 554 pci_cfg_fake_ranges(dev, bus, pbm); 555 goto after_ranges; 556 } 557 i = 1; 558 for (; len >= 32; len -= 32, ranges += 8) { 559 struct resource *root; 560 561 flags = pci_parse_of_flags(ranges[0]); 562 size = GET_64BIT(ranges, 6); 563 if (flags == 0 || size == 0) 564 continue; 565 if (flags & IORESOURCE_IO) { 566 res = bus->resource[0]; 567 if (res->flags) { 568 printk(KERN_ERR "PCI: ignoring extra I/O range" 569 " for bridge %s\n", node->full_name); 570 continue; 571 } 572 root = &pbm->io_space; 573 } else { 574 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { 575 printk(KERN_ERR "PCI: too many memory ranges" 576 " for bridge %s\n", node->full_name); 577 continue; 578 } 579 res = bus->resource[i]; 580 ++i; 581 root = &pbm->mem_space; 582 } 583 584 res->start = GET_64BIT(ranges, 1); 585 res->end = res->start + size - 1; 586 res->flags = flags; 587 588 /* Another way to implement this would be to add an of_device 589 * layer routine that can calculate a resource for a given 590 * range property value in a PCI device. 591 */ 592 pci_resource_adjust(res, root); 593 } 594 after_ranges: 595 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 596 bus->number); 597 if (ofpci_verbose) 598 printk(" bus name: %s\n", bus->name); 599 600 pci_of_scan_bus(pbm, node, bus); 601 } 602 603 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, 604 struct device_node *node, 605 struct pci_bus *bus) 606 { 607 struct device_node *child; 608 const u32 *reg; 609 int reglen, devfn, prev_devfn; 610 struct pci_dev *dev; 611 612 if (ofpci_verbose) 613 printk("PCI: scan_bus[%s] bus no %d\n", 614 node->full_name, bus->number); 615 616 child = NULL; 617 prev_devfn = -1; 618 while ((child = of_get_next_child(node, child)) != NULL) { 619 if (ofpci_verbose) 620 printk(" * %s\n", child->full_name); 621 reg = of_get_property(child, "reg", ®len); 622 if (reg == NULL || reglen < 20) 623 continue; 624 625 devfn = (reg[0] >> 8) & 0xff; 626 627 /* This is a workaround for some device trees 628 * which list PCI devices twice. On the V100 629 * for example, device number 3 is listed twice. 630 * Once as "pm" and once again as "lomp". 631 */ 632 if (devfn == prev_devfn) 633 continue; 634 prev_devfn = devfn; 635 636 /* create a new pci_dev for this device */ 637 dev = of_create_pci_dev(pbm, child, bus, devfn); 638 if (!dev) 639 continue; 640 if (ofpci_verbose) 641 printk("PCI: dev header type: %x\n", 642 dev->hdr_type); 643 644 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 645 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 646 of_scan_pci_bridge(pbm, child, dev); 647 } 648 } 649 650 static ssize_t 651 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) 652 { 653 struct pci_dev *pdev; 654 struct device_node *dp; 655 656 pdev = to_pci_dev(dev); 657 dp = pdev->dev.of_node; 658 659 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); 660 } 661 662 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); 663 664 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) 665 { 666 struct pci_dev *dev; 667 struct pci_bus *child_bus; 668 int err; 669 670 list_for_each_entry(dev, &bus->devices, bus_list) { 671 /* we don't really care if we can create this file or 672 * not, but we need to assign the result of the call 673 * or the world will fall under alien invasion and 674 * everybody will be frozen on a spaceship ready to be 675 * eaten on alpha centauri by some green and jelly 676 * humanoid. 677 */ 678 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); 679 (void) err; 680 } 681 list_for_each_entry(child_bus, &bus->children, node) 682 pci_bus_register_of_sysfs(child_bus); 683 } 684 685 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, 686 struct device *parent) 687 { 688 LIST_HEAD(resources); 689 struct device_node *node = pbm->op->dev.of_node; 690 struct pci_bus *bus; 691 692 printk("PCI: Scanning PBM %s\n", node->full_name); 693 694 pci_add_resource(&resources, &pbm->io_space); 695 pci_add_resource(&resources, &pbm->mem_space); 696 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops, 697 pbm, &resources); 698 if (!bus) { 699 printk(KERN_ERR "Failed to create bus for %s\n", 700 node->full_name); 701 pci_free_resource_list(&resources); 702 return NULL; 703 } 704 bus->secondary = pbm->pci_first_busno; 705 bus->subordinate = pbm->pci_last_busno; 706 707 pci_of_scan_bus(pbm, node, bus); 708 pci_bus_add_devices(bus); 709 pci_bus_register_of_sysfs(bus); 710 711 return bus; 712 } 713 714 void __devinit pcibios_fixup_bus(struct pci_bus *pbus) 715 { 716 } 717 718 void pcibios_update_irq(struct pci_dev *pdev, int irq) 719 { 720 } 721 722 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 723 resource_size_t size, resource_size_t align) 724 { 725 return res->start; 726 } 727 728 int pcibios_enable_device(struct pci_dev *dev, int mask) 729 { 730 u16 cmd, oldcmd; 731 int i; 732 733 pci_read_config_word(dev, PCI_COMMAND, &cmd); 734 oldcmd = cmd; 735 736 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 737 struct resource *res = &dev->resource[i]; 738 739 /* Only set up the requested stuff */ 740 if (!(mask & (1<<i))) 741 continue; 742 743 if (res->flags & IORESOURCE_IO) 744 cmd |= PCI_COMMAND_IO; 745 if (res->flags & IORESOURCE_MEM) 746 cmd |= PCI_COMMAND_MEMORY; 747 } 748 749 if (cmd != oldcmd) { 750 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", 751 pci_name(dev), cmd); 752 /* Enable the appropriate bits in the PCI command register. */ 753 pci_write_config_word(dev, PCI_COMMAND, cmd); 754 } 755 return 0; 756 } 757 758 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, 759 struct resource *res) 760 { 761 struct pci_pbm_info *pbm = pdev->bus->sysdata; 762 struct resource zero_res, *root; 763 764 zero_res.start = 0; 765 zero_res.end = 0; 766 zero_res.flags = res->flags; 767 768 if (res->flags & IORESOURCE_IO) 769 root = &pbm->io_space; 770 else 771 root = &pbm->mem_space; 772 773 pci_resource_adjust(&zero_res, root); 774 775 region->start = res->start - zero_res.start; 776 region->end = res->end - zero_res.start; 777 } 778 EXPORT_SYMBOL(pcibios_resource_to_bus); 779 780 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, 781 struct pci_bus_region *region) 782 { 783 struct pci_pbm_info *pbm = pdev->bus->sysdata; 784 struct resource *root; 785 786 res->start = region->start; 787 res->end = region->end; 788 789 if (res->flags & IORESOURCE_IO) 790 root = &pbm->io_space; 791 else 792 root = &pbm->mem_space; 793 794 pci_resource_adjust(res, root); 795 } 796 EXPORT_SYMBOL(pcibios_bus_to_resource); 797 798 char * __devinit pcibios_setup(char *str) 799 { 800 return str; 801 } 802 803 /* Platform support for /proc/bus/pci/X/Y mmap()s. */ 804 805 /* If the user uses a host-bridge as the PCI device, he may use 806 * this to perform a raw mmap() of the I/O or MEM space behind 807 * that controller. 808 * 809 * This can be useful for execution of x86 PCI bios initialization code 810 * on a PCI card, like the xfree86 int10 stuff does. 811 */ 812 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, 813 enum pci_mmap_state mmap_state) 814 { 815 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 816 unsigned long space_size, user_offset, user_size; 817 818 if (mmap_state == pci_mmap_io) { 819 space_size = resource_size(&pbm->io_space); 820 } else { 821 space_size = resource_size(&pbm->mem_space); 822 } 823 824 /* Make sure the request is in range. */ 825 user_offset = vma->vm_pgoff << PAGE_SHIFT; 826 user_size = vma->vm_end - vma->vm_start; 827 828 if (user_offset >= space_size || 829 (user_offset + user_size) > space_size) 830 return -EINVAL; 831 832 if (mmap_state == pci_mmap_io) { 833 vma->vm_pgoff = (pbm->io_space.start + 834 user_offset) >> PAGE_SHIFT; 835 } else { 836 vma->vm_pgoff = (pbm->mem_space.start + 837 user_offset) >> PAGE_SHIFT; 838 } 839 840 return 0; 841 } 842 843 /* Adjust vm_pgoff of VMA such that it is the physical page offset 844 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 845 * 846 * Basically, the user finds the base address for his device which he wishes 847 * to mmap. They read the 32-bit value from the config space base register, 848 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 849 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 850 * 851 * Returns negative error code on failure, zero on success. 852 */ 853 static int __pci_mmap_make_offset(struct pci_dev *pdev, 854 struct vm_area_struct *vma, 855 enum pci_mmap_state mmap_state) 856 { 857 unsigned long user_paddr, user_size; 858 int i, err; 859 860 /* First compute the physical address in vma->vm_pgoff, 861 * making sure the user offset is within range in the 862 * appropriate PCI space. 863 */ 864 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state); 865 if (err) 866 return err; 867 868 /* If this is a mapping on a host bridge, any address 869 * is OK. 870 */ 871 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST) 872 return err; 873 874 /* Otherwise make sure it's in the range for one of the 875 * device's resources. 876 */ 877 user_paddr = vma->vm_pgoff << PAGE_SHIFT; 878 user_size = vma->vm_end - vma->vm_start; 879 880 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 881 struct resource *rp = &pdev->resource[i]; 882 resource_size_t aligned_end; 883 884 /* Active? */ 885 if (!rp->flags) 886 continue; 887 888 /* Same type? */ 889 if (i == PCI_ROM_RESOURCE) { 890 if (mmap_state != pci_mmap_mem) 891 continue; 892 } else { 893 if ((mmap_state == pci_mmap_io && 894 (rp->flags & IORESOURCE_IO) == 0) || 895 (mmap_state == pci_mmap_mem && 896 (rp->flags & IORESOURCE_MEM) == 0)) 897 continue; 898 } 899 900 /* Align the resource end to the next page address. 901 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1), 902 * because actually we need the address of the next byte 903 * after rp->end. 904 */ 905 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK; 906 907 if ((rp->start <= user_paddr) && 908 (user_paddr + user_size) <= aligned_end) 909 break; 910 } 911 912 if (i > PCI_ROM_RESOURCE) 913 return -EINVAL; 914 915 return 0; 916 } 917 918 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device 919 * mapping. 920 */ 921 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, 922 enum pci_mmap_state mmap_state) 923 { 924 vma->vm_flags |= (VM_IO | VM_RESERVED); 925 } 926 927 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 928 * device mapping. 929 */ 930 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, 931 enum pci_mmap_state mmap_state) 932 { 933 /* Our io_remap_pfn_range takes care of this, do nothing. */ 934 } 935 936 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate 937 * for this architecture. The region in the process to map is described by vm_start 938 * and vm_end members of VMA, the base physical address is found in vm_pgoff. 939 * The pci device structure is provided so that architectures may make mapping 940 * decisions on a per-device or per-bus basis. 941 * 942 * Returns a negative error code on failure, zero on success. 943 */ 944 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 945 enum pci_mmap_state mmap_state, 946 int write_combine) 947 { 948 int ret; 949 950 ret = __pci_mmap_make_offset(dev, vma, mmap_state); 951 if (ret < 0) 952 return ret; 953 954 __pci_mmap_set_flags(dev, vma, mmap_state); 955 __pci_mmap_set_pgprot(dev, vma, mmap_state); 956 957 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 958 ret = io_remap_pfn_range(vma, vma->vm_start, 959 vma->vm_pgoff, 960 vma->vm_end - vma->vm_start, 961 vma->vm_page_prot); 962 if (ret) 963 return ret; 964 965 return 0; 966 } 967 968 #ifdef CONFIG_NUMA 969 int pcibus_to_node(struct pci_bus *pbus) 970 { 971 struct pci_pbm_info *pbm = pbus->sysdata; 972 973 return pbm->numa_node; 974 } 975 EXPORT_SYMBOL(pcibus_to_node); 976 #endif 977 978 /* Return the domain number for this pci bus */ 979 980 int pci_domain_nr(struct pci_bus *pbus) 981 { 982 struct pci_pbm_info *pbm = pbus->sysdata; 983 int ret; 984 985 if (!pbm) { 986 ret = -ENXIO; 987 } else { 988 ret = pbm->index; 989 } 990 991 return ret; 992 } 993 EXPORT_SYMBOL(pci_domain_nr); 994 995 #ifdef CONFIG_PCI_MSI 996 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 997 { 998 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 999 unsigned int irq; 1000 1001 if (!pbm->setup_msi_irq) 1002 return -EINVAL; 1003 1004 return pbm->setup_msi_irq(&irq, pdev, desc); 1005 } 1006 1007 void arch_teardown_msi_irq(unsigned int irq) 1008 { 1009 struct msi_desc *entry = irq_get_msi_desc(irq); 1010 struct pci_dev *pdev = entry->dev; 1011 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 1012 1013 if (pbm->teardown_msi_irq) 1014 pbm->teardown_msi_irq(irq, pdev); 1015 } 1016 #endif /* !(CONFIG_PCI_MSI) */ 1017 1018 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) 1019 { 1020 struct pci_dev *ali_isa_bridge; 1021 u8 val; 1022 1023 /* ALI sound chips generate 31-bits of DMA, a special register 1024 * determines what bit 31 is emitted as. 1025 */ 1026 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, 1027 PCI_DEVICE_ID_AL_M1533, 1028 NULL); 1029 1030 pci_read_config_byte(ali_isa_bridge, 0x7e, &val); 1031 if (set_bit) 1032 val |= 0x01; 1033 else 1034 val &= ~0x01; 1035 pci_write_config_byte(ali_isa_bridge, 0x7e, val); 1036 pci_dev_put(ali_isa_bridge); 1037 } 1038 1039 int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask) 1040 { 1041 u64 dma_addr_mask; 1042 1043 if (pdev == NULL) { 1044 dma_addr_mask = 0xffffffff; 1045 } else { 1046 struct iommu *iommu = pdev->dev.archdata.iommu; 1047 1048 dma_addr_mask = iommu->dma_addr_mask; 1049 1050 if (pdev->vendor == PCI_VENDOR_ID_AL && 1051 pdev->device == PCI_DEVICE_ID_AL_M5451 && 1052 device_mask == 0x7fffffff) { 1053 ali_sound_dma_hack(pdev, 1054 (dma_addr_mask & 0x80000000) != 0); 1055 return 1; 1056 } 1057 } 1058 1059 if (device_mask >= (1UL << 32UL)) 1060 return 0; 1061 1062 return (device_mask & dma_addr_mask) == dma_addr_mask; 1063 } 1064 1065 void pci_resource_to_user(const struct pci_dev *pdev, int bar, 1066 const struct resource *rp, resource_size_t *start, 1067 resource_size_t *end) 1068 { 1069 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 1070 unsigned long offset; 1071 1072 if (rp->flags & IORESOURCE_IO) 1073 offset = pbm->io_space.start; 1074 else 1075 offset = pbm->mem_space.start; 1076 1077 *start = rp->start - offset; 1078 *end = rp->end - offset; 1079 } 1080 1081 void pcibios_set_master(struct pci_dev *dev) 1082 { 1083 /* No special bus mastering setup handling */ 1084 } 1085 1086 static int __init pcibios_init(void) 1087 { 1088 pci_dfl_cache_line_size = 64 >> 2; 1089 return 0; 1090 } 1091 subsys_initcall(pcibios_init); 1092 1093 #ifdef CONFIG_SYSFS 1094 static void __devinit pci_bus_slot_names(struct device_node *node, 1095 struct pci_bus *bus) 1096 { 1097 const struct pci_slot_names { 1098 u32 slot_mask; 1099 char names[0]; 1100 } *prop; 1101 const char *sp; 1102 int len, i; 1103 u32 mask; 1104 1105 prop = of_get_property(node, "slot-names", &len); 1106 if (!prop) 1107 return; 1108 1109 mask = prop->slot_mask; 1110 sp = prop->names; 1111 1112 if (ofpci_verbose) 1113 printk("PCI: Making slots for [%s] mask[0x%02x]\n", 1114 node->full_name, mask); 1115 1116 i = 0; 1117 while (mask) { 1118 struct pci_slot *pci_slot; 1119 u32 this_bit = 1 << i; 1120 1121 if (!(mask & this_bit)) { 1122 i++; 1123 continue; 1124 } 1125 1126 if (ofpci_verbose) 1127 printk("PCI: Making slot [%s]\n", sp); 1128 1129 pci_slot = pci_create_slot(bus, i, sp, NULL); 1130 if (IS_ERR(pci_slot)) 1131 printk(KERN_ERR "PCI: pci_create_slot returned %ld\n", 1132 PTR_ERR(pci_slot)); 1133 1134 sp += strlen(sp) + 1; 1135 mask &= ~this_bit; 1136 i++; 1137 } 1138 } 1139 1140 static int __init of_pci_slot_init(void) 1141 { 1142 struct pci_bus *pbus = NULL; 1143 1144 while ((pbus = pci_find_next_bus(pbus)) != NULL) { 1145 struct device_node *node; 1146 1147 if (pbus->self) { 1148 /* PCI->PCI bridge */ 1149 node = pbus->self->dev.of_node; 1150 } else { 1151 struct pci_pbm_info *pbm = pbus->sysdata; 1152 1153 /* Host PCI controller */ 1154 node = pbm->op->dev.of_node; 1155 } 1156 1157 pci_bus_slot_names(node, pbus); 1158 } 1159 1160 return 0; 1161 } 1162 1163 module_init(of_pci_slot_init); 1164 #endif 1165