1 // SPDX-License-Identifier: GPL-2.0 2 /* pci.c: UltraSparc PCI controller support. 3 * 4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) 5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) 7 * 8 * OF tree based PCI bus probing taken from the PowerPC port 9 * with minor modifications, see there for credits. 10 */ 11 12 #include <linux/export.h> 13 #include <linux/kernel.h> 14 #include <linux/string.h> 15 #include <linux/sched.h> 16 #include <linux/capability.h> 17 #include <linux/errno.h> 18 #include <linux/pci.h> 19 #include <linux/msi.h> 20 #include <linux/irq.h> 21 #include <linux/init.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pgtable.h> 25 #include <linux/platform_device.h> 26 27 #include <linux/uaccess.h> 28 #include <asm/irq.h> 29 #include <asm/prom.h> 30 #include <asm/apb.h> 31 32 #include "pci_impl.h" 33 #include "kernel.h" 34 35 /* List of all PCI controllers found in the system. */ 36 struct pci_pbm_info *pci_pbm_root = NULL; 37 38 /* Each PBM found gets a unique index. */ 39 int pci_num_pbms = 0; 40 41 volatile int pci_poke_in_progress; 42 volatile int pci_poke_cpu = -1; 43 volatile int pci_poke_faulted; 44 45 static DEFINE_SPINLOCK(pci_poke_lock); 46 47 void pci_config_read8(u8 *addr, u8 *ret) 48 { 49 unsigned long flags; 50 u8 byte; 51 52 spin_lock_irqsave(&pci_poke_lock, flags); 53 pci_poke_cpu = smp_processor_id(); 54 pci_poke_in_progress = 1; 55 pci_poke_faulted = 0; 56 __asm__ __volatile__("membar #Sync\n\t" 57 "lduba [%1] %2, %0\n\t" 58 "membar #Sync" 59 : "=r" (byte) 60 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 61 : "memory"); 62 pci_poke_in_progress = 0; 63 pci_poke_cpu = -1; 64 if (!pci_poke_faulted) 65 *ret = byte; 66 spin_unlock_irqrestore(&pci_poke_lock, flags); 67 } 68 69 void pci_config_read16(u16 *addr, u16 *ret) 70 { 71 unsigned long flags; 72 u16 word; 73 74 spin_lock_irqsave(&pci_poke_lock, flags); 75 pci_poke_cpu = smp_processor_id(); 76 pci_poke_in_progress = 1; 77 pci_poke_faulted = 0; 78 __asm__ __volatile__("membar #Sync\n\t" 79 "lduha [%1] %2, %0\n\t" 80 "membar #Sync" 81 : "=r" (word) 82 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 83 : "memory"); 84 pci_poke_in_progress = 0; 85 pci_poke_cpu = -1; 86 if (!pci_poke_faulted) 87 *ret = word; 88 spin_unlock_irqrestore(&pci_poke_lock, flags); 89 } 90 91 void pci_config_read32(u32 *addr, u32 *ret) 92 { 93 unsigned long flags; 94 u32 dword; 95 96 spin_lock_irqsave(&pci_poke_lock, flags); 97 pci_poke_cpu = smp_processor_id(); 98 pci_poke_in_progress = 1; 99 pci_poke_faulted = 0; 100 __asm__ __volatile__("membar #Sync\n\t" 101 "lduwa [%1] %2, %0\n\t" 102 "membar #Sync" 103 : "=r" (dword) 104 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 105 : "memory"); 106 pci_poke_in_progress = 0; 107 pci_poke_cpu = -1; 108 if (!pci_poke_faulted) 109 *ret = dword; 110 spin_unlock_irqrestore(&pci_poke_lock, flags); 111 } 112 113 void pci_config_write8(u8 *addr, u8 val) 114 { 115 unsigned long flags; 116 117 spin_lock_irqsave(&pci_poke_lock, flags); 118 pci_poke_cpu = smp_processor_id(); 119 pci_poke_in_progress = 1; 120 pci_poke_faulted = 0; 121 __asm__ __volatile__("membar #Sync\n\t" 122 "stba %0, [%1] %2\n\t" 123 "membar #Sync" 124 : /* no outputs */ 125 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 126 : "memory"); 127 pci_poke_in_progress = 0; 128 pci_poke_cpu = -1; 129 spin_unlock_irqrestore(&pci_poke_lock, flags); 130 } 131 132 void pci_config_write16(u16 *addr, u16 val) 133 { 134 unsigned long flags; 135 136 spin_lock_irqsave(&pci_poke_lock, flags); 137 pci_poke_cpu = smp_processor_id(); 138 pci_poke_in_progress = 1; 139 pci_poke_faulted = 0; 140 __asm__ __volatile__("membar #Sync\n\t" 141 "stha %0, [%1] %2\n\t" 142 "membar #Sync" 143 : /* no outputs */ 144 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 145 : "memory"); 146 pci_poke_in_progress = 0; 147 pci_poke_cpu = -1; 148 spin_unlock_irqrestore(&pci_poke_lock, flags); 149 } 150 151 void pci_config_write32(u32 *addr, u32 val) 152 { 153 unsigned long flags; 154 155 spin_lock_irqsave(&pci_poke_lock, flags); 156 pci_poke_cpu = smp_processor_id(); 157 pci_poke_in_progress = 1; 158 pci_poke_faulted = 0; 159 __asm__ __volatile__("membar #Sync\n\t" 160 "stwa %0, [%1] %2\n\t" 161 "membar #Sync" 162 : /* no outputs */ 163 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 164 : "memory"); 165 pci_poke_in_progress = 0; 166 pci_poke_cpu = -1; 167 spin_unlock_irqrestore(&pci_poke_lock, flags); 168 } 169 170 static int ofpci_verbose; 171 172 static int __init ofpci_debug(char *str) 173 { 174 int val = 0; 175 176 get_option(&str, &val); 177 if (val) 178 ofpci_verbose = 1; 179 return 1; 180 } 181 182 __setup("ofpci_debug=", ofpci_debug); 183 184 static void of_fixup_pci_pref(struct pci_dev *dev, int index, 185 struct resource *res) 186 { 187 struct pci_bus_region region; 188 189 if (!(res->flags & IORESOURCE_MEM_64)) 190 return; 191 192 if (!resource_size(res)) 193 return; 194 195 pcibios_resource_to_bus(dev->bus, ®ion, res); 196 if (region.end <= ~((u32)0)) 197 return; 198 199 if (!(res->flags & IORESOURCE_PREFETCH)) { 200 res->flags |= IORESOURCE_PREFETCH; 201 pci_info(dev, "reg 0x%x: fixup: pref added to 64-bit resource\n", 202 index); 203 } 204 } 205 206 static unsigned long pci_parse_of_flags(u32 addr0) 207 { 208 unsigned long flags = 0; 209 210 if (addr0 & 0x02000000) { 211 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; 212 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; 213 if (addr0 & 0x01000000) 214 flags |= IORESOURCE_MEM_64 215 | PCI_BASE_ADDRESS_MEM_TYPE_64; 216 if (addr0 & 0x40000000) 217 flags |= IORESOURCE_PREFETCH 218 | PCI_BASE_ADDRESS_MEM_PREFETCH; 219 } else if (addr0 & 0x01000000) 220 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; 221 return flags; 222 } 223 224 /* The of_device layer has translated all of the assigned-address properties 225 * into physical address resources, we only have to figure out the register 226 * mapping. 227 */ 228 static void pci_parse_of_addrs(struct platform_device *op, 229 struct device_node *node, 230 struct pci_dev *dev) 231 { 232 struct resource *op_res; 233 const u32 *addrs; 234 int proplen; 235 236 addrs = of_get_property(node, "assigned-addresses", &proplen); 237 if (!addrs) 238 return; 239 if (ofpci_verbose) 240 pci_info(dev, " parse addresses (%d bytes) @ %p\n", 241 proplen, addrs); 242 op_res = &op->resource[0]; 243 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { 244 struct resource *res; 245 unsigned long flags; 246 int i; 247 248 flags = pci_parse_of_flags(addrs[0]); 249 if (!flags) 250 continue; 251 i = addrs[0] & 0xff; 252 if (ofpci_verbose) 253 pci_info(dev, " start: %llx, end: %llx, i: %x\n", 254 op_res->start, op_res->end, i); 255 256 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { 257 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; 258 } else if (i == dev->rom_base_reg) { 259 res = &dev->resource[PCI_ROM_RESOURCE]; 260 flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 261 } else { 262 pci_err(dev, "bad cfg reg num 0x%x\n", i); 263 continue; 264 } 265 res->start = op_res->start; 266 res->end = op_res->end; 267 res->flags = flags; 268 res->name = pci_name(dev); 269 of_fixup_pci_pref(dev, i, res); 270 271 pci_info(dev, "reg 0x%x: %pR\n", i, res); 272 } 273 } 274 275 static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu, 276 void *stc, void *host_controller, 277 struct platform_device *op, 278 int numa_node) 279 { 280 sd->iommu = iommu; 281 sd->stc = stc; 282 sd->host_controller = host_controller; 283 sd->op = op; 284 sd->numa_node = numa_node; 285 } 286 287 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, 288 struct device_node *node, 289 struct pci_bus *bus, int devfn) 290 { 291 struct dev_archdata *sd; 292 struct platform_device *op; 293 struct pci_dev *dev; 294 u32 class; 295 296 dev = pci_alloc_dev(bus); 297 if (!dev) 298 return NULL; 299 300 op = of_find_device_by_node(node); 301 sd = &dev->dev.archdata; 302 pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op, 303 pbm->numa_node); 304 sd = &op->dev.archdata; 305 sd->iommu = pbm->iommu; 306 sd->stc = &pbm->stc; 307 sd->numa_node = pbm->numa_node; 308 309 if (of_node_name_eq(node, "ebus")) 310 of_propagate_archdata(op); 311 312 if (ofpci_verbose) 313 pci_info(bus," create device, devfn: %x, type: %s\n", 314 devfn, of_node_get_device_type(node)); 315 316 dev->sysdata = node; 317 dev->dev.parent = bus->bridge; 318 dev->dev.bus = &pci_bus_type; 319 dev->dev.of_node = of_node_get(node); 320 dev->devfn = devfn; 321 dev->multifunction = 0; /* maybe a lie? */ 322 set_pcie_port_type(dev); 323 324 pci_dev_assign_slot(dev); 325 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); 326 dev->device = of_getintprop_default(node, "device-id", 0xffff); 327 dev->subsystem_vendor = 328 of_getintprop_default(node, "subsystem-vendor-id", 0); 329 dev->subsystem_device = 330 of_getintprop_default(node, "subsystem-id", 0); 331 332 dev->cfg_size = pci_cfg_space_size(dev); 333 334 /* We can't actually use the firmware value, we have 335 * to read what is in the register right now. One 336 * reason is that in the case of IDE interfaces the 337 * firmware can sample the value before the IDE 338 * interface is programmed into native mode. 339 */ 340 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 341 dev->class = class >> 8; 342 dev->revision = class & 0xff; 343 344 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), 345 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 346 347 /* I have seen IDE devices which will not respond to 348 * the bmdma simplex check reads if bus mastering is 349 * disabled. 350 */ 351 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) 352 pci_set_master(dev); 353 354 dev->current_state = PCI_UNKNOWN; /* unknown power state */ 355 dev->error_state = pci_channel_io_normal; 356 dev->dma_mask = 0xffffffff; 357 358 /* 359 * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit 360 * if MSI (rather than MSI-X) capability does not have 361 * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. 362 */ 363 dev->msi_addr_mask = DMA_BIT_MASK(64); 364 365 if (of_node_name_eq(node, "pci")) { 366 /* a PCI-PCI bridge */ 367 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; 368 dev->rom_base_reg = PCI_ROM_ADDRESS1; 369 } else if (of_node_is_type(node, "cardbus")) { 370 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; 371 } else { 372 dev->hdr_type = PCI_HEADER_TYPE_NORMAL; 373 dev->rom_base_reg = PCI_ROM_ADDRESS; 374 375 dev->irq = sd->op->archdata.irqs[0]; 376 if (dev->irq == 0xffffffff) 377 dev->irq = PCI_IRQ_NONE; 378 } 379 380 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 381 dev->vendor, dev->device, dev->hdr_type, dev->class); 382 383 pci_parse_of_addrs(sd->op, node, dev); 384 385 if (ofpci_verbose) 386 pci_info(dev, " adding to system ...\n"); 387 388 pci_device_add(dev, bus); 389 390 return dev; 391 } 392 393 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) 394 { 395 u32 idx, first, last; 396 397 first = 8; 398 last = 0; 399 for (idx = 0; idx < 8; idx++) { 400 if ((map & (1 << idx)) != 0) { 401 if (first > idx) 402 first = idx; 403 if (last < idx) 404 last = idx; 405 } 406 } 407 408 *first_p = first; 409 *last_p = last; 410 } 411 412 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack 413 * a proper 'ranges' property. 414 */ 415 static void apb_fake_ranges(struct pci_dev *dev, 416 struct pci_bus *bus, 417 struct pci_pbm_info *pbm) 418 { 419 struct pci_bus_region region; 420 struct resource *res; 421 u32 first, last; 422 u8 map; 423 424 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); 425 apb_calc_first_last(map, &first, &last); 426 res = bus->resource[0]; 427 res->flags = IORESOURCE_IO; 428 region.start = (first << 21); 429 region.end = (last << 21) + ((1 << 21) - 1); 430 pcibios_bus_to_resource(dev->bus, res, ®ion); 431 432 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); 433 apb_calc_first_last(map, &first, &last); 434 res = bus->resource[1]; 435 res->flags = IORESOURCE_MEM; 436 region.start = (first << 29); 437 region.end = (last << 29) + ((1 << 29) - 1); 438 pcibios_bus_to_resource(dev->bus, res, ®ion); 439 } 440 441 static void pci_of_scan_bus(struct pci_pbm_info *pbm, 442 struct device_node *node, 443 struct pci_bus *bus); 444 445 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) 446 447 static void of_scan_pci_bridge(struct pci_pbm_info *pbm, 448 struct device_node *node, 449 struct pci_dev *dev) 450 { 451 struct pci_bus *bus; 452 const u32 *busrange, *ranges; 453 int len, i, simba; 454 struct pci_bus_region region; 455 struct resource *res; 456 unsigned int flags; 457 u64 size; 458 459 if (ofpci_verbose) 460 pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node); 461 462 /* parse bus-range property */ 463 busrange = of_get_property(node, "bus-range", &len); 464 if (busrange == NULL || len != 8) { 465 pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n", 466 node); 467 return; 468 } 469 470 if (ofpci_verbose) 471 pci_info(dev, " Bridge bus range [%u --> %u]\n", 472 busrange[0], busrange[1]); 473 474 ranges = of_get_property(node, "ranges", &len); 475 simba = 0; 476 if (ranges == NULL) { 477 const char *model = of_get_property(node, "model", NULL); 478 if (model && !strcmp(model, "SUNW,simba")) 479 simba = 1; 480 } 481 482 bus = pci_add_new_bus(dev->bus, dev, busrange[0]); 483 if (!bus) { 484 pci_err(dev, "Failed to create pci bus for %pOF\n", 485 node); 486 return; 487 } 488 489 bus->primary = dev->bus->number; 490 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]); 491 bus->bridge_ctl = 0; 492 493 if (ofpci_verbose) 494 pci_info(dev, " Bridge ranges[%p] simba[%d]\n", 495 ranges, simba); 496 497 /* parse ranges property, or cook one up by hand for Simba */ 498 /* PCI #address-cells == 3 and #size-cells == 2 always */ 499 res = &dev->resource[PCI_BRIDGE_RESOURCES]; 500 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { 501 res->flags = 0; 502 bus->resource[i] = res; 503 ++res; 504 } 505 if (simba) { 506 apb_fake_ranges(dev, bus, pbm); 507 goto after_ranges; 508 } else if (ranges == NULL) { 509 pci_read_bridge_bases(bus); 510 goto after_ranges; 511 } 512 i = 1; 513 for (; len >= 32; len -= 32, ranges += 8) { 514 u64 start; 515 516 if (ofpci_verbose) 517 pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:" 518 "%08x:%08x]\n", 519 ranges[0], ranges[1], ranges[2], ranges[3], 520 ranges[4], ranges[5], ranges[6], ranges[7]); 521 522 flags = pci_parse_of_flags(ranges[0]); 523 size = GET_64BIT(ranges, 6); 524 if (flags == 0 || size == 0) 525 continue; 526 527 /* On PCI-Express systems, PCI bridges that have no devices downstream 528 * have a bogus size value where the first 32-bit cell is 0xffffffff. 529 * This results in a bogus range where start + size overflows. 530 * 531 * Just skip these otherwise the kernel will complain when the resource 532 * tries to be claimed. 533 */ 534 if (size >> 32 == 0xffffffff) 535 continue; 536 537 if (flags & IORESOURCE_IO) { 538 res = bus->resource[0]; 539 if (res->flags) { 540 pci_err(dev, "ignoring extra I/O range" 541 " for bridge %pOF\n", node); 542 continue; 543 } 544 } else { 545 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { 546 pci_err(dev, "too many memory ranges" 547 " for bridge %pOF\n", node); 548 continue; 549 } 550 res = bus->resource[i]; 551 ++i; 552 } 553 554 res->flags = flags; 555 region.start = start = GET_64BIT(ranges, 1); 556 region.end = region.start + size - 1; 557 558 if (ofpci_verbose) 559 pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n", 560 flags, start, size); 561 562 pcibios_bus_to_resource(dev->bus, res, ®ion); 563 } 564 after_ranges: 565 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 566 bus->number); 567 if (ofpci_verbose) 568 pci_info(dev, " bus name: %s\n", bus->name); 569 570 pci_of_scan_bus(pbm, node, bus); 571 } 572 573 static void pci_of_scan_bus(struct pci_pbm_info *pbm, 574 struct device_node *node, 575 struct pci_bus *bus) 576 { 577 struct device_node *child; 578 const u32 *reg; 579 int reglen, devfn, prev_devfn; 580 struct pci_dev *dev; 581 582 if (ofpci_verbose) 583 pci_info(bus, "scan_bus[%pOF] bus no %d\n", 584 node, bus->number); 585 586 prev_devfn = -1; 587 for_each_child_of_node(node, child) { 588 if (ofpci_verbose) 589 pci_info(bus, " * %pOF\n", child); 590 reg = of_get_property(child, "reg", ®len); 591 if (reg == NULL || reglen < 20) 592 continue; 593 594 devfn = (reg[0] >> 8) & 0xff; 595 596 /* This is a workaround for some device trees 597 * which list PCI devices twice. On the V100 598 * for example, device number 3 is listed twice. 599 * Once as "pm" and once again as "lomp". 600 */ 601 if (devfn == prev_devfn) 602 continue; 603 prev_devfn = devfn; 604 605 /* create a new pci_dev for this device */ 606 dev = of_create_pci_dev(pbm, child, bus, devfn); 607 if (!dev) 608 continue; 609 if (ofpci_verbose) 610 pci_info(dev, "dev header type: %x\n", dev->hdr_type); 611 612 if (pci_is_bridge(dev)) 613 of_scan_pci_bridge(pbm, child, dev); 614 } 615 } 616 617 static ssize_t 618 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) 619 { 620 struct pci_dev *pdev; 621 struct device_node *dp; 622 623 pdev = to_pci_dev(dev); 624 dp = pdev->dev.of_node; 625 626 return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp); 627 } 628 629 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); 630 631 static void pci_bus_register_of_sysfs(struct pci_bus *bus) 632 { 633 struct pci_dev *dev; 634 struct pci_bus *child_bus; 635 int err; 636 637 list_for_each_entry(dev, &bus->devices, bus_list) { 638 /* we don't really care if we can create this file or 639 * not, but we need to assign the result of the call 640 * or the world will fall under alien invasion and 641 * everybody will be frozen on a spaceship ready to be 642 * eaten on alpha centauri by some green and jelly 643 * humanoid. 644 */ 645 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); 646 (void) err; 647 } 648 list_for_each_entry(child_bus, &bus->children, node) 649 pci_bus_register_of_sysfs(child_bus); 650 } 651 652 static void pci_claim_legacy_resources(struct pci_dev *dev) 653 { 654 struct pci_bus_region region; 655 struct resource *p, *root, *conflict; 656 657 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) 658 return; 659 660 p = kzalloc_obj(*p); 661 if (!p) 662 return; 663 664 p->name = "Video RAM area"; 665 p->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 666 667 region.start = 0xa0000UL; 668 region.end = region.start + 0x1ffffUL; 669 pcibios_bus_to_resource(dev->bus, p, ®ion); 670 671 root = pci_find_parent_resource(dev, p); 672 if (!root) { 673 pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p); 674 goto err; 675 } 676 677 conflict = request_resource_conflict(root, p); 678 if (conflict) { 679 pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n", 680 p, conflict->name, conflict); 681 goto err; 682 } 683 684 pci_info(dev, "VGA legacy framebuffer %pR\n", p); 685 return; 686 687 err: 688 kfree(p); 689 } 690 691 static void pci_claim_bus_resources(struct pci_bus *bus) 692 { 693 struct pci_bus *child_bus; 694 struct pci_dev *dev; 695 696 list_for_each_entry(dev, &bus->devices, bus_list) { 697 struct resource *r; 698 int i; 699 700 pci_dev_for_each_resource(dev, r, i) { 701 if (r->parent || !r->start || !r->flags) 702 continue; 703 704 if (ofpci_verbose) 705 pci_info(dev, "Claiming Resource %d: %pR\n", 706 i, r); 707 708 pci_claim_resource(dev, i); 709 } 710 711 pci_claim_legacy_resources(dev); 712 } 713 714 list_for_each_entry(child_bus, &bus->children, node) 715 pci_claim_bus_resources(child_bus); 716 } 717 718 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm, 719 struct device *parent) 720 { 721 LIST_HEAD(resources); 722 struct device_node *node = pbm->op->dev.of_node; 723 struct pci_bus *bus; 724 725 printk("PCI: Scanning PBM %pOF\n", node); 726 727 pci_add_resource_offset(&resources, &pbm->io_space, 728 pbm->io_offset); 729 pci_add_resource_offset(&resources, &pbm->mem_space, 730 pbm->mem_offset); 731 if (pbm->mem64_space.flags) 732 pci_add_resource_offset(&resources, &pbm->mem64_space, 733 pbm->mem64_offset); 734 pbm->busn.start = pbm->pci_first_busno; 735 pbm->busn.end = pbm->pci_last_busno; 736 pbm->busn.flags = IORESOURCE_BUS; 737 pci_add_resource(&resources, &pbm->busn); 738 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops, 739 pbm, &resources); 740 if (!bus) { 741 printk(KERN_ERR "Failed to create bus for %pOF\n", node); 742 pci_free_resource_list(&resources); 743 return NULL; 744 } 745 746 pci_of_scan_bus(pbm, node, bus); 747 pci_bus_register_of_sysfs(bus); 748 749 pci_claim_bus_resources(bus); 750 751 pci_bus_add_devices(bus); 752 return bus; 753 } 754 755 /* Platform support for /proc/bus/pci/X/Y mmap()s. */ 756 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) 757 { 758 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 759 resource_size_t ioaddr = pci_resource_start(pdev, bar); 760 761 if (!pbm) 762 return -EINVAL; 763 764 vma->vm_pgoff += (ioaddr + pbm->io_space.start) >> PAGE_SHIFT; 765 766 return 0; 767 } 768 769 #ifdef CONFIG_NUMA 770 int pcibus_to_node(struct pci_bus *pbus) 771 { 772 struct pci_pbm_info *pbm = pbus->sysdata; 773 774 return pbm->numa_node; 775 } 776 EXPORT_SYMBOL(pcibus_to_node); 777 #endif 778 779 /* Return the domain number for this pci bus */ 780 781 int pci_domain_nr(struct pci_bus *pbus) 782 { 783 struct pci_pbm_info *pbm = pbus->sysdata; 784 int ret; 785 786 if (!pbm) { 787 ret = -ENXIO; 788 } else { 789 ret = pbm->index; 790 } 791 792 return ret; 793 } 794 EXPORT_SYMBOL(pci_domain_nr); 795 796 #ifdef CONFIG_PCI_MSI 797 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 798 { 799 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 800 unsigned int irq; 801 802 if (!pbm->setup_msi_irq) 803 return -EINVAL; 804 805 return pbm->setup_msi_irq(&irq, pdev, desc); 806 } 807 808 void arch_teardown_msi_irq(unsigned int irq) 809 { 810 struct msi_desc *entry = irq_get_msi_desc(irq); 811 struct pci_dev *pdev = msi_desc_to_pci_dev(entry); 812 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 813 814 if (pbm->teardown_msi_irq) 815 pbm->teardown_msi_irq(irq, pdev); 816 } 817 #endif /* !(CONFIG_PCI_MSI) */ 818 819 /* ALI sound chips generate 31-bits of DMA, a special register 820 * determines what bit 31 is emitted as. 821 */ 822 int ali_sound_dma_hack(struct device *dev, u64 device_mask) 823 { 824 struct iommu *iommu = dev->archdata.iommu; 825 struct pci_dev *ali_isa_bridge; 826 u8 val; 827 828 if (!dev_is_pci(dev)) 829 return 0; 830 831 if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL || 832 to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 || 833 device_mask != 0x7fffffff) 834 return 0; 835 836 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, 837 PCI_DEVICE_ID_AL_M1533, 838 NULL); 839 840 pci_read_config_byte(ali_isa_bridge, 0x7e, &val); 841 if (iommu->dma_addr_mask & 0x80000000) 842 val |= 0x01; 843 else 844 val &= ~0x01; 845 pci_write_config_byte(ali_isa_bridge, 0x7e, val); 846 pci_dev_put(ali_isa_bridge); 847 return 1; 848 } 849 850 void pci_resource_to_user(const struct pci_dev *pdev, int bar, 851 const struct resource *rp, resource_size_t *start, 852 resource_size_t *end) 853 { 854 struct pci_bus_region region; 855 856 /* 857 * "User" addresses are shown in /sys/devices/pci.../.../resource 858 * and /proc/bus/pci/devices and used as mmap offsets for 859 * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()). 860 * 861 * On sparc, these are PCI bus addresses, i.e., raw BAR values. 862 */ 863 pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp); 864 *start = region.start; 865 *end = region.end; 866 } 867 868 void pcibios_set_master(struct pci_dev *dev) 869 { 870 /* No special bus mastering setup handling */ 871 } 872 873 #ifdef CONFIG_PCI_IOV 874 int pcibios_device_add(struct pci_dev *dev) 875 { 876 struct pci_dev *pdev; 877 878 /* Add sriov arch specific initialization here. 879 * Copy dev_archdata from PF to VF 880 */ 881 if (dev->is_virtfn) { 882 struct dev_archdata *psd; 883 884 pdev = dev->physfn; 885 psd = &pdev->dev.archdata; 886 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu, 887 psd->stc, psd->host_controller, NULL, 888 psd->numa_node); 889 } 890 return 0; 891 } 892 #endif /* CONFIG_PCI_IOV */ 893 894 static int __init pcibios_init(void) 895 { 896 pci_dfl_cache_line_size = 64 >> 2; 897 return 0; 898 } 899 subsys_initcall(pcibios_init); 900 901 #ifdef CONFIG_SYSFS 902 903 #define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */ 904 905 static void pcie_bus_slot_names(struct pci_bus *pbus) 906 { 907 struct pci_dev *pdev; 908 struct pci_bus *bus; 909 910 list_for_each_entry(pdev, &pbus->devices, bus_list) { 911 char name[SLOT_NAME_SIZE]; 912 struct pci_slot *pci_slot; 913 const u32 *slot_num; 914 int len; 915 916 slot_num = of_get_property(pdev->dev.of_node, 917 "physical-slot#", &len); 918 919 if (slot_num == NULL || len != 4) 920 continue; 921 922 snprintf(name, sizeof(name), "%u", slot_num[0]); 923 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL); 924 925 if (IS_ERR(pci_slot)) 926 pr_err("PCI: pci_create_slot returned %ld.\n", 927 PTR_ERR(pci_slot)); 928 } 929 930 list_for_each_entry(bus, &pbus->children, node) 931 pcie_bus_slot_names(bus); 932 } 933 934 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus) 935 { 936 const struct pci_slot_names { 937 u32 slot_mask; 938 char names[]; 939 } *prop; 940 const char *sp; 941 int len, i; 942 u32 mask; 943 944 prop = of_get_property(node, "slot-names", &len); 945 if (!prop) 946 return; 947 948 mask = prop->slot_mask; 949 sp = prop->names; 950 951 if (ofpci_verbose) 952 pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n", 953 node, mask); 954 955 i = 0; 956 while (mask) { 957 struct pci_slot *pci_slot; 958 u32 this_bit = 1 << i; 959 960 if (!(mask & this_bit)) { 961 i++; 962 continue; 963 } 964 965 if (ofpci_verbose) 966 pci_info(bus, "Making slot [%s]\n", sp); 967 968 pci_slot = pci_create_slot(bus, i, sp, NULL); 969 if (IS_ERR(pci_slot)) 970 pci_err(bus, "pci_create_slot returned %ld\n", 971 PTR_ERR(pci_slot)); 972 973 sp += strlen(sp) + 1; 974 mask &= ~this_bit; 975 i++; 976 } 977 } 978 979 static int __init of_pci_slot_init(void) 980 { 981 struct pci_bus *pbus = NULL; 982 983 while ((pbus = pci_find_next_bus(pbus)) != NULL) { 984 struct device_node *node; 985 struct pci_dev *pdev; 986 987 pdev = list_first_entry(&pbus->devices, struct pci_dev, 988 bus_list); 989 990 if (pdev && pci_is_pcie(pdev)) { 991 pcie_bus_slot_names(pbus); 992 } else { 993 994 if (pbus->self) { 995 996 /* PCI->PCI bridge */ 997 node = pbus->self->dev.of_node; 998 999 } else { 1000 struct pci_pbm_info *pbm = pbus->sysdata; 1001 1002 /* Host PCI controller */ 1003 node = pbm->op->dev.of_node; 1004 } 1005 1006 pci_bus_slot_names(node, pbus); 1007 } 1008 } 1009 1010 return 0; 1011 } 1012 device_initcall(of_pci_slot_init); 1013 #endif 1014