1 // SPDX-License-Identifier: GPL-2.0 2 /* irq.c: UltraSparc IRQ handling/init/registry. 3 * 4 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) 5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) 7 */ 8 9 #include <linux/sched.h> 10 #include <linux/linkage.h> 11 #include <linux/ptrace.h> 12 #include <linux/errno.h> 13 #include <linux/kernel_stat.h> 14 #include <linux/signal.h> 15 #include <linux/mm.h> 16 #include <linux/interrupt.h> 17 #include <linux/slab.h> 18 #include <linux/random.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/proc_fs.h> 22 #include <linux/seq_file.h> 23 #include <linux/ftrace.h> 24 #include <linux/irq.h> 25 26 #include <asm/ptrace.h> 27 #include <asm/processor.h> 28 #include <linux/atomic.h> 29 #include <asm/irq.h> 30 #include <asm/io.h> 31 #include <asm/iommu.h> 32 #include <asm/upa.h> 33 #include <asm/oplib.h> 34 #include <asm/prom.h> 35 #include <asm/timer.h> 36 #include <asm/smp.h> 37 #include <asm/starfire.h> 38 #include <linux/uaccess.h> 39 #include <asm/cache.h> 40 #include <asm/cpudata.h> 41 #include <asm/auxio.h> 42 #include <asm/head.h> 43 #include <asm/hypervisor.h> 44 #include <asm/cacheflush.h> 45 #include <asm/softirq_stack.h> 46 47 #include "entry.h" 48 #include "cpumap.h" 49 #include "kstack.h" 50 51 struct ino_bucket *ivector_table; 52 unsigned long ivector_table_pa; 53 54 /* On several sun4u processors, it is illegal to mix bypass and 55 * non-bypass accesses. Therefore we access all INO buckets 56 * using bypass accesses only. 57 */ 58 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa) 59 { 60 unsigned long ret; 61 62 __asm__ __volatile__("ldxa [%1] %2, %0" 63 : "=&r" (ret) 64 : "r" (bucket_pa + 65 offsetof(struct ino_bucket, 66 __irq_chain_pa)), 67 "i" (ASI_PHYS_USE_EC)); 68 69 return ret; 70 } 71 72 static void bucket_clear_chain_pa(unsigned long bucket_pa) 73 { 74 __asm__ __volatile__("stxa %%g0, [%0] %1" 75 : /* no outputs */ 76 : "r" (bucket_pa + 77 offsetof(struct ino_bucket, 78 __irq_chain_pa)), 79 "i" (ASI_PHYS_USE_EC)); 80 } 81 82 static unsigned int bucket_get_irq(unsigned long bucket_pa) 83 { 84 unsigned int ret; 85 86 __asm__ __volatile__("lduwa [%1] %2, %0" 87 : "=&r" (ret) 88 : "r" (bucket_pa + 89 offsetof(struct ino_bucket, 90 __irq)), 91 "i" (ASI_PHYS_USE_EC)); 92 93 return ret; 94 } 95 96 static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq) 97 { 98 __asm__ __volatile__("stwa %0, [%1] %2" 99 : /* no outputs */ 100 : "r" (irq), 101 "r" (bucket_pa + 102 offsetof(struct ino_bucket, 103 __irq)), 104 "i" (ASI_PHYS_USE_EC)); 105 } 106 107 #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa) 108 109 static unsigned long hvirq_major __initdata; 110 static int __init early_hvirq_major(char *p) 111 { 112 int rc = kstrtoul(p, 10, &hvirq_major); 113 114 return rc; 115 } 116 early_param("hvirq", early_hvirq_major); 117 118 static int hv_irq_version; 119 120 /* Major version 2.0 of HV_GRP_INTR added support for the VIRQ cookie 121 * based interfaces, but: 122 * 123 * 1) Several OSs, Solaris and Linux included, use them even when only 124 * negotiating version 1.0 (or failing to negotiate at all). So the 125 * hypervisor has a workaround that provides the VIRQ interfaces even 126 * when only verion 1.0 of the API is in use. 127 * 128 * 2) Second, and more importantly, with major version 2.0 these VIRQ 129 * interfaces only were actually hooked up for LDC interrupts, even 130 * though the Hypervisor specification clearly stated: 131 * 132 * The new interrupt API functions will be available to a guest 133 * when it negotiates version 2.0 in the interrupt API group 0x2. When 134 * a guest negotiates version 2.0, all interrupt sources will only 135 * support using the cookie interface, and any attempt to use the 136 * version 1.0 interrupt APIs numbered 0xa0 to 0xa6 will result in the 137 * ENOTSUPPORTED error being returned. 138 * 139 * with an emphasis on "all interrupt sources". 140 * 141 * To correct this, major version 3.0 was created which does actually 142 * support VIRQs for all interrupt sources (not just LDC devices). So 143 * if we want to move completely over the cookie based VIRQs we must 144 * negotiate major version 3.0 or later of HV_GRP_INTR. 145 */ 146 static bool sun4v_cookie_only_virqs(void) 147 { 148 if (hv_irq_version >= 3) 149 return true; 150 return false; 151 } 152 153 static void __init irq_init_hv(void) 154 { 155 unsigned long hv_error, major, minor = 0; 156 157 if (tlb_type != hypervisor) 158 return; 159 160 if (hvirq_major) 161 major = hvirq_major; 162 else 163 major = 3; 164 165 hv_error = sun4v_hvapi_register(HV_GRP_INTR, major, &minor); 166 if (!hv_error) 167 hv_irq_version = major; 168 else 169 hv_irq_version = 1; 170 171 pr_info("SUN4V: Using IRQ API major %d, cookie only virqs %s\n", 172 hv_irq_version, 173 sun4v_cookie_only_virqs() ? "enabled" : "disabled"); 174 } 175 176 /* This function is for the timer interrupt.*/ 177 int __init arch_probe_nr_irqs(void) 178 { 179 return 1; 180 } 181 182 #define DEFAULT_NUM_IVECS (0xfffU) 183 static unsigned int nr_ivec = DEFAULT_NUM_IVECS; 184 #define NUM_IVECS (nr_ivec) 185 186 static unsigned int __init size_nr_ivec(void) 187 { 188 if (tlb_type == hypervisor) { 189 switch (sun4v_chip_type) { 190 /* Athena's devhandle|devino is large.*/ 191 case SUN4V_CHIP_SPARC64X: 192 nr_ivec = 0xffff; 193 break; 194 } 195 } 196 return nr_ivec; 197 } 198 199 struct irq_handler_data { 200 union { 201 struct { 202 unsigned int dev_handle; 203 unsigned int dev_ino; 204 }; 205 unsigned long sysino; 206 }; 207 struct ino_bucket bucket; 208 unsigned long iclr; 209 unsigned long imap; 210 }; 211 212 static inline unsigned int irq_data_to_handle(struct irq_data *data) 213 { 214 struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data); 215 216 return ihd->dev_handle; 217 } 218 219 static inline unsigned int irq_data_to_ino(struct irq_data *data) 220 { 221 struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data); 222 223 return ihd->dev_ino; 224 } 225 226 static inline unsigned long irq_data_to_sysino(struct irq_data *data) 227 { 228 struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data); 229 230 return ihd->sysino; 231 } 232 233 void irq_free(unsigned int irq) 234 { 235 void *data = irq_get_handler_data(irq); 236 237 kfree(data); 238 irq_set_handler_data(irq, NULL); 239 irq_free_descs(irq, 1); 240 } 241 242 unsigned int irq_alloc(unsigned int dev_handle, unsigned int dev_ino) 243 { 244 int irq; 245 246 irq = __irq_alloc_descs(-1, 1, 1, numa_node_id(), NULL, NULL); 247 if (irq <= 0) 248 goto out; 249 250 return irq; 251 out: 252 return 0; 253 } 254 255 static unsigned int cookie_exists(u32 devhandle, unsigned int devino) 256 { 257 unsigned long hv_err, cookie; 258 struct ino_bucket *bucket; 259 unsigned int irq = 0U; 260 261 hv_err = sun4v_vintr_get_cookie(devhandle, devino, &cookie); 262 if (hv_err) { 263 pr_err("HV get cookie failed hv_err = %ld\n", hv_err); 264 goto out; 265 } 266 267 if (cookie & ((1UL << 63UL))) { 268 cookie = ~cookie; 269 bucket = (struct ino_bucket *) __va(cookie); 270 irq = bucket->__irq; 271 } 272 out: 273 return irq; 274 } 275 276 static unsigned int sysino_exists(u32 devhandle, unsigned int devino) 277 { 278 unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); 279 struct ino_bucket *bucket; 280 unsigned int irq; 281 282 bucket = &ivector_table[sysino]; 283 irq = bucket_get_irq(__pa(bucket)); 284 285 return irq; 286 } 287 288 void ack_bad_irq(unsigned int irq) 289 { 290 pr_crit("BAD IRQ ack %d\n", irq); 291 } 292 293 void irq_install_pre_handler(int irq, 294 void (*func)(unsigned int, void *, void *), 295 void *arg1, void *arg2) 296 { 297 pr_warn("IRQ pre handler NOT supported.\n"); 298 } 299 300 /* 301 * /proc/interrupts printing: 302 */ 303 int arch_show_interrupts(struct seq_file *p, int prec) 304 { 305 int j; 306 307 seq_printf(p, "NMI: "); 308 for_each_online_cpu(j) 309 seq_printf(p, "%10u ", cpu_data(j).__nmi_count); 310 seq_printf(p, " Non-maskable interrupts\n"); 311 return 0; 312 } 313 314 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) 315 { 316 unsigned int tid; 317 318 if (this_is_starfire) { 319 tid = starfire_translate(imap, cpuid); 320 tid <<= IMAP_TID_SHIFT; 321 tid &= IMAP_TID_UPA; 322 } else { 323 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 324 unsigned long ver; 325 326 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 327 if ((ver >> 32UL) == __JALAPENO_ID || 328 (ver >> 32UL) == __SERRANO_ID) { 329 tid = cpuid << IMAP_TID_SHIFT; 330 tid &= IMAP_TID_JBUS; 331 } else { 332 unsigned int a = cpuid & 0x1f; 333 unsigned int n = (cpuid >> 5) & 0x1f; 334 335 tid = ((a << IMAP_AID_SHIFT) | 336 (n << IMAP_NID_SHIFT)); 337 tid &= (IMAP_AID_SAFARI | 338 IMAP_NID_SAFARI); 339 } 340 } else { 341 tid = cpuid << IMAP_TID_SHIFT; 342 tid &= IMAP_TID_UPA; 343 } 344 } 345 346 return tid; 347 } 348 349 #ifdef CONFIG_SMP 350 static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity) 351 { 352 int cpuid; 353 354 if (cpumask_equal(affinity, cpu_online_mask)) { 355 cpuid = map_to_cpu(irq); 356 } else { 357 cpuid = cpumask_first_and(affinity, cpu_online_mask); 358 cpuid = cpuid < nr_cpu_ids ? cpuid : map_to_cpu(irq); 359 } 360 361 return cpuid; 362 } 363 #else 364 #define irq_choose_cpu(irq, affinity) \ 365 real_hard_smp_processor_id() 366 #endif 367 368 static void sun4u_irq_enable(struct irq_data *data) 369 { 370 struct irq_handler_data *handler_data; 371 372 handler_data = irq_data_get_irq_handler_data(data); 373 if (likely(handler_data)) { 374 unsigned long cpuid, imap, val; 375 unsigned int tid; 376 377 cpuid = irq_choose_cpu(data->irq, 378 irq_data_get_affinity_mask(data)); 379 imap = handler_data->imap; 380 381 tid = sun4u_compute_tid(imap, cpuid); 382 383 val = upa_readq(imap); 384 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | 385 IMAP_AID_SAFARI | IMAP_NID_SAFARI); 386 val |= tid | IMAP_VALID; 387 upa_writeq(val, imap); 388 upa_writeq(ICLR_IDLE, handler_data->iclr); 389 } 390 } 391 392 static int sun4u_set_affinity(struct irq_data *data, 393 const struct cpumask *mask, bool force) 394 { 395 struct irq_handler_data *handler_data; 396 397 handler_data = irq_data_get_irq_handler_data(data); 398 if (likely(handler_data)) { 399 unsigned long cpuid, imap, val; 400 unsigned int tid; 401 402 cpuid = irq_choose_cpu(data->irq, mask); 403 imap = handler_data->imap; 404 405 tid = sun4u_compute_tid(imap, cpuid); 406 407 val = upa_readq(imap); 408 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | 409 IMAP_AID_SAFARI | IMAP_NID_SAFARI); 410 val |= tid | IMAP_VALID; 411 upa_writeq(val, imap); 412 upa_writeq(ICLR_IDLE, handler_data->iclr); 413 } 414 415 return 0; 416 } 417 418 /* Don't do anything. The desc->status check for IRQ_DISABLED in 419 * handler_irq() will skip the handler call and that will leave the 420 * interrupt in the sent state. The next ->enable() call will hit the 421 * ICLR register to reset the state machine. 422 * 423 * This scheme is necessary, instead of clearing the Valid bit in the 424 * IMAP register, to handle the case of IMAP registers being shared by 425 * multiple INOs (and thus ICLR registers). Since we use a different 426 * virtual IRQ for each shared IMAP instance, the generic code thinks 427 * there is only one user so it prematurely calls ->disable() on 428 * free_irq(). 429 * 430 * We have to provide an explicit ->disable() method instead of using 431 * NULL to get the default. The reason is that if the generic code 432 * sees that, it also hooks up a default ->shutdown method which 433 * invokes ->mask() which we do not want. See irq_chip_set_defaults(). 434 */ 435 static void sun4u_irq_disable(struct irq_data *data) 436 { 437 } 438 439 static void sun4u_irq_eoi(struct irq_data *data) 440 { 441 struct irq_handler_data *handler_data; 442 443 handler_data = irq_data_get_irq_handler_data(data); 444 if (likely(handler_data)) 445 upa_writeq(ICLR_IDLE, handler_data->iclr); 446 } 447 448 static void sun4v_irq_enable(struct irq_data *data) 449 { 450 unsigned long cpuid = irq_choose_cpu(data->irq, 451 irq_data_get_affinity_mask(data)); 452 unsigned int ino = irq_data_to_sysino(data); 453 int err; 454 455 err = sun4v_intr_settarget(ino, cpuid); 456 if (err != HV_EOK) 457 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " 458 "err(%d)\n", ino, cpuid, err); 459 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); 460 if (err != HV_EOK) 461 printk(KERN_ERR "sun4v_intr_setstate(%x): " 462 "err(%d)\n", ino, err); 463 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); 464 if (err != HV_EOK) 465 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", 466 ino, err); 467 } 468 469 static int sun4v_set_affinity(struct irq_data *data, 470 const struct cpumask *mask, bool force) 471 { 472 unsigned long cpuid = irq_choose_cpu(data->irq, mask); 473 unsigned int ino = irq_data_to_sysino(data); 474 int err; 475 476 err = sun4v_intr_settarget(ino, cpuid); 477 if (err != HV_EOK) 478 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " 479 "err(%d)\n", ino, cpuid, err); 480 481 return 0; 482 } 483 484 static void sun4v_irq_disable(struct irq_data *data) 485 { 486 unsigned int ino = irq_data_to_sysino(data); 487 int err; 488 489 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); 490 if (err != HV_EOK) 491 printk(KERN_ERR "sun4v_intr_setenabled(%x): " 492 "err(%d)\n", ino, err); 493 } 494 495 static void sun4v_irq_eoi(struct irq_data *data) 496 { 497 unsigned int ino = irq_data_to_sysino(data); 498 int err; 499 500 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); 501 if (err != HV_EOK) 502 printk(KERN_ERR "sun4v_intr_setstate(%x): " 503 "err(%d)\n", ino, err); 504 } 505 506 static void sun4v_virq_enable(struct irq_data *data) 507 { 508 unsigned long dev_handle = irq_data_to_handle(data); 509 unsigned long dev_ino = irq_data_to_ino(data); 510 unsigned long cpuid; 511 int err; 512 513 cpuid = irq_choose_cpu(data->irq, irq_data_get_affinity_mask(data)); 514 515 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); 516 if (err != HV_EOK) 517 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " 518 "err(%d)\n", 519 dev_handle, dev_ino, cpuid, err); 520 err = sun4v_vintr_set_state(dev_handle, dev_ino, 521 HV_INTR_STATE_IDLE); 522 if (err != HV_EOK) 523 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," 524 "HV_INTR_STATE_IDLE): err(%d)\n", 525 dev_handle, dev_ino, err); 526 err = sun4v_vintr_set_valid(dev_handle, dev_ino, 527 HV_INTR_ENABLED); 528 if (err != HV_EOK) 529 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," 530 "HV_INTR_ENABLED): err(%d)\n", 531 dev_handle, dev_ino, err); 532 } 533 534 static int sun4v_virt_set_affinity(struct irq_data *data, 535 const struct cpumask *mask, bool force) 536 { 537 unsigned long dev_handle = irq_data_to_handle(data); 538 unsigned long dev_ino = irq_data_to_ino(data); 539 unsigned long cpuid; 540 int err; 541 542 cpuid = irq_choose_cpu(data->irq, mask); 543 544 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); 545 if (err != HV_EOK) 546 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " 547 "err(%d)\n", 548 dev_handle, dev_ino, cpuid, err); 549 550 return 0; 551 } 552 553 static void sun4v_virq_disable(struct irq_data *data) 554 { 555 unsigned long dev_handle = irq_data_to_handle(data); 556 unsigned long dev_ino = irq_data_to_ino(data); 557 int err; 558 559 560 err = sun4v_vintr_set_valid(dev_handle, dev_ino, 561 HV_INTR_DISABLED); 562 if (err != HV_EOK) 563 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," 564 "HV_INTR_DISABLED): err(%d)\n", 565 dev_handle, dev_ino, err); 566 } 567 568 static void sun4v_virq_eoi(struct irq_data *data) 569 { 570 unsigned long dev_handle = irq_data_to_handle(data); 571 unsigned long dev_ino = irq_data_to_ino(data); 572 int err; 573 574 err = sun4v_vintr_set_state(dev_handle, dev_ino, 575 HV_INTR_STATE_IDLE); 576 if (err != HV_EOK) 577 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," 578 "HV_INTR_STATE_IDLE): err(%d)\n", 579 dev_handle, dev_ino, err); 580 } 581 582 static struct irq_chip sun4u_irq = { 583 .name = "sun4u", 584 .irq_enable = sun4u_irq_enable, 585 .irq_disable = sun4u_irq_disable, 586 .irq_eoi = sun4u_irq_eoi, 587 .irq_set_affinity = sun4u_set_affinity, 588 .flags = IRQCHIP_EOI_IF_HANDLED, 589 }; 590 591 static struct irq_chip sun4v_irq = { 592 .name = "sun4v", 593 .irq_enable = sun4v_irq_enable, 594 .irq_disable = sun4v_irq_disable, 595 .irq_eoi = sun4v_irq_eoi, 596 .irq_set_affinity = sun4v_set_affinity, 597 .flags = IRQCHIP_EOI_IF_HANDLED, 598 }; 599 600 static struct irq_chip sun4v_virq = { 601 .name = "vsun4v", 602 .irq_enable = sun4v_virq_enable, 603 .irq_disable = sun4v_virq_disable, 604 .irq_eoi = sun4v_virq_eoi, 605 .irq_set_affinity = sun4v_virt_set_affinity, 606 .flags = IRQCHIP_EOI_IF_HANDLED, 607 }; 608 609 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) 610 { 611 struct irq_handler_data *handler_data; 612 struct ino_bucket *bucket; 613 unsigned int irq; 614 int ino; 615 616 BUG_ON(tlb_type == hypervisor); 617 618 ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; 619 bucket = &ivector_table[ino]; 620 irq = bucket_get_irq(__pa(bucket)); 621 if (!irq) { 622 irq = irq_alloc(0, ino); 623 bucket_set_irq(__pa(bucket), irq); 624 irq_set_chip_and_handler_name(irq, &sun4u_irq, 625 handle_fasteoi_irq, "IVEC"); 626 } 627 628 handler_data = irq_get_handler_data(irq); 629 if (unlikely(handler_data)) 630 goto out; 631 632 handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); 633 if (unlikely(!handler_data)) { 634 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); 635 prom_halt(); 636 } 637 irq_set_handler_data(irq, handler_data); 638 639 handler_data->imap = imap; 640 handler_data->iclr = iclr; 641 642 out: 643 return irq; 644 } 645 646 static unsigned int sun4v_build_common(u32 devhandle, unsigned int devino, 647 void (*handler_data_init)(struct irq_handler_data *data, 648 u32 devhandle, unsigned int devino), 649 struct irq_chip *chip) 650 { 651 struct irq_handler_data *data; 652 unsigned int irq; 653 654 irq = irq_alloc(devhandle, devino); 655 if (!irq) 656 goto out; 657 658 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); 659 if (unlikely(!data)) { 660 pr_err("IRQ handler data allocation failed.\n"); 661 irq_free(irq); 662 irq = 0; 663 goto out; 664 } 665 666 irq_set_handler_data(irq, data); 667 handler_data_init(data, devhandle, devino); 668 irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq, "IVEC"); 669 data->imap = ~0UL; 670 data->iclr = ~0UL; 671 out: 672 return irq; 673 } 674 675 static unsigned long cookie_assign(unsigned int irq, u32 devhandle, 676 unsigned int devino) 677 { 678 struct irq_handler_data *ihd = irq_get_handler_data(irq); 679 unsigned long hv_error, cookie; 680 681 /* handler_irq needs to find the irq. cookie is seen signed in 682 * sun4v_dev_mondo and treated as a non ivector_table delivery. 683 */ 684 ihd->bucket.__irq = irq; 685 cookie = ~__pa(&ihd->bucket); 686 687 hv_error = sun4v_vintr_set_cookie(devhandle, devino, cookie); 688 if (hv_error) 689 pr_err("HV vintr set cookie failed = %ld\n", hv_error); 690 691 return hv_error; 692 } 693 694 static void cookie_handler_data(struct irq_handler_data *data, 695 u32 devhandle, unsigned int devino) 696 { 697 data->dev_handle = devhandle; 698 data->dev_ino = devino; 699 } 700 701 static unsigned int cookie_build_irq(u32 devhandle, unsigned int devino, 702 struct irq_chip *chip) 703 { 704 unsigned long hv_error; 705 unsigned int irq; 706 707 irq = sun4v_build_common(devhandle, devino, cookie_handler_data, chip); 708 709 hv_error = cookie_assign(irq, devhandle, devino); 710 if (hv_error) { 711 irq_free(irq); 712 irq = 0; 713 } 714 715 return irq; 716 } 717 718 static unsigned int sun4v_build_cookie(u32 devhandle, unsigned int devino) 719 { 720 unsigned int irq; 721 722 irq = cookie_exists(devhandle, devino); 723 if (irq) 724 goto out; 725 726 irq = cookie_build_irq(devhandle, devino, &sun4v_virq); 727 728 out: 729 return irq; 730 } 731 732 static void sysino_set_bucket(unsigned int irq) 733 { 734 struct irq_handler_data *ihd = irq_get_handler_data(irq); 735 struct ino_bucket *bucket; 736 unsigned long sysino; 737 738 sysino = sun4v_devino_to_sysino(ihd->dev_handle, ihd->dev_ino); 739 BUG_ON(sysino >= nr_ivec); 740 bucket = &ivector_table[sysino]; 741 bucket_set_irq(__pa(bucket), irq); 742 } 743 744 static void sysino_handler_data(struct irq_handler_data *data, 745 u32 devhandle, unsigned int devino) 746 { 747 unsigned long sysino; 748 749 sysino = sun4v_devino_to_sysino(devhandle, devino); 750 data->sysino = sysino; 751 } 752 753 static unsigned int sysino_build_irq(u32 devhandle, unsigned int devino, 754 struct irq_chip *chip) 755 { 756 unsigned int irq; 757 758 irq = sun4v_build_common(devhandle, devino, sysino_handler_data, chip); 759 if (!irq) 760 goto out; 761 762 sysino_set_bucket(irq); 763 out: 764 return irq; 765 } 766 767 static int sun4v_build_sysino(u32 devhandle, unsigned int devino) 768 { 769 int irq; 770 771 irq = sysino_exists(devhandle, devino); 772 if (irq) 773 goto out; 774 775 irq = sysino_build_irq(devhandle, devino, &sun4v_irq); 776 out: 777 return irq; 778 } 779 780 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) 781 { 782 unsigned int irq; 783 784 if (sun4v_cookie_only_virqs()) 785 irq = sun4v_build_cookie(devhandle, devino); 786 else 787 irq = sun4v_build_sysino(devhandle, devino); 788 789 return irq; 790 } 791 792 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) 793 { 794 int irq; 795 796 irq = cookie_build_irq(devhandle, devino, &sun4v_virq); 797 if (!irq) 798 goto out; 799 800 /* This is borrowed from the original function. 801 */ 802 irq_set_status_flags(irq, IRQ_NOAUTOEN); 803 804 out: 805 return irq; 806 } 807 808 void *hardirq_stack[NR_CPUS]; 809 void *softirq_stack[NR_CPUS]; 810 811 void __irq_entry handler_irq(int pil, struct pt_regs *regs) 812 { 813 unsigned long pstate, bucket_pa; 814 struct pt_regs *old_regs; 815 void *orig_sp; 816 817 clear_softint(1 << pil); 818 819 old_regs = set_irq_regs(regs); 820 irq_enter(); 821 822 /* Grab an atomic snapshot of the pending IVECs. */ 823 __asm__ __volatile__("rdpr %%pstate, %0\n\t" 824 "wrpr %0, %3, %%pstate\n\t" 825 "ldx [%2], %1\n\t" 826 "stx %%g0, [%2]\n\t" 827 "wrpr %0, 0x0, %%pstate\n\t" 828 : "=&r" (pstate), "=&r" (bucket_pa) 829 : "r" (irq_work_pa(smp_processor_id())), 830 "i" (PSTATE_IE) 831 : "memory"); 832 833 orig_sp = set_hardirq_stack(); 834 835 while (bucket_pa) { 836 unsigned long next_pa; 837 unsigned int irq; 838 839 next_pa = bucket_get_chain_pa(bucket_pa); 840 irq = bucket_get_irq(bucket_pa); 841 bucket_clear_chain_pa(bucket_pa); 842 843 generic_handle_irq(irq); 844 845 bucket_pa = next_pa; 846 } 847 848 restore_hardirq_stack(orig_sp); 849 850 irq_exit(); 851 set_irq_regs(old_regs); 852 } 853 854 #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK 855 void do_softirq_own_stack(void) 856 { 857 void *orig_sp, *sp = softirq_stack[smp_processor_id()]; 858 859 sp += THREAD_SIZE - 192 - STACK_BIAS; 860 861 __asm__ __volatile__("mov %%sp, %0\n\t" 862 "mov %1, %%sp" 863 : "=&r" (orig_sp) 864 : "r" (sp)); 865 __do_softirq(); 866 __asm__ __volatile__("mov %0, %%sp" 867 : : "r" (orig_sp)); 868 } 869 #endif 870 871 #ifdef CONFIG_HOTPLUG_CPU 872 void fixup_irqs(void) 873 { 874 unsigned int irq; 875 876 for (irq = 0; irq < NR_IRQS; irq++) { 877 struct irq_desc *desc = irq_to_desc(irq); 878 struct irq_data *data; 879 unsigned long flags; 880 881 if (!desc) 882 continue; 883 data = irq_desc_get_irq_data(desc); 884 raw_spin_lock_irqsave(&desc->lock, flags); 885 if (desc->action && !irqd_is_per_cpu(data)) { 886 if (data->chip->irq_set_affinity) 887 data->chip->irq_set_affinity(data, 888 irq_data_get_affinity_mask(data), 889 false); 890 } 891 raw_spin_unlock_irqrestore(&desc->lock, flags); 892 } 893 894 tick_ops->disable_irq(); 895 } 896 #endif 897 898 struct sun5_timer { 899 u64 count0; 900 u64 limit0; 901 u64 count1; 902 u64 limit1; 903 }; 904 905 static struct sun5_timer *prom_timers; 906 static u64 prom_limit0, prom_limit1; 907 908 static void map_prom_timers(void) 909 { 910 struct device_node *dp; 911 const unsigned int *addr; 912 913 /* PROM timer node hangs out in the top level of device siblings... */ 914 dp = of_find_node_by_path("/"); 915 dp = dp->child; 916 while (dp) { 917 if (of_node_name_eq(dp, "counter-timer")) 918 break; 919 dp = dp->sibling; 920 } 921 922 /* Assume if node is not present, PROM uses different tick mechanism 923 * which we should not care about. 924 */ 925 if (!dp) { 926 prom_timers = (struct sun5_timer *) 0; 927 return; 928 } 929 930 /* If PROM is really using this, it must be mapped by him. */ 931 addr = of_get_property(dp, "address", NULL); 932 if (!addr) { 933 prom_printf("PROM does not have timer mapped, trying to continue.\n"); 934 prom_timers = (struct sun5_timer *) 0; 935 return; 936 } 937 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); 938 } 939 940 static void kill_prom_timer(void) 941 { 942 if (!prom_timers) 943 return; 944 945 /* Save them away for later. */ 946 prom_limit0 = prom_timers->limit0; 947 prom_limit1 = prom_timers->limit1; 948 949 /* Just as in sun4c PROM uses timer which ticks at IRQ 14. 950 * We turn both off here just to be paranoid. 951 */ 952 prom_timers->limit0 = 0; 953 prom_timers->limit1 = 0; 954 955 /* Wheee, eat the interrupt packet too... */ 956 __asm__ __volatile__( 957 " mov 0x40, %%g2\n" 958 " ldxa [%%g0] %0, %%g1\n" 959 " ldxa [%%g2] %1, %%g1\n" 960 " stxa %%g0, [%%g0] %0\n" 961 " membar #Sync\n" 962 : /* no outputs */ 963 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) 964 : "g1", "g2"); 965 } 966 967 void notrace init_irqwork_curcpu(void) 968 { 969 int cpu = hard_smp_processor_id(); 970 971 trap_block[cpu].irq_worklist_pa = 0UL; 972 } 973 974 /* Please be very careful with register_one_mondo() and 975 * sun4v_register_mondo_queues(). 976 * 977 * On SMP this gets invoked from the CPU trampoline before 978 * the cpu has fully taken over the trap table from OBP, 979 * and its kernel stack + %g6 thread register state is 980 * not fully cooked yet. 981 * 982 * Therefore you cannot make any OBP calls, not even prom_printf, 983 * from these two routines. 984 */ 985 static void notrace register_one_mondo(unsigned long paddr, unsigned long type, 986 unsigned long qmask) 987 { 988 unsigned long num_entries = (qmask + 1) / 64; 989 unsigned long status; 990 991 status = sun4v_cpu_qconf(type, paddr, num_entries); 992 if (status != HV_EOK) { 993 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " 994 "err %lu\n", type, paddr, num_entries, status); 995 prom_halt(); 996 } 997 } 998 999 void notrace sun4v_register_mondo_queues(int this_cpu) 1000 { 1001 struct trap_per_cpu *tb = &trap_block[this_cpu]; 1002 1003 register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, 1004 tb->cpu_mondo_qmask); 1005 register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, 1006 tb->dev_mondo_qmask); 1007 register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, 1008 tb->resum_qmask); 1009 register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, 1010 tb->nonresum_qmask); 1011 } 1012 1013 /* Each queue region must be a power of 2 multiple of 64 bytes in 1014 * size. The base real address must be aligned to the size of the 1015 * region. Thus, an 8KB queue must be 8KB aligned, for example. 1016 */ 1017 static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask) 1018 { 1019 unsigned long size = PAGE_ALIGN(qmask + 1); 1020 unsigned long order = get_order(size); 1021 unsigned long p; 1022 1023 p = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order); 1024 if (!p) { 1025 prom_printf("SUN4V: Error, cannot allocate queue.\n"); 1026 prom_halt(); 1027 } 1028 1029 *pa_ptr = __pa(p); 1030 } 1031 1032 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) 1033 { 1034 #ifdef CONFIG_SMP 1035 unsigned long page; 1036 void *mondo, *p; 1037 1038 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > PAGE_SIZE); 1039 1040 /* Make sure mondo block is 64byte aligned */ 1041 p = kzalloc(127, GFP_KERNEL); 1042 if (!p) { 1043 prom_printf("SUN4V: Error, cannot allocate mondo block.\n"); 1044 prom_halt(); 1045 } 1046 mondo = (void *)(((unsigned long)p + 63) & ~0x3f); 1047 tb->cpu_mondo_block_pa = __pa(mondo); 1048 1049 page = get_zeroed_page(GFP_KERNEL); 1050 if (!page) { 1051 prom_printf("SUN4V: Error, cannot allocate cpu list page.\n"); 1052 prom_halt(); 1053 } 1054 1055 tb->cpu_list_pa = __pa(page); 1056 #endif 1057 } 1058 1059 /* Allocate mondo and error queues for all possible cpus. */ 1060 static void __init sun4v_init_mondo_queues(void) 1061 { 1062 int cpu; 1063 1064 for_each_possible_cpu(cpu) { 1065 struct trap_per_cpu *tb = &trap_block[cpu]; 1066 1067 alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); 1068 alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask); 1069 alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask); 1070 alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask); 1071 alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask); 1072 alloc_one_queue(&tb->nonresum_kernel_buf_pa, 1073 tb->nonresum_qmask); 1074 } 1075 } 1076 1077 static void __init init_send_mondo_info(void) 1078 { 1079 int cpu; 1080 1081 for_each_possible_cpu(cpu) { 1082 struct trap_per_cpu *tb = &trap_block[cpu]; 1083 1084 init_cpu_send_mondo_info(tb); 1085 } 1086 } 1087 1088 static struct irqaction timer_irq_action = { 1089 .name = "timer", 1090 }; 1091 1092 static void __init irq_ivector_init(void) 1093 { 1094 unsigned long size, order; 1095 unsigned int ivecs; 1096 1097 /* If we are doing cookie only VIRQs then we do not need the ivector 1098 * table to process interrupts. 1099 */ 1100 if (sun4v_cookie_only_virqs()) 1101 return; 1102 1103 ivecs = size_nr_ivec(); 1104 size = sizeof(struct ino_bucket) * ivecs; 1105 order = get_order(size); 1106 ivector_table = (struct ino_bucket *) 1107 __get_free_pages(GFP_KERNEL | __GFP_ZERO, order); 1108 if (!ivector_table) { 1109 prom_printf("Fatal error, cannot allocate ivector_table\n"); 1110 prom_halt(); 1111 } 1112 __flush_dcache_range((unsigned long) ivector_table, 1113 ((unsigned long) ivector_table) + size); 1114 1115 ivector_table_pa = __pa(ivector_table); 1116 } 1117 1118 /* Only invoked on boot processor.*/ 1119 void __init init_IRQ(void) 1120 { 1121 irq_init_hv(); 1122 irq_ivector_init(); 1123 map_prom_timers(); 1124 kill_prom_timer(); 1125 1126 if (tlb_type == hypervisor) 1127 sun4v_init_mondo_queues(); 1128 1129 init_send_mondo_info(); 1130 1131 if (tlb_type == hypervisor) { 1132 /* Load up the boot cpu's entries. */ 1133 sun4v_register_mondo_queues(hard_smp_processor_id()); 1134 } 1135 1136 /* We need to clear any IRQ's pending in the soft interrupt 1137 * registers, a spurious one could be left around from the 1138 * PROM timer which we just disabled. 1139 */ 1140 clear_softint(get_softint()); 1141 1142 /* Now that ivector table is initialized, it is safe 1143 * to receive IRQ vector traps. We will normally take 1144 * one or two right now, in case some device PROM used 1145 * to boot us wants to speak to us. We just ignore them. 1146 */ 1147 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" 1148 "or %%g1, %0, %%g1\n\t" 1149 "wrpr %%g1, 0x0, %%pstate" 1150 : /* No outputs */ 1151 : "i" (PSTATE_IE) 1152 : "g1"); 1153 1154 irq_to_desc(0)->action = &timer_irq_action; 1155 } 1156