11d05995bSSam Ravnborg #include <linux/platform_device.h> 21d05995bSSam Ravnborg 3d550bbd4SDavid Howells #include <asm/cpu_type.h> 432231a66SAl Viro 56baa9b20SSam Ravnborg struct irq_bucket { 66baa9b20SSam Ravnborg struct irq_bucket *next; 76baa9b20SSam Ravnborg unsigned int real_irq; 86baa9b20SSam Ravnborg unsigned int irq; 96baa9b20SSam Ravnborg unsigned int pil; 106baa9b20SSam Ravnborg }; 116baa9b20SSam Ravnborg 124ba22b16SSam Ravnborg #define SUN4M_HARD_INT(x) (0x000000001 << (x)) 134ba22b16SSam Ravnborg #define SUN4M_SOFT_INT(x) (0x000010000 << (x)) 144ba22b16SSam Ravnborg 156baa9b20SSam Ravnborg #define SUN4D_MAX_BOARD 10 166baa9b20SSam Ravnborg #define SUN4D_MAX_IRQ ((SUN4D_MAX_BOARD + 2) << 5) 176baa9b20SSam Ravnborg 186baa9b20SSam Ravnborg /* Map between the irq identifier used in hw to the 196baa9b20SSam Ravnborg * irq_bucket. The map is sufficient large to hold 206baa9b20SSam Ravnborg * the sun4d hw identifiers. 216baa9b20SSam Ravnborg */ 226baa9b20SSam Ravnborg extern struct irq_bucket *irq_map[SUN4D_MAX_IRQ]; 236baa9b20SSam Ravnborg 246baa9b20SSam Ravnborg 250399bb5bSSam Ravnborg /* sun4m specific type definitions */ 260399bb5bSSam Ravnborg 270399bb5bSSam Ravnborg /* This maps direct to CPU specific interrupt registers */ 280399bb5bSSam Ravnborg struct sun4m_irq_percpu { 290399bb5bSSam Ravnborg u32 pending; 300399bb5bSSam Ravnborg u32 clear; 310399bb5bSSam Ravnborg u32 set; 320399bb5bSSam Ravnborg }; 330399bb5bSSam Ravnborg 340399bb5bSSam Ravnborg /* This maps direct to global interrupt registers */ 350399bb5bSSam Ravnborg struct sun4m_irq_global { 360399bb5bSSam Ravnborg u32 pending; 370399bb5bSSam Ravnborg u32 mask; 380399bb5bSSam Ravnborg u32 mask_clear; 390399bb5bSSam Ravnborg u32 mask_set; 400399bb5bSSam Ravnborg u32 interrupt_target; 410399bb5bSSam Ravnborg }; 420399bb5bSSam Ravnborg 430399bb5bSSam Ravnborg extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS]; 440399bb5bSSam Ravnborg extern struct sun4m_irq_global __iomem *sun4m_irq_global; 450399bb5bSSam Ravnborg 4662f08283STkhai Kirill /* The following definitions describe the individual platform features: */ 4762f08283STkhai Kirill #define FEAT_L10_CLOCKSOURCE (1 << 0) /* L10 timer is used as a clocksource */ 4862f08283STkhai Kirill #define FEAT_L10_CLOCKEVENT (1 << 1) /* L10 timer is used as a clockevent */ 4962f08283STkhai Kirill #define FEAT_L14_ONESHOT (1 << 2) /* L14 timer clockevent can oneshot */ 5062f08283STkhai Kirill 51bbdc2661SSam Ravnborg /* 52472bc4f2SSam Ravnborg * Platform specific configuration 53bbdc2661SSam Ravnborg * The individual platforms assign their platform 54bbdc2661SSam Ravnborg * specifics in their init functions. 55bbdc2661SSam Ravnborg */ 56472bc4f2SSam Ravnborg struct sparc_config { 5762f08283STkhai Kirill void (*init_timers)(void); 581d05995bSSam Ravnborg unsigned int (*build_device_irq)(struct platform_device *op, 591d05995bSSam Ravnborg unsigned int real_irq); 6062f08283STkhai Kirill 6162f08283STkhai Kirill /* generic clockevent features - see FEAT_* above */ 6262f08283STkhai Kirill int features; 6362f08283STkhai Kirill 6462f08283STkhai Kirill /* clock rate used for clock event timer */ 6562f08283STkhai Kirill int clock_rate; 6662f08283STkhai Kirill 6762f08283STkhai Kirill /* one period for clock source timer */ 6862f08283STkhai Kirill unsigned int cs_period; 6962f08283STkhai Kirill 7062f08283STkhai Kirill /* function to obtain offsett for cs period */ 7162f08283STkhai Kirill unsigned int (*get_cycles_offset)(void); 7208c9388fSSam Ravnborg 7308c9388fSSam Ravnborg void (*clear_clock_irq)(void); 7408c9388fSSam Ravnborg void (*load_profile_irq)(int cpu, unsigned int limit); 75bbdc2661SSam Ravnborg }; 76472bc4f2SSam Ravnborg extern struct sparc_config sparc_config; 77bbdc2661SSam Ravnborg 786baa9b20SSam Ravnborg unsigned int irq_alloc(unsigned int real_irq, unsigned int pil); 796baa9b20SSam Ravnborg void irq_link(unsigned int irq); 806baa9b20SSam Ravnborg void irq_unlink(unsigned int irq); 816baa9b20SSam Ravnborg void handler_irq(unsigned int pil, struct pt_regs *regs); 82bbdc2661SSam Ravnborg 834ba22b16SSam Ravnborg unsigned long leon_get_irqmask(unsigned int irq); 8432231a66SAl Viro 85fbb86383SSam Ravnborg /* irq_32.c */ 86fbb86383SSam Ravnborg void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs); 87fbb86383SSam Ravnborg 882b399177SSam Ravnborg /* sun4m_irq.c */ 892b399177SSam Ravnborg void sun4m_nmi(struct pt_regs *regs); 902b399177SSam Ravnborg 915ac75688SSam Ravnborg /* sun4d_irq.c */ 925ac75688SSam Ravnborg void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs); 935ac75688SSam Ravnborg 944ba22b16SSam Ravnborg #ifdef CONFIG_SMP 9555dd23ecSDaniel Hellstrom 9655dd23ecSDaniel Hellstrom /* All SUN4D IPIs are sent on this IRQ, may be shared with hard IRQs */ 9738f7f8f0SKjetil Oftedal #define SUN4D_IPI_IRQ 13 9855dd23ecSDaniel Hellstrom 99*2e74a74fSSam Ravnborg void sun4d_ipi_interrupt(void); 10055dd23ecSDaniel Hellstrom 10132231a66SAl Viro #endif 102