1*a88b5ba8SSam Ravnborg/* hvtramp.S: Hypervisor start-cpu trampoline code. 2*a88b5ba8SSam Ravnborg * 3*a88b5ba8SSam Ravnborg * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net> 4*a88b5ba8SSam Ravnborg */ 5*a88b5ba8SSam Ravnborg 6*a88b5ba8SSam Ravnborg#include <linux/init.h> 7*a88b5ba8SSam Ravnborg 8*a88b5ba8SSam Ravnborg#include <asm/thread_info.h> 9*a88b5ba8SSam Ravnborg#include <asm/hypervisor.h> 10*a88b5ba8SSam Ravnborg#include <asm/scratchpad.h> 11*a88b5ba8SSam Ravnborg#include <asm/spitfire.h> 12*a88b5ba8SSam Ravnborg#include <asm/hvtramp.h> 13*a88b5ba8SSam Ravnborg#include <asm/pstate.h> 14*a88b5ba8SSam Ravnborg#include <asm/ptrace.h> 15*a88b5ba8SSam Ravnborg#include <asm/head.h> 16*a88b5ba8SSam Ravnborg#include <asm/asi.h> 17*a88b5ba8SSam Ravnborg#include <asm/pil.h> 18*a88b5ba8SSam Ravnborg 19*a88b5ba8SSam Ravnborg __CPUINIT 20*a88b5ba8SSam Ravnborg .align 8 21*a88b5ba8SSam Ravnborg .globl hv_cpu_startup, hv_cpu_startup_end 22*a88b5ba8SSam Ravnborg 23*a88b5ba8SSam Ravnborg /* This code executes directly out of the hypervisor 24*a88b5ba8SSam Ravnborg * with physical addressing (va==pa). %o0 contains 25*a88b5ba8SSam Ravnborg * our client argument which for Linux points to 26*a88b5ba8SSam Ravnborg * a descriptor data structure which defines the 27*a88b5ba8SSam Ravnborg * MMU entries we need to load up. 28*a88b5ba8SSam Ravnborg * 29*a88b5ba8SSam Ravnborg * After we set things up we enable the MMU and call 30*a88b5ba8SSam Ravnborg * into the kernel. 31*a88b5ba8SSam Ravnborg * 32*a88b5ba8SSam Ravnborg * First setup basic privileged cpu state. 33*a88b5ba8SSam Ravnborg */ 34*a88b5ba8SSam Ravnborghv_cpu_startup: 35*a88b5ba8SSam Ravnborg SET_GL(0) 36*a88b5ba8SSam Ravnborg wrpr %g0, PIL_NORMAL_MAX, %pil 37*a88b5ba8SSam Ravnborg wrpr %g0, 0, %canrestore 38*a88b5ba8SSam Ravnborg wrpr %g0, 0, %otherwin 39*a88b5ba8SSam Ravnborg wrpr %g0, 6, %cansave 40*a88b5ba8SSam Ravnborg wrpr %g0, 6, %cleanwin 41*a88b5ba8SSam Ravnborg wrpr %g0, 0, %cwp 42*a88b5ba8SSam Ravnborg wrpr %g0, 0, %wstate 43*a88b5ba8SSam Ravnborg wrpr %g0, 0, %tl 44*a88b5ba8SSam Ravnborg 45*a88b5ba8SSam Ravnborg sethi %hi(sparc64_ttable_tl0), %g1 46*a88b5ba8SSam Ravnborg wrpr %g1, %tba 47*a88b5ba8SSam Ravnborg 48*a88b5ba8SSam Ravnborg mov %o0, %l0 49*a88b5ba8SSam Ravnborg 50*a88b5ba8SSam Ravnborg lduw [%l0 + HVTRAMP_DESCR_CPU], %g1 51*a88b5ba8SSam Ravnborg mov SCRATCHPAD_CPUID, %g2 52*a88b5ba8SSam Ravnborg stxa %g1, [%g2] ASI_SCRATCHPAD 53*a88b5ba8SSam Ravnborg 54*a88b5ba8SSam Ravnborg ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2 55*a88b5ba8SSam Ravnborg stxa %g2, [%g0] ASI_SCRATCHPAD 56*a88b5ba8SSam Ravnborg 57*a88b5ba8SSam Ravnborg mov 0, %l1 58*a88b5ba8SSam Ravnborg lduw [%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2 59*a88b5ba8SSam Ravnborg add %l0, HVTRAMP_DESCR_MAPS, %l3 60*a88b5ba8SSam Ravnborg 61*a88b5ba8SSam Ravnborg1: ldx [%l3 + HVTRAMP_MAPPING_VADDR], %o0 62*a88b5ba8SSam Ravnborg clr %o1 63*a88b5ba8SSam Ravnborg ldx [%l3 + HVTRAMP_MAPPING_TTE], %o2 64*a88b5ba8SSam Ravnborg mov HV_MMU_IMMU | HV_MMU_DMMU, %o3 65*a88b5ba8SSam Ravnborg mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 66*a88b5ba8SSam Ravnborg ta HV_FAST_TRAP 67*a88b5ba8SSam Ravnborg 68*a88b5ba8SSam Ravnborg brnz,pn %o0, 80f 69*a88b5ba8SSam Ravnborg nop 70*a88b5ba8SSam Ravnborg 71*a88b5ba8SSam Ravnborg add %l1, 1, %l1 72*a88b5ba8SSam Ravnborg cmp %l1, %l2 73*a88b5ba8SSam Ravnborg blt,a,pt %xcc, 1b 74*a88b5ba8SSam Ravnborg add %l3, HVTRAMP_MAPPING_SIZE, %l3 75*a88b5ba8SSam Ravnborg 76*a88b5ba8SSam Ravnborg ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0 77*a88b5ba8SSam Ravnborg mov HV_FAST_MMU_FAULT_AREA_CONF, %o5 78*a88b5ba8SSam Ravnborg ta HV_FAST_TRAP 79*a88b5ba8SSam Ravnborg 80*a88b5ba8SSam Ravnborg brnz,pn %o0, 80f 81*a88b5ba8SSam Ravnborg nop 82*a88b5ba8SSam Ravnborg 83*a88b5ba8SSam Ravnborg wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate 84*a88b5ba8SSam Ravnborg 85*a88b5ba8SSam Ravnborg ldx [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6 86*a88b5ba8SSam Ravnborg 87*a88b5ba8SSam Ravnborg mov 1, %o0 88*a88b5ba8SSam Ravnborg set 1f, %o1 89*a88b5ba8SSam Ravnborg mov HV_FAST_MMU_ENABLE, %o5 90*a88b5ba8SSam Ravnborg ta HV_FAST_TRAP 91*a88b5ba8SSam Ravnborg 92*a88b5ba8SSam Ravnborg ba,pt %xcc, 80f 93*a88b5ba8SSam Ravnborg nop 94*a88b5ba8SSam Ravnborg 95*a88b5ba8SSam Ravnborg1: 96*a88b5ba8SSam Ravnborg wr %g0, 0, %fprs 97*a88b5ba8SSam Ravnborg wr %g0, ASI_P, %asi 98*a88b5ba8SSam Ravnborg 99*a88b5ba8SSam Ravnborg mov PRIMARY_CONTEXT, %g7 100*a88b5ba8SSam Ravnborg stxa %g0, [%g7] ASI_MMU 101*a88b5ba8SSam Ravnborg membar #Sync 102*a88b5ba8SSam Ravnborg 103*a88b5ba8SSam Ravnborg mov SECONDARY_CONTEXT, %g7 104*a88b5ba8SSam Ravnborg stxa %g0, [%g7] ASI_MMU 105*a88b5ba8SSam Ravnborg membar #Sync 106*a88b5ba8SSam Ravnborg 107*a88b5ba8SSam Ravnborg mov %l6, %g6 108*a88b5ba8SSam Ravnborg ldx [%g6 + TI_TASK], %g4 109*a88b5ba8SSam Ravnborg 110*a88b5ba8SSam Ravnborg mov 1, %g5 111*a88b5ba8SSam Ravnborg sllx %g5, THREAD_SHIFT, %g5 112*a88b5ba8SSam Ravnborg sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5 113*a88b5ba8SSam Ravnborg add %g6, %g5, %sp 114*a88b5ba8SSam Ravnborg mov 0, %fp 115*a88b5ba8SSam Ravnborg 116*a88b5ba8SSam Ravnborg call init_irqwork_curcpu 117*a88b5ba8SSam Ravnborg nop 118*a88b5ba8SSam Ravnborg call hard_smp_processor_id 119*a88b5ba8SSam Ravnborg nop 120*a88b5ba8SSam Ravnborg 121*a88b5ba8SSam Ravnborg call sun4v_register_mondo_queues 122*a88b5ba8SSam Ravnborg nop 123*a88b5ba8SSam Ravnborg 124*a88b5ba8SSam Ravnborg call init_cur_cpu_trap 125*a88b5ba8SSam Ravnborg mov %g6, %o0 126*a88b5ba8SSam Ravnborg 127*a88b5ba8SSam Ravnborg wrpr %g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate 128*a88b5ba8SSam Ravnborg 129*a88b5ba8SSam Ravnborg call smp_callin 130*a88b5ba8SSam Ravnborg nop 131*a88b5ba8SSam Ravnborg call cpu_idle 132*a88b5ba8SSam Ravnborg mov 0, %o0 133*a88b5ba8SSam Ravnborg call cpu_panic 134*a88b5ba8SSam Ravnborg nop 135*a88b5ba8SSam Ravnborg 136*a88b5ba8SSam Ravnborg80: ba,pt %xcc, 80b 137*a88b5ba8SSam Ravnborg nop 138*a88b5ba8SSam Ravnborg 139*a88b5ba8SSam Ravnborg .align 8 140*a88b5ba8SSam Ravnborghv_cpu_startup_end: 141