1/* 2 * head.S: The initial boot code for the Sparc port of Linux. 3 * 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1995,1999 Pete Zaitcev (zaitcev@yahoo.com) 6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) 7 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 8 * Copyright (C) 1997 Michael A. Griffith (grif@acm.org) 9 * 10 * CompactPCI platform by Eric Brower, 1999. 11 */ 12 13#include <linux/version.h> 14#include <linux/init.h> 15 16#include <asm/head.h> 17#include <asm/asi.h> 18#include <asm/contregs.h> 19#include <asm/ptrace.h> 20#include <asm/psr.h> 21#include <asm/page.h> 22#include <asm/kdebug.h> 23#include <asm/winmacro.h> 24#include <asm/thread_info.h> /* TI_UWINMASK */ 25#include <asm/errno.h> 26#include <asm/pgtsrmmu.h> /* SRMMU_PGDIR_SHIFT */ 27 28 .data 29/* The following are used with the prom_vector node-ops to figure out 30 * the cpu-type 31 */ 32 .align 4 33cputyp: 34 .word 1 35 36 .align 4 37 .globl cputypval 38cputypval: 39 .asciz "sun4m" 40 .ascii " " 41 42/* Tested on SS-5, SS-10 */ 43 .align 4 44cputypvar: 45 .asciz "compatible" 46 47 .align 4 48 49sun4c_notsup: 50 .asciz "Sparc-Linux sun4/sun4c support does no longer exist.\n\n" 51 .align 4 52 53sun4e_notsup: 54 .asciz "Sparc-Linux sun4e support does not exist\n\n" 55 .align 4 56 57/* The trap-table - located in the __HEAD section */ 58#include "ttable_32.S" 59 60 .align PAGE_SIZE 61 62/* This was the only reasonable way I could think of to properly align 63 * these page-table data structures. 64 */ 65 .globl swapper_pg_dir 66swapper_pg_dir: .skip PAGE_SIZE 67 .globl empty_zero_page 68empty_zero_page: .skip PAGE_SIZE 69 70 .global root_flags 71 .global ram_flags 72 .global root_dev 73 .global sparc_ramdisk_image 74 .global sparc_ramdisk_size 75 76/* This stuff has to be in sync with SILO and other potential boot loaders 77 * Fields should be kept upward compatible and whenever any change is made, 78 * HdrS version should be incremented. 79 */ 80 .ascii "HdrS" 81 .word LINUX_VERSION_CODE 82 .half 0x0203 /* HdrS version */ 83root_flags: 84 .half 1 85root_dev: 86 .half 0 87ram_flags: 88 .half 0 89sparc_ramdisk_image: 90 .word 0 91sparc_ramdisk_size: 92 .word 0 93 .word reboot_command 94 .word 0, 0, 0 95 .word _end 96 97/* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in 98 * %g7 and at prom_vector_p. And also quickly check whether we are on 99 * a v0, v2, or v3 prom. 100 */ 101gokernel: 102 /* Ok, it's nice to know, as early as possible, if we 103 * are already mapped where we expect to be in virtual 104 * memory. The Solaris /boot elf format bootloader 105 * will peek into our elf header and load us where 106 * we want to be, otherwise we have to re-map. 107 * 108 * Some boot loaders don't place the jmp'rs address 109 * in %o7, so we do a pc-relative call to a local 110 * label, then see what %o7 has. 111 */ 112 113 mov %o7, %g4 ! Save %o7 114 115 /* Jump to it, and pray... */ 116current_pc: 117 call 1f 118 nop 119 1201: 121 mov %o7, %g3 122 123 tst %o0 124 be no_sun4u_here 125 mov %g4, %o7 /* Previous %o7. */ 126 127 mov %o0, %l0 ! stash away romvec 128 mov %o0, %g7 ! put it here too 129 mov %o1, %l1 ! stash away debug_vec too 130 131 /* Ok, let's check out our run time program counter. */ 132 set current_pc, %g5 133 cmp %g3, %g5 134 be already_mapped 135 nop 136 137 /* %l6 will hold the offset we have to subtract 138 * from absolute symbols in order to access areas 139 * in our own image. If already mapped this is 140 * just plain zero, else it is KERNBASE. 141 */ 142 set KERNBASE, %l6 143 b copy_prom_lvl14 144 nop 145 146already_mapped: 147 mov 0, %l6 148 149 /* Copy over the Prom's level 14 clock handler. */ 150copy_prom_lvl14: 151#if 1 152 /* DJHR 153 * preserve our linked/calculated instructions 154 */ 155 set lvl14_save, %g1 156 set t_irq14, %g3 157 sub %g1, %l6, %g1 ! translate to physical 158 sub %g3, %l6, %g3 ! translate to physical 159 ldd [%g3], %g4 160 std %g4, [%g1] 161 ldd [%g3+8], %g4 162 std %g4, [%g1+8] 163#endif 164 rd %tbr, %g1 165 andn %g1, 0xfff, %g1 ! proms trap table base 166 or %g0, (0x1e<<4), %g2 ! offset to lvl14 intr 167 or %g1, %g2, %g2 168 set t_irq14, %g3 169 sub %g3, %l6, %g3 170 ldd [%g2], %g4 171 std %g4, [%g3] 172 ldd [%g2 + 0x8], %g4 173 std %g4, [%g3 + 0x8] ! Copy proms handler 174 175/* DON'T TOUCH %l0 thru %l5 in these remapping routines, 176 * we need their values afterwards! 177 */ 178 179 /* Now check whether we are already mapped, if we 180 * are we can skip all this garbage coming up. 181 */ 182copy_prom_done: 183 cmp %l6, 0 184 be go_to_highmem ! this will be a nop then 185 nop 186 187 /* Validate that we are in fact running on an 188 * SRMMU based cpu. 189 */ 190 set 0x4000, %g6 191 cmp %g7, %g6 192 bne not_a_sun4 193 nop 194 195halt_sun4_or_sun4c: 196 ld [%g7 + 0x68], %o1 197 set sun4c_notsup, %o0 198 sub %o0, %l6, %o0 199 call %o1 200 nop 201 ba halt_me 202 nop 203 204not_a_sun4: 205 lda [%g0] ASI_M_MMUREGS, %g1 206 andcc %g1, 1, %g0 207 be halt_sun4_or_sun4c 208 nop 209 210srmmu_remap: 211 /* First, check for a viking (TI) module. */ 212 set 0x40000000, %g2 213 rd %psr, %g3 214 and %g2, %g3, %g3 215 subcc %g3, 0x0, %g0 216 bz srmmu_nviking 217 nop 218 219 /* Figure out what kind of viking we are on. 220 * We need to know if we have to play with the 221 * AC bit and disable traps or not. 222 */ 223 224 /* I've only seen MicroSparc's on SparcClassics with this 225 * bit set. 226 */ 227 set 0x800, %g2 228 lda [%g0] ASI_M_MMUREGS, %g3 ! peek in the control reg 229 and %g2, %g3, %g3 230 subcc %g3, 0x0, %g0 231 bnz srmmu_nviking ! is in mbus mode 232 nop 233 234 rd %psr, %g3 ! DO NOT TOUCH %g3 235 andn %g3, PSR_ET, %g2 236 wr %g2, 0x0, %psr 237 WRITE_PAUSE 238 239 /* Get context table pointer, then convert to 240 * a physical address, which is 36 bits. 241 */ 242 set AC_M_CTPR, %g4 243 lda [%g4] ASI_M_MMUREGS, %g4 244 sll %g4, 0x4, %g4 ! We use this below 245 ! DO NOT TOUCH %g4 246 247 /* Set the AC bit in the Viking's MMU control reg. */ 248 lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5 249 set 0x8000, %g6 ! AC bit mask 250 or %g5, %g6, %g6 ! Or it in... 251 sta %g6, [%g0] ASI_M_MMUREGS ! Close your eyes... 252 253 /* Grrr, why does it seem like every other load/store 254 * on the sun4m is in some ASI space... 255 * Fine with me, let's get the pointer to the level 1 256 * page table directory and fetch its entry. 257 */ 258 lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr 259 srl %o1, 0x4, %o1 ! Clear low 4 bits 260 sll %o1, 0x8, %o1 ! Make physical 261 262 /* Ok, pull in the PTD. */ 263 lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd 264 265 /* Calculate to KERNBASE entry. */ 266 add %o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3 267 268 /* Poke the entry into the calculated address. */ 269 sta %o2, [%o3] ASI_M_BYPASS 270 271 /* I don't get it Sun, if you engineered all these 272 * boot loaders and the PROM (thank you for the debugging 273 * features btw) why did you not have them load kernel 274 * images up in high address space, since this is necessary 275 * for ABI compliance anyways? Does this low-mapping provide 276 * enhanced interoperability? 277 * 278 * "The PROM is the computer." 279 */ 280 281 /* Ok, restore the MMU control register we saved in %g5 */ 282 sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch 283 284 /* Turn traps back on. We saved it in %g3 earlier. */ 285 wr %g3, 0x0, %psr ! tick tock, tick tock 286 287 /* Now we burn precious CPU cycles due to bad engineering. */ 288 WRITE_PAUSE 289 290 /* Wow, all that just to move a 32-bit value from one 291 * place to another... Jump to high memory. 292 */ 293 b go_to_highmem 294 nop 295 296 /* This works on viking's in Mbus mode and all 297 * other MBUS modules. It is virtually the same as 298 * the above madness sans turning traps off and flipping 299 * the AC bit. 300 */ 301srmmu_nviking: 302 set AC_M_CTPR, %g1 303 lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr 304 sll %g1, 0x4, %g1 ! make physical addr 305 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table 306 srl %g1, 0x4, %g1 307 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl 308 309 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0 310 add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3 311 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry 312 b go_to_highmem 313 nop ! wheee.... 314 315 316/* Now do a non-relative jump so that PC is in high-memory */ 317go_to_highmem: 318 set execute_in_high_mem, %g1 319 jmpl %g1, %g0 320 nop 321 322/* The code above should be at beginning and we have to take care about 323 * short jumps, as branching to .init.text section from .text is usually 324 * impossible */ 325 __INIT 326/* Acquire boot time privileged register values, this will help debugging. 327 * I figure out and store nwindows and nwindowsm1 later on. 328 */ 329execute_in_high_mem: 330 mov %l0, %o0 ! put back romvec 331 mov %l1, %o1 ! and debug_vec 332 333 sethi %hi(prom_vector_p), %g1 334 st %o0, [%g1 + %lo(prom_vector_p)] 335 336 sethi %hi(linux_dbvec), %g1 337 st %o1, [%g1 + %lo(linux_dbvec)] 338 339/* Get the machine type via the mysterious romvec node operations. */ 340 341 add %g7, 0x1c, %l1 342 ld [%l1], %l0 343 ld [%l0], %l0 344 call %l0 345 or %g0, %g0, %o0 ! next_node(0) = first_node 346 or %o0, %g0, %g6 347 348 sethi %hi(cputypvar), %o1 ! First node has cpu-arch 349 or %o1, %lo(cputypvar), %o1 350 sethi %hi(cputypval), %o2 ! information, the string 351 or %o2, %lo(cputypval), %o2 352 ld [%l1], %l0 ! 'compatible' tells 353 ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where 354 call %l0 ! x is one of 'm', 'd' or 'e'. 355 nop ! %o2 holds pointer 356 ! to a buf where above string 357 ! will get stored by the prom. 358 359#ifdef CONFIG_SPARC_LEON 360 /* no cpu-type check is needed, it is a SPARC-LEON */ 361 362 sethi %hi(boot_cpu_id), %g2 ! boot-cpu index 363 364#ifdef CONFIG_SMP 365 ldub [%g2 + %lo(boot_cpu_id)], %g1 366 cmp %g1, 0xff ! unset means first CPU 367 bne leon_smp_cpu_startup ! continue only with master 368 nop 369#endif 370 /* Get CPU-ID from most significant 4-bit of ASR17 */ 371 rd %asr17, %g1 372 srl %g1, 28, %g1 373 374 /* Update boot_cpu_id only on boot cpu */ 375 stub %g1, [%g2 + %lo(boot_cpu_id)] 376 377 ba continue_boot 378 nop 379#endif 380 381/* Check to cputype. We may be booted on a sun4u (64 bit box), 382 * and sun4d needs special treatment. 383 */ 384 385 set cputypval, %o2 386 ldub [%o2 + 0x4], %l1 387 388 cmp %l1, 'm' 389 be sun4m_init 390 cmp %l1, 's' 391 be sun4m_init 392 cmp %l1, 'd' 393 be sun4d_init 394 cmp %l1, 'e' 395 be no_sun4e_here ! Could be a sun4e. 396 nop 397 b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :)) 398 nop 399 400/* CPUID in bootbus can be found at PA 0xff0140000 */ 401#define SUN4D_BOOTBUS_CPUID 0xf0140000 402 403sun4d_init: 404 /* Need to patch call to handler_irq */ 405 set patch_handler_irq, %g4 406 set sun4d_handler_irq, %g5 407 sethi %hi(0x40000000), %g3 ! call 408 sub %g5, %g4, %g5 409 srl %g5, 2, %g5 410 or %g5, %g3, %g5 411 st %g5, [%g4] 412 413#ifdef CONFIG_SMP 414 /* Get our CPU id out of bootbus */ 415 set SUN4D_BOOTBUS_CPUID, %g3 416 lduba [%g3] ASI_M_CTL, %g3 417 and %g3, 0xf8, %g3 418 srl %g3, 3, %g4 419 sta %g4, [%g0] ASI_M_VIKING_TMP1 420 sethi %hi(boot_cpu_id), %g5 421 stb %g4, [%g5 + %lo(boot_cpu_id)] 422#endif 423 424 /* Fall through to sun4m_init */ 425 426sun4m_init: 427/* Ok, the PROM could have done funny things and apple cider could still 428 * be sitting in the fault status/address registers. Read them all to 429 * clear them so we don't get magic faults later on. 430 */ 431/* This sucks, apparently this makes Vikings call prom panic, will fix later */ 4322: 433 rd %psr, %o1 434 srl %o1, 28, %o1 ! Get a type of the CPU 435 436 subcc %o1, 4, %g0 ! TI: Viking or MicroSPARC 437 be continue_boot 438 nop 439 440 set AC_M_SFSR, %o0 441 lda [%o0] ASI_M_MMUREGS, %g0 442 set AC_M_SFAR, %o0 443 lda [%o0] ASI_M_MMUREGS, %g0 444 445 /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */ 446 subcc %o1, 0, %g0 447 be continue_boot 448 nop 449 450 set AC_M_AFSR, %o0 451 lda [%o0] ASI_M_MMUREGS, %g0 452 set AC_M_AFAR, %o0 453 lda [%o0] ASI_M_MMUREGS, %g0 454 nop 455 456 457continue_boot: 458 459/* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's 460 * show-time! 461 */ 462 463 sethi %hi(cputyp), %o0 464 st %g4, [%o0 + %lo(cputyp)] 465 466 /* Turn on Supervisor, EnableFloating, and all the PIL bits. 467 * Also puts us in register window zero with traps off. 468 */ 469 set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2 470 wr %g2, 0x0, %psr 471 WRITE_PAUSE 472 473 /* I want a kernel stack NOW! */ 474 set init_thread_union, %g1 475 set (THREAD_SIZE - STACKFRAME_SZ), %g2 476 add %g1, %g2, %sp 477 mov 0, %fp /* And for good luck */ 478 479 /* Zero out our BSS section. */ 480 set __bss_start , %o0 ! First address of BSS 481 set _end , %o1 ! Last address of BSS 482 add %o0, 0x1, %o0 4831: 484 stb %g0, [%o0] 485 subcc %o0, %o1, %g0 486 bl 1b 487 add %o0, 0x1, %o0 488 489 /* If boot_cpu_id has not been setup by machine specific 490 * init-code above we default it to zero. 491 */ 492 sethi %hi(boot_cpu_id), %g2 493 ldub [%g2 + %lo(boot_cpu_id)], %g3 494 cmp %g3, 0xff 495 bne 1f 496 nop 497 mov %g0, %g3 498 stub %g3, [%g2 + %lo(boot_cpu_id)] 499 5001: sll %g3, 2, %g3 501 502 /* Initialize the uwinmask value for init task just in case. 503 * But first make current_set[boot_cpu_id] point to something useful. 504 */ 505 set init_thread_union, %g6 506 set current_set, %g2 507#ifdef CONFIG_SMP 508 st %g6, [%g2] 509 add %g2, %g3, %g2 510#endif 511 st %g6, [%g2] 512 513 st %g0, [%g6 + TI_UWINMASK] 514 515/* Compute NWINDOWS and stash it away. Now uses %wim trick explained 516 * in the V8 manual. Ok, this method seems to work, Sparc is cool... 517 * No, it doesn't work, have to play the save/readCWP/restore trick. 518 */ 519 520 wr %g0, 0x0, %wim ! so we do not get a trap 521 WRITE_PAUSE 522 523 save 524 525 rd %psr, %g3 526 527 restore 528 529 and %g3, 0x1f, %g3 530 add %g3, 0x1, %g3 531 532 mov 2, %g1 533 wr %g1, 0x0, %wim ! make window 1 invalid 534 WRITE_PAUSE 535 536 cmp %g3, 0x7 537 bne 2f 538 nop 539 540 /* Adjust our window handling routines to 541 * do things correctly on 7 window Sparcs. 542 */ 543 544#define PATCH_INSN(src, dest) \ 545 set src, %g5; \ 546 set dest, %g2; \ 547 ld [%g5], %g4; \ 548 st %g4, [%g2]; 549 550 /* Patch for window spills... */ 551 PATCH_INSN(spnwin_patch1_7win, spnwin_patch1) 552 PATCH_INSN(spnwin_patch2_7win, spnwin_patch2) 553 PATCH_INSN(spnwin_patch3_7win, spnwin_patch3) 554 555 /* Patch for window fills... */ 556 PATCH_INSN(fnwin_patch1_7win, fnwin_patch1) 557 PATCH_INSN(fnwin_patch2_7win, fnwin_patch2) 558 559 /* Patch for trap entry setup... */ 560 PATCH_INSN(tsetup_7win_patch1, tsetup_patch1) 561 PATCH_INSN(tsetup_7win_patch2, tsetup_patch2) 562 PATCH_INSN(tsetup_7win_patch3, tsetup_patch3) 563 PATCH_INSN(tsetup_7win_patch4, tsetup_patch4) 564 PATCH_INSN(tsetup_7win_patch5, tsetup_patch5) 565 PATCH_INSN(tsetup_7win_patch6, tsetup_patch6) 566 567 /* Patch for returning from traps... */ 568 PATCH_INSN(rtrap_7win_patch1, rtrap_patch1) 569 PATCH_INSN(rtrap_7win_patch2, rtrap_patch2) 570 PATCH_INSN(rtrap_7win_patch3, rtrap_patch3) 571 PATCH_INSN(rtrap_7win_patch4, rtrap_patch4) 572 PATCH_INSN(rtrap_7win_patch5, rtrap_patch5) 573 574 /* Patch for killing user windows from the register file. */ 575 PATCH_INSN(kuw_patch1_7win, kuw_patch1) 576 577 /* Now patch the kernel window flush sequences. 578 * This saves 2 traps on every switch and fork. 579 */ 580 set 0x01000000, %g4 581 set flush_patch_one, %g5 582 st %g4, [%g5 + 0x18] 583 st %g4, [%g5 + 0x1c] 584 set flush_patch_two, %g5 585 st %g4, [%g5 + 0x18] 586 st %g4, [%g5 + 0x1c] 587 set flush_patch_three, %g5 588 st %g4, [%g5 + 0x18] 589 st %g4, [%g5 + 0x1c] 590 set flush_patch_four, %g5 591 st %g4, [%g5 + 0x18] 592 st %g4, [%g5 + 0x1c] 593 set flush_patch_exception, %g5 594 st %g4, [%g5 + 0x18] 595 st %g4, [%g5 + 0x1c] 596 set flush_patch_switch, %g5 597 st %g4, [%g5 + 0x18] 598 st %g4, [%g5 + 0x1c] 599 6002: 601 sethi %hi(nwindows), %g4 602 st %g3, [%g4 + %lo(nwindows)] ! store final value 603 sub %g3, 0x1, %g3 604 sethi %hi(nwindowsm1), %g4 605 st %g3, [%g4 + %lo(nwindowsm1)] 606 607 /* Here we go, start using Linux's trap table... */ 608 set trapbase, %g3 609 wr %g3, 0x0, %tbr 610 WRITE_PAUSE 611 612 /* Finally, turn on traps so that we can call c-code. */ 613 rd %psr, %g3 614 wr %g3, 0x0, %psr 615 WRITE_PAUSE 616 617 wr %g3, PSR_ET, %psr 618 WRITE_PAUSE 619 620 /* First we call prom_init() to set up PROMLIB, then 621 * off to start_kernel(). 622 */ 623 624 sethi %hi(prom_vector_p), %g5 625 ld [%g5 + %lo(prom_vector_p)], %o0 626 call prom_init 627 nop 628 629 call start_kernel 630 nop 631 632 /* We should not get here. */ 633 call halt_me 634 nop 635 636no_sun4e_here: 637 ld [%g7 + 0x68], %o1 638 set sun4e_notsup, %o0 639 call %o1 640 nop 641 b halt_me 642 nop 643 644 __INITDATA 645 646sun4u_1: 647 .asciz "finddevice" 648 .align 4 649sun4u_2: 650 .asciz "/chosen" 651 .align 4 652sun4u_3: 653 .asciz "getprop" 654 .align 4 655sun4u_4: 656 .asciz "stdout" 657 .align 4 658sun4u_5: 659 .asciz "write" 660 .align 4 661sun4u_6: 662 .asciz "\n\rOn sun4u you have to use UltraLinux (64bit) kernel\n\rand not a 32bit sun4[cdem] version\n\r\n\r" 663sun4u_6e: 664 .align 4 665sun4u_7: 666 .asciz "exit" 667 .align 8 668sun4u_a1: 669 .word 0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0 670sun4u_r1: 671 .word 0 672sun4u_a2: 673 .word 0, sun4u_3, 0, 4, 0, 1, 0 674sun4u_i2: 675 .word 0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0 676sun4u_r2: 677 .word 0 678sun4u_a3: 679 .word 0, sun4u_5, 0, 3, 0, 1, 0 680sun4u_i3: 681 .word 0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0 682sun4u_r3: 683 .word 0 684sun4u_a4: 685 .word 0, sun4u_7, 0, 0, 0, 0 686sun4u_r4: 687 688 __INIT 689no_sun4u_here: 690 set sun4u_a1, %o0 691 set current_pc, %l2 692 cmp %l2, %g3 693 be 1f 694 mov %o4, %l0 695 sub %g3, %l2, %l6 696 add %o0, %l6, %o0 697 mov %o0, %l4 698 mov sun4u_r4 - sun4u_a1, %l3 699 ld [%l4], %l5 7002: 701 add %l4, 4, %l4 702 cmp %l5, %l2 703 add %l5, %l6, %l5 704 bgeu,a 3f 705 st %l5, [%l4 - 4] 7063: 707 subcc %l3, 4, %l3 708 bne 2b 709 ld [%l4], %l5 7101: 711 call %l0 712 mov %o0, %l1 713 714 ld [%l1 + (sun4u_r1 - sun4u_a1)], %o1 715 add %l1, (sun4u_a2 - sun4u_a1), %o0 716 call %l0 717 st %o1, [%o0 + (sun4u_i2 - sun4u_a2)] 718 719 ld [%l1 + (sun4u_1 - sun4u_a1)], %o1 720 add %l1, (sun4u_a3 - sun4u_a1), %o0 721 call %l0 722 st %o1, [%o0 + (sun4u_i3 - sun4u_a3)] 723 724 call %l0 725 add %l1, (sun4u_a4 - sun4u_a1), %o0 726 727 /* Not reached */ 728halt_me: 729 ld [%g7 + 0x74], %o0 730 call %o0 ! Get us out of here... 731 nop ! Apparently Solaris is better. 732 733/* Ok, now we continue in the .data/.text sections */ 734 735 .data 736 .align 4 737 738/* 739 * Fill up the prom vector, note in particular the kind first element, 740 * no joke. I don't need all of them in here as the entire prom vector 741 * gets initialized in c-code so all routines can use it. 742 */ 743 744prom_vector_p: 745 .word 0 746 747/* We calculate the following at boot time, window fills/spills and trap entry 748 * code uses these to keep track of the register windows. 749 */ 750 751 .align 4 752 .globl nwindows 753 .globl nwindowsm1 754nwindows: 755 .word 8 756nwindowsm1: 757 .word 7 758 759/* Boot time debugger vector value. We need this later on. */ 760 761 .align 4 762 .globl linux_dbvec 763linux_dbvec: 764 .word 0 765 .word 0 766 767 .align 8 768 769 .globl lvl14_save 770lvl14_save: 771 .word 0 772 .word 0 773 .word 0 774 .word 0 775 .word t_irq14 776 777 .section ".fixup",#alloc,#execinstr 778 .globl __ret_efault 779__ret_efault: 780 ret 781 restore %g0, -EFAULT, %o0 782