1/* 2 * etrap.S: Preparing for entry into the kernel on Sparc V9. 3 * 4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz) 6 */ 7 8 9#include <asm/asi.h> 10#include <asm/pstate.h> 11#include <asm/ptrace.h> 12#include <asm/page.h> 13#include <asm/spitfire.h> 14#include <asm/head.h> 15#include <asm/processor.h> 16#include <asm/mmu.h> 17 18#define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ) 19#define ETRAP_PSTATE1 (PSTATE_TSO | PSTATE_PRIV) 20#define ETRAP_PSTATE2 \ 21 (PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE) 22 23/* 24 * On entry, %g7 is return address - 0x4. 25 * %g4 and %g5 will be preserved %l4 and %l5 respectively. 26 */ 27 28 .text 29 .align 64 30 .globl etrap_syscall, etrap, etrap_irq, etraptl1 31etrap: rdpr %pil, %g2 32etrap_irq: clr %g3 33etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1) 34 rdpr %tstate, %g1 35 or %g1, %g3, %g1 36 sllx %g2, 20, %g3 37 andcc %g1, TSTATE_PRIV, %g0 38 or %g1, %g3, %g1 39 bne,pn %xcc, 1f 40 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2 41661: wrpr %g0, 7, %cleanwin 42 .section .fast_win_ctrl_1insn_patch, "ax" 43 .word 661b 44 .word 0x85880000 ! allclean 45 .previous 46 47 sethi %hi(TASK_REGOFF), %g2 48 sethi %hi(TSTATE_PEF), %g3 49 or %g2, %lo(TASK_REGOFF), %g2 50 and %g1, %g3, %g3 51 brnz,pn %g3, 1f 52 add %g6, %g2, %g2 53 wr %g0, 0, %fprs 541: rdpr %tpc, %g3 55 56 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE] 57 rdpr %tnpc, %g1 58 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC] 59 rd %y, %g3 60 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC] 61 rdpr %tt, %g1 62 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y] 63 sethi %hi(PT_REGS_MAGIC), %g3 64 or %g3, %g1, %g1 65 st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC] 66 67 rdpr %cansave, %g1 68 brnz,pt %g1, etrap_save 69 nop 70 71 rdpr %cwp, %g1 72 add %g1, 2, %g1 73 wrpr %g1, %cwp 74 be,pt %xcc, etrap_user_spill 75 mov ASI_AIUP, %g3 76 77 rdpr %otherwin, %g3 78 brz %g3, etrap_kernel_spill 79 mov ASI_AIUS, %g3 80 81etrap_user_spill: 82 83 wr %g3, 0x0, %asi 84 ldx [%g6 + TI_FLAGS], %g3 85 and %g3, _TIF_32BIT, %g3 86 brnz,pt %g3, etrap_user_spill_32bit 87 nop 88 ba,a,pt %xcc, etrap_user_spill_64bit 89 90etrap_save: save %g2, -STACK_BIAS, %sp 91 mov %g6, %l6 92 93 bne,pn %xcc, 3f 94 mov PRIMARY_CONTEXT, %l4 95661: rdpr %canrestore, %g3 96 .section .fast_win_ctrl_1insn_patch, "ax" 97 .word 661b 98 nop 99 .previous 100 101 rdpr %wstate, %g2 102661: wrpr %g0, 0, %canrestore 103 .section .fast_win_ctrl_1insn_patch, "ax" 104 .word 661b 105 nop 106 .previous 107 sll %g2, 3, %g2 108 109 /* Set TI_SYS_FPDEPTH to 1 and clear TI_SYS_NOERROR. */ 110 mov 1, %l5 111 sth %l5, [%l6 + TI_SYS_NOERROR] 112 113661: wrpr %g3, 0, %otherwin 114 .section .fast_win_ctrl_1insn_patch, "ax" 115 .word 661b 116 .word 0x87880000 ! otherw 117 .previous 118 119 wrpr %g2, 0, %wstate 120 sethi %hi(sparc64_kern_pri_context), %g2 121 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3 122 123661: stxa %g3, [%l4] ASI_DMMU 124 .section .sun4v_1insn_patch, "ax" 125 .word 661b 126 stxa %g3, [%l4] ASI_MMU 127 .previous 128 129 sethi %hi(KERNBASE), %l4 130 flush %l4 131 mov ASI_AIUS, %l7 1322: mov %g4, %l4 133 mov %g5, %l5 134 add %g7, 4, %l2 135 136 /* Go to trap time globals so we can save them. */ 137661: wrpr %g0, ETRAP_PSTATE1, %pstate 138 .section .sun4v_1insn_patch, "ax" 139 .word 661b 140 SET_GL(0) 141 .previous 142 143 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1] 144 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2] 145 sllx %l7, 24, %l7 146 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3] 147 rdpr %cwp, %l0 148 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4] 149 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5] 150 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6] 151 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7] 152 or %l7, %l0, %l7 153 sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0 154 or %l7, %l0, %l7 155 wrpr %l2, %tnpc 156 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate 157 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0] 158 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1] 159 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2] 160 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3] 161 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4] 162 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5] 163 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6] 164 mov %l6, %g6 165 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] 166 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1) 167 ldx [%g6 + TI_TASK], %g4 168 done 169 1703: mov ASI_P, %l7 171 ldub [%l6 + TI_FPDEPTH], %l5 172 add %l6, TI_FPSAVED + 1, %l4 173 srl %l5, 1, %l3 174 add %l5, 2, %l5 175 176 /* Set TI_SYS_FPDEPTH to %l5 and clear TI_SYS_NOERROR. */ 177 sth %l5, [%l6 + TI_SYS_NOERROR] 178 ba,pt %xcc, 2b 179 stb %g0, [%l4 + %l3] 180 nop 181 182etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself. 183 * We place this right after pt_regs on the trap stack. 184 * The layout is: 185 * 0x00 TL1's TSTATE 186 * 0x08 TL1's TPC 187 * 0x10 TL1's TNPC 188 * 0x18 TL1's TT 189 * ... 190 * 0x58 TL4's TT 191 * 0x60 TL 192 */ 193 TRAP_LOAD_THREAD_REG(%g6, %g1) 194 sub %sp, ((4 * 8) * 4) + 8, %g2 195 rdpr %tl, %g1 196 197 wrpr %g0, 1, %tl 198 rdpr %tstate, %g3 199 stx %g3, [%g2 + STACK_BIAS + 0x00] 200 rdpr %tpc, %g3 201 stx %g3, [%g2 + STACK_BIAS + 0x08] 202 rdpr %tnpc, %g3 203 stx %g3, [%g2 + STACK_BIAS + 0x10] 204 rdpr %tt, %g3 205 stx %g3, [%g2 + STACK_BIAS + 0x18] 206 207 wrpr %g0, 2, %tl 208 rdpr %tstate, %g3 209 stx %g3, [%g2 + STACK_BIAS + 0x20] 210 rdpr %tpc, %g3 211 stx %g3, [%g2 + STACK_BIAS + 0x28] 212 rdpr %tnpc, %g3 213 stx %g3, [%g2 + STACK_BIAS + 0x30] 214 rdpr %tt, %g3 215 stx %g3, [%g2 + STACK_BIAS + 0x38] 216 217 sethi %hi(is_sun4v), %g3 218 lduw [%g3 + %lo(is_sun4v)], %g3 219 brnz,pn %g3, finish_tl1_capture 220 nop 221 222 wrpr %g0, 3, %tl 223 rdpr %tstate, %g3 224 stx %g3, [%g2 + STACK_BIAS + 0x40] 225 rdpr %tpc, %g3 226 stx %g3, [%g2 + STACK_BIAS + 0x48] 227 rdpr %tnpc, %g3 228 stx %g3, [%g2 + STACK_BIAS + 0x50] 229 rdpr %tt, %g3 230 stx %g3, [%g2 + STACK_BIAS + 0x58] 231 232 wrpr %g0, 4, %tl 233 rdpr %tstate, %g3 234 stx %g3, [%g2 + STACK_BIAS + 0x60] 235 rdpr %tpc, %g3 236 stx %g3, [%g2 + STACK_BIAS + 0x68] 237 rdpr %tnpc, %g3 238 stx %g3, [%g2 + STACK_BIAS + 0x70] 239 rdpr %tt, %g3 240 stx %g3, [%g2 + STACK_BIAS + 0x78] 241 242 stx %g1, [%g2 + STACK_BIAS + 0x80] 243 244finish_tl1_capture: 245 wrpr %g0, 1, %tl 246661: nop 247 .section .sun4v_1insn_patch, "ax" 248 .word 661b 249 SET_GL(1) 250 .previous 251 252 rdpr %tstate, %g1 253 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2 254 ba,pt %xcc, 1b 255 andcc %g1, TSTATE_PRIV, %g0 256 257#undef TASK_REGOFF 258#undef ETRAP_PSTATE1 259