1/* arch/sparc/kernel/entry.S: Sparc trap low-level entry points. 2 * 3 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net) 4 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) 6 * Copyright (C) 1996-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au) 8 */ 9 10#include <linux/linkage.h> 11#include <linux/errno.h> 12 13#include <asm/head.h> 14#include <asm/asi.h> 15#include <asm/smp.h> 16#include <asm/contregs.h> 17#include <asm/ptrace.h> 18#include <asm/asm-offsets.h> 19#include <asm/psr.h> 20#include <asm/vaddrs.h> 21#include <asm/page.h> 22#include <asm/pgtable.h> 23#include <asm/winmacro.h> 24#include <asm/signal.h> 25#include <asm/obio.h> 26#include <asm/mxcc.h> 27#include <asm/thread_info.h> 28#include <asm/param.h> 29#include <asm/unistd.h> 30 31#include <asm/asmmacro.h> 32 33#define curptr g6 34 35/* These are just handy. */ 36#define _SV save %sp, -STACKFRAME_SZ, %sp 37#define _RS restore 38 39#define FLUSH_ALL_KERNEL_WINDOWS \ 40 _SV; _SV; _SV; _SV; _SV; _SV; _SV; \ 41 _RS; _RS; _RS; _RS; _RS; _RS; _RS; 42 43 .text 44 45#ifdef CONFIG_KGDB 46 .align 4 47 .globl arch_kgdb_breakpoint 48 .type arch_kgdb_breakpoint,#function 49arch_kgdb_breakpoint: 50 ta 0x7d 51 retl 52 nop 53 .size arch_kgdb_breakpoint,.-arch_kgdb_breakpoint 54#endif 55 56#if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE) 57 .align 4 58 .globl floppy_hardint 59floppy_hardint: 60 /* 61 * This code cannot touch registers %l0 %l1 and %l2 62 * because SAVE_ALL depends on their values. It depends 63 * on %l3 also, but we regenerate it before a call. 64 * Other registers are: 65 * %l3 -- base address of fdc registers 66 * %l4 -- pdma_vaddr 67 * %l5 -- scratch for ld/st address 68 * %l6 -- pdma_size 69 * %l7 -- scratch [floppy byte, ld/st address, aux. data] 70 */ 71 72 /* Do we have work to do? */ 73 sethi %hi(doing_pdma), %l7 74 ld [%l7 + %lo(doing_pdma)], %l7 75 cmp %l7, 0 76 be floppy_dosoftint 77 nop 78 79 /* Load fdc register base */ 80 sethi %hi(fdc_status), %l3 81 ld [%l3 + %lo(fdc_status)], %l3 82 83 /* Setup register addresses */ 84 sethi %hi(pdma_vaddr), %l5 ! transfer buffer 85 ld [%l5 + %lo(pdma_vaddr)], %l4 86 sethi %hi(pdma_size), %l5 ! bytes to go 87 ld [%l5 + %lo(pdma_size)], %l6 88next_byte: 89 ldub [%l3], %l7 90 91 andcc %l7, 0x80, %g0 ! Does fifo still have data 92 bz floppy_fifo_emptied ! fifo has been emptied... 93 andcc %l7, 0x20, %g0 ! in non-dma mode still? 94 bz floppy_overrun ! nope, overrun 95 andcc %l7, 0x40, %g0 ! 0=write 1=read 96 bz floppy_write 97 sub %l6, 0x1, %l6 98 99 /* Ok, actually read this byte */ 100 ldub [%l3 + 1], %l7 101 orcc %g0, %l6, %g0 102 stb %l7, [%l4] 103 bne next_byte 104 add %l4, 0x1, %l4 105 106 b floppy_tdone 107 nop 108 109floppy_write: 110 /* Ok, actually write this byte */ 111 ldub [%l4], %l7 112 orcc %g0, %l6, %g0 113 stb %l7, [%l3 + 1] 114 bne next_byte 115 add %l4, 0x1, %l4 116 117 /* fall through... */ 118floppy_tdone: 119 sethi %hi(pdma_vaddr), %l5 120 st %l4, [%l5 + %lo(pdma_vaddr)] 121 sethi %hi(pdma_size), %l5 122 st %l6, [%l5 + %lo(pdma_size)] 123 /* Flip terminal count pin */ 124 set auxio_register, %l7 125 ld [%l7], %l7 126 127 ldub [%l7], %l5 128 129 or %l5, 0xc2, %l5 130 stb %l5, [%l7] 131 andn %l5, 0x02, %l5 132 1332: 134 /* Kill some time so the bits set */ 135 WRITE_PAUSE 136 WRITE_PAUSE 137 138 stb %l5, [%l7] 139 140 /* Prevent recursion */ 141 sethi %hi(doing_pdma), %l7 142 b floppy_dosoftint 143 st %g0, [%l7 + %lo(doing_pdma)] 144 145 /* We emptied the FIFO, but we haven't read everything 146 * as of yet. Store the current transfer address and 147 * bytes left to read so we can continue when the next 148 * fast IRQ comes in. 149 */ 150floppy_fifo_emptied: 151 sethi %hi(pdma_vaddr), %l5 152 st %l4, [%l5 + %lo(pdma_vaddr)] 153 sethi %hi(pdma_size), %l7 154 st %l6, [%l7 + %lo(pdma_size)] 155 156 /* Restore condition codes */ 157 wr %l0, 0x0, %psr 158 WRITE_PAUSE 159 160 jmp %l1 161 rett %l2 162 163floppy_overrun: 164 sethi %hi(pdma_vaddr), %l5 165 st %l4, [%l5 + %lo(pdma_vaddr)] 166 sethi %hi(pdma_size), %l5 167 st %l6, [%l5 + %lo(pdma_size)] 168 /* Prevent recursion */ 169 sethi %hi(doing_pdma), %l7 170 st %g0, [%l7 + %lo(doing_pdma)] 171 172 /* fall through... */ 173floppy_dosoftint: 174 rd %wim, %l3 175 SAVE_ALL 176 177 /* Set all IRQs off. */ 178 or %l0, PSR_PIL, %l4 179 wr %l4, 0x0, %psr 180 WRITE_PAUSE 181 wr %l4, PSR_ET, %psr 182 WRITE_PAUSE 183 184 mov 11, %o0 ! floppy irq level (unused anyway) 185 mov %g0, %o1 ! devid is not used in fast interrupts 186 call sparc_floppy_irq 187 add %sp, STACKFRAME_SZ, %o2 ! struct pt_regs *regs 188 189 RESTORE_ALL 190 191#endif /* (CONFIG_BLK_DEV_FD) */ 192 193 /* Bad trap handler */ 194 .globl bad_trap_handler 195bad_trap_handler: 196 SAVE_ALL 197 198 wr %l0, PSR_ET, %psr 199 WRITE_PAUSE 200 201 add %sp, STACKFRAME_SZ, %o0 ! pt_regs 202 call do_hw_interrupt 203 mov %l7, %o1 ! trap number 204 205 RESTORE_ALL 206 207/* For now all IRQ's not registered get sent here. handler_irq() will 208 * see if a routine is registered to handle this interrupt and if not 209 * it will say so on the console. 210 */ 211 212 .align 4 213 .globl real_irq_entry, patch_handler_irq 214real_irq_entry: 215 SAVE_ALL 216 217#ifdef CONFIG_SMP 218 .globl patchme_maybe_smp_msg 219 220 cmp %l7, 11 221patchme_maybe_smp_msg: 222 bgu maybe_smp4m_msg 223 nop 224#endif 225 226real_irq_continue: 227 or %l0, PSR_PIL, %g2 228 wr %g2, 0x0, %psr 229 WRITE_PAUSE 230 wr %g2, PSR_ET, %psr 231 WRITE_PAUSE 232 mov %l7, %o0 ! irq level 233patch_handler_irq: 234 call handler_irq 235 add %sp, STACKFRAME_SZ, %o1 ! pt_regs ptr 236 or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq 237 wr %g2, PSR_ET, %psr ! keep ET up 238 WRITE_PAUSE 239 240 RESTORE_ALL 241 242#ifdef CONFIG_SMP 243 /* SMP per-cpu ticker interrupts are handled specially. */ 244smp4m_ticker: 245 bne real_irq_continue+4 246 or %l0, PSR_PIL, %g2 247 wr %g2, 0x0, %psr 248 WRITE_PAUSE 249 wr %g2, PSR_ET, %psr 250 WRITE_PAUSE 251 call smp4m_percpu_timer_interrupt 252 add %sp, STACKFRAME_SZ, %o0 253 wr %l0, PSR_ET, %psr 254 WRITE_PAUSE 255 RESTORE_ALL 256 257#define GET_PROCESSOR4M_ID(reg) \ 258 rd %tbr, %reg; \ 259 srl %reg, 12, %reg; \ 260 and %reg, 3, %reg; 261 262 /* Here is where we check for possible SMP IPI passed to us 263 * on some level other than 15 which is the NMI and only used 264 * for cross calls. That has a separate entry point below. 265 * 266 * IPIs are sent on Level 12, 13 and 14. See IRQ_IPI_*. 267 */ 268maybe_smp4m_msg: 269 GET_PROCESSOR4M_ID(o3) 270 sethi %hi(sun4m_irq_percpu), %l5 271 sll %o3, 2, %o3 272 or %l5, %lo(sun4m_irq_percpu), %o5 273 sethi %hi(0x70000000), %o2 ! Check all soft-IRQs 274 ld [%o5 + %o3], %o1 275 ld [%o1 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending 276 andcc %o3, %o2, %g0 277 be,a smp4m_ticker 278 cmp %l7, 14 279 /* Soft-IRQ IPI */ 280 st %o2, [%o1 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x70000000 281 WRITE_PAUSE 282 ld [%o1 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending 283 WRITE_PAUSE 284 or %l0, PSR_PIL, %l4 285 wr %l4, 0x0, %psr 286 WRITE_PAUSE 287 wr %l4, PSR_ET, %psr 288 WRITE_PAUSE 289 srl %o3, 28, %o2 ! shift for simpler checks below 290maybe_smp4m_msg_check_single: 291 andcc %o2, 0x1, %g0 292 beq,a maybe_smp4m_msg_check_mask 293 andcc %o2, 0x2, %g0 294 call smp_call_function_single_interrupt 295 nop 296 andcc %o2, 0x2, %g0 297maybe_smp4m_msg_check_mask: 298 beq,a maybe_smp4m_msg_check_resched 299 andcc %o2, 0x4, %g0 300 call smp_call_function_interrupt 301 nop 302 andcc %o2, 0x4, %g0 303maybe_smp4m_msg_check_resched: 304 /* rescheduling is done in RESTORE_ALL regardless, but incr stats */ 305 beq,a maybe_smp4m_msg_out 306 nop 307 call smp_resched_interrupt 308 nop 309maybe_smp4m_msg_out: 310 RESTORE_ALL 311 312 .align 4 313 .globl linux_trap_ipi15_sun4m 314linux_trap_ipi15_sun4m: 315 SAVE_ALL 316 sethi %hi(0x80000000), %o2 317 GET_PROCESSOR4M_ID(o0) 318 sethi %hi(sun4m_irq_percpu), %l5 319 or %l5, %lo(sun4m_irq_percpu), %o5 320 sll %o0, 2, %o0 321 ld [%o5 + %o0], %o5 322 ld [%o5 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending 323 andcc %o3, %o2, %g0 324 be sun4m_nmi_error ! Must be an NMI async memory error 325 st %o2, [%o5 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x80000000 326 WRITE_PAUSE 327 ld [%o5 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending 328 WRITE_PAUSE 329 or %l0, PSR_PIL, %l4 330 wr %l4, 0x0, %psr 331 WRITE_PAUSE 332 wr %l4, PSR_ET, %psr 333 WRITE_PAUSE 334 call smp4m_cross_call_irq 335 nop 336 b ret_trap_lockless_ipi 337 clr %l6 338 339 .globl smp4d_ticker 340 /* SMP per-cpu ticker interrupts are handled specially. */ 341smp4d_ticker: 342 SAVE_ALL 343 or %l0, PSR_PIL, %g2 344 sethi %hi(CC_ICLR), %o0 345 sethi %hi(1 << 14), %o1 346 or %o0, %lo(CC_ICLR), %o0 347 stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 14 in MXCC's ICLR */ 348 wr %g2, 0x0, %psr 349 WRITE_PAUSE 350 wr %g2, PSR_ET, %psr 351 WRITE_PAUSE 352 call smp4d_percpu_timer_interrupt 353 add %sp, STACKFRAME_SZ, %o0 354 wr %l0, PSR_ET, %psr 355 WRITE_PAUSE 356 RESTORE_ALL 357 358 .align 4 359 .globl linux_trap_ipi15_sun4d 360linux_trap_ipi15_sun4d: 361 SAVE_ALL 362 sethi %hi(CC_BASE), %o4 363 sethi %hi(MXCC_ERR_ME|MXCC_ERR_PEW|MXCC_ERR_ASE|MXCC_ERR_PEE), %o2 364 or %o4, (CC_EREG - CC_BASE), %o0 365 ldda [%o0] ASI_M_MXCC, %o0 366 andcc %o0, %o2, %g0 367 bne 1f 368 sethi %hi(BB_STAT2), %o2 369 lduba [%o2] ASI_M_CTL, %o2 370 andcc %o2, BB_STAT2_MASK, %g0 371 bne 2f 372 or %o4, (CC_ICLR - CC_BASE), %o0 373 sethi %hi(1 << 15), %o1 374 stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 15 in MXCC's ICLR */ 375 or %l0, PSR_PIL, %l4 376 wr %l4, 0x0, %psr 377 WRITE_PAUSE 378 wr %l4, PSR_ET, %psr 379 WRITE_PAUSE 380 call smp4d_cross_call_irq 381 nop 382 b ret_trap_lockless_ipi 383 clr %l6 384 3851: /* MXCC error */ 3862: /* BB error */ 387 /* Disable PIL 15 */ 388 set CC_IMSK, %l4 389 lduha [%l4] ASI_M_MXCC, %l5 390 sethi %hi(1 << 15), %l7 391 or %l5, %l7, %l5 392 stha %l5, [%l4] ASI_M_MXCC 393 /* FIXME */ 3941: b,a 1b 395 396 .globl smpleon_ipi 397 .extern leon_ipi_interrupt 398 /* SMP per-cpu IPI interrupts are handled specially. */ 399smpleon_ipi: 400 SAVE_ALL 401 or %l0, PSR_PIL, %g2 402 wr %g2, 0x0, %psr 403 WRITE_PAUSE 404 wr %g2, PSR_ET, %psr 405 WRITE_PAUSE 406 call leonsmp_ipi_interrupt 407 add %sp, STACKFRAME_SZ, %o1 ! pt_regs 408 wr %l0, PSR_ET, %psr 409 WRITE_PAUSE 410 RESTORE_ALL 411 412 .align 4 413 .globl linux_trap_ipi15_leon 414linux_trap_ipi15_leon: 415 SAVE_ALL 416 or %l0, PSR_PIL, %l4 417 wr %l4, 0x0, %psr 418 WRITE_PAUSE 419 wr %l4, PSR_ET, %psr 420 WRITE_PAUSE 421 call leon_cross_call_irq 422 nop 423 b ret_trap_lockless_ipi 424 clr %l6 425 426#endif /* CONFIG_SMP */ 427 428 /* This routine handles illegal instructions and privileged 429 * instruction attempts from user code. 430 */ 431 .align 4 432 .globl bad_instruction 433bad_instruction: 434 sethi %hi(0xc1f80000), %l4 435 ld [%l1], %l5 436 sethi %hi(0x81d80000), %l7 437 and %l5, %l4, %l5 438 cmp %l5, %l7 439 be 1f 440 SAVE_ALL 441 442 wr %l0, PSR_ET, %psr ! re-enable traps 443 WRITE_PAUSE 444 445 add %sp, STACKFRAME_SZ, %o0 446 mov %l1, %o1 447 mov %l2, %o2 448 call do_illegal_instruction 449 mov %l0, %o3 450 451 RESTORE_ALL 452 4531: /* unimplemented flush - just skip */ 454 jmpl %l2, %g0 455 rett %l2 + 4 456 457 .align 4 458 .globl priv_instruction 459priv_instruction: 460 SAVE_ALL 461 462 wr %l0, PSR_ET, %psr 463 WRITE_PAUSE 464 465 add %sp, STACKFRAME_SZ, %o0 466 mov %l1, %o1 467 mov %l2, %o2 468 call do_priv_instruction 469 mov %l0, %o3 470 471 RESTORE_ALL 472 473 /* This routine handles unaligned data accesses. */ 474 .align 4 475 .globl mna_handler 476mna_handler: 477 andcc %l0, PSR_PS, %g0 478 be mna_fromuser 479 nop 480 481 SAVE_ALL 482 483 wr %l0, PSR_ET, %psr 484 WRITE_PAUSE 485 486 ld [%l1], %o1 487 call kernel_unaligned_trap 488 add %sp, STACKFRAME_SZ, %o0 489 490 RESTORE_ALL 491 492mna_fromuser: 493 SAVE_ALL 494 495 wr %l0, PSR_ET, %psr ! re-enable traps 496 WRITE_PAUSE 497 498 ld [%l1], %o1 499 call user_unaligned_trap 500 add %sp, STACKFRAME_SZ, %o0 501 502 RESTORE_ALL 503 504 /* This routine handles floating point disabled traps. */ 505 .align 4 506 .globl fpd_trap_handler 507fpd_trap_handler: 508 SAVE_ALL 509 510 wr %l0, PSR_ET, %psr ! re-enable traps 511 WRITE_PAUSE 512 513 add %sp, STACKFRAME_SZ, %o0 514 mov %l1, %o1 515 mov %l2, %o2 516 call do_fpd_trap 517 mov %l0, %o3 518 519 RESTORE_ALL 520 521 /* This routine handles Floating Point Exceptions. */ 522 .align 4 523 .globl fpe_trap_handler 524fpe_trap_handler: 525 set fpsave_magic, %l5 526 cmp %l1, %l5 527 be 1f 528 sethi %hi(fpsave), %l5 529 or %l5, %lo(fpsave), %l5 530 cmp %l1, %l5 531 bne 2f 532 sethi %hi(fpsave_catch2), %l5 533 or %l5, %lo(fpsave_catch2), %l5 534 wr %l0, 0x0, %psr 535 WRITE_PAUSE 536 jmp %l5 537 rett %l5 + 4 5381: 539 sethi %hi(fpsave_catch), %l5 540 or %l5, %lo(fpsave_catch), %l5 541 wr %l0, 0x0, %psr 542 WRITE_PAUSE 543 jmp %l5 544 rett %l5 + 4 545 5462: 547 SAVE_ALL 548 549 wr %l0, PSR_ET, %psr ! re-enable traps 550 WRITE_PAUSE 551 552 add %sp, STACKFRAME_SZ, %o0 553 mov %l1, %o1 554 mov %l2, %o2 555 call do_fpe_trap 556 mov %l0, %o3 557 558 RESTORE_ALL 559 560 /* This routine handles Tag Overflow Exceptions. */ 561 .align 4 562 .globl do_tag_overflow 563do_tag_overflow: 564 SAVE_ALL 565 566 wr %l0, PSR_ET, %psr ! re-enable traps 567 WRITE_PAUSE 568 569 add %sp, STACKFRAME_SZ, %o0 570 mov %l1, %o1 571 mov %l2, %o2 572 call handle_tag_overflow 573 mov %l0, %o3 574 575 RESTORE_ALL 576 577 /* This routine handles Watchpoint Exceptions. */ 578 .align 4 579 .globl do_watchpoint 580do_watchpoint: 581 SAVE_ALL 582 583 wr %l0, PSR_ET, %psr ! re-enable traps 584 WRITE_PAUSE 585 586 add %sp, STACKFRAME_SZ, %o0 587 mov %l1, %o1 588 mov %l2, %o2 589 call handle_watchpoint 590 mov %l0, %o3 591 592 RESTORE_ALL 593 594 /* This routine handles Register Access Exceptions. */ 595 .align 4 596 .globl do_reg_access 597do_reg_access: 598 SAVE_ALL 599 600 wr %l0, PSR_ET, %psr ! re-enable traps 601 WRITE_PAUSE 602 603 add %sp, STACKFRAME_SZ, %o0 604 mov %l1, %o1 605 mov %l2, %o2 606 call handle_reg_access 607 mov %l0, %o3 608 609 RESTORE_ALL 610 611 /* This routine handles Co-Processor Disabled Exceptions. */ 612 .align 4 613 .globl do_cp_disabled 614do_cp_disabled: 615 SAVE_ALL 616 617 wr %l0, PSR_ET, %psr ! re-enable traps 618 WRITE_PAUSE 619 620 add %sp, STACKFRAME_SZ, %o0 621 mov %l1, %o1 622 mov %l2, %o2 623 call handle_cp_disabled 624 mov %l0, %o3 625 626 RESTORE_ALL 627 628 /* This routine handles Co-Processor Exceptions. */ 629 .align 4 630 .globl do_cp_exception 631do_cp_exception: 632 SAVE_ALL 633 634 wr %l0, PSR_ET, %psr ! re-enable traps 635 WRITE_PAUSE 636 637 add %sp, STACKFRAME_SZ, %o0 638 mov %l1, %o1 639 mov %l2, %o2 640 call handle_cp_exception 641 mov %l0, %o3 642 643 RESTORE_ALL 644 645 /* This routine handles Hardware Divide By Zero Exceptions. */ 646 .align 4 647 .globl do_hw_divzero 648do_hw_divzero: 649 SAVE_ALL 650 651 wr %l0, PSR_ET, %psr ! re-enable traps 652 WRITE_PAUSE 653 654 add %sp, STACKFRAME_SZ, %o0 655 mov %l1, %o1 656 mov %l2, %o2 657 call handle_hw_divzero 658 mov %l0, %o3 659 660 RESTORE_ALL 661 662 .align 4 663 .globl do_flush_windows 664do_flush_windows: 665 SAVE_ALL 666 667 wr %l0, PSR_ET, %psr 668 WRITE_PAUSE 669 670 andcc %l0, PSR_PS, %g0 671 bne dfw_kernel 672 nop 673 674 call flush_user_windows 675 nop 676 677 /* Advance over the trap instruction. */ 678 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 679 add %l1, 0x4, %l2 680 st %l1, [%sp + STACKFRAME_SZ + PT_PC] 681 st %l2, [%sp + STACKFRAME_SZ + PT_NPC] 682 683 RESTORE_ALL 684 685 .globl flush_patch_one 686 687 /* We get these for debugging routines using __builtin_return_address() */ 688dfw_kernel: 689flush_patch_one: 690 FLUSH_ALL_KERNEL_WINDOWS 691 692 /* Advance over the trap instruction. */ 693 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 694 add %l1, 0x4, %l2 695 st %l1, [%sp + STACKFRAME_SZ + PT_PC] 696 st %l2, [%sp + STACKFRAME_SZ + PT_NPC] 697 698 RESTORE_ALL 699 700 /* The getcc software trap. The user wants the condition codes from 701 * the %psr in register %g1. 702 */ 703 704 .align 4 705 .globl getcc_trap_handler 706getcc_trap_handler: 707 srl %l0, 20, %g1 ! give user 708 and %g1, 0xf, %g1 ! only ICC bits in %psr 709 jmp %l2 ! advance over trap instruction 710 rett %l2 + 0x4 ! like this... 711 712 /* The setcc software trap. The user has condition codes in %g1 713 * that it would like placed in the %psr. Be careful not to flip 714 * any unintentional bits! 715 */ 716 717 .align 4 718 .globl setcc_trap_handler 719setcc_trap_handler: 720 sll %g1, 0x14, %l4 721 set PSR_ICC, %l5 722 andn %l0, %l5, %l0 ! clear ICC bits in %psr 723 and %l4, %l5, %l4 ! clear non-ICC bits in user value 724 or %l4, %l0, %l4 ! or them in... mix mix mix 725 726 wr %l4, 0x0, %psr ! set new %psr 727 WRITE_PAUSE ! TI scumbags... 728 729 jmp %l2 ! advance over trap instruction 730 rett %l2 + 0x4 ! like this... 731 732sun4m_nmi_error: 733 /* NMI async memory error handling. */ 734 sethi %hi(0x80000000), %l4 735 sethi %hi(sun4m_irq_global), %o5 736 ld [%o5 + %lo(sun4m_irq_global)], %l5 737 st %l4, [%l5 + 0x0c] ! sun4m_irq_global->mask_set=0x80000000 738 WRITE_PAUSE 739 ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending 740 WRITE_PAUSE 741 or %l0, PSR_PIL, %l4 742 wr %l4, 0x0, %psr 743 WRITE_PAUSE 744 wr %l4, PSR_ET, %psr 745 WRITE_PAUSE 746 call sun4m_nmi 747 nop 748 st %l4, [%l5 + 0x08] ! sun4m_irq_global->mask_clear=0x80000000 749 WRITE_PAUSE 750 ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending 751 WRITE_PAUSE 752 RESTORE_ALL 753 754#ifndef CONFIG_SMP 755 .align 4 756 .globl linux_trap_ipi15_sun4m 757linux_trap_ipi15_sun4m: 758 SAVE_ALL 759 760 ba sun4m_nmi_error 761 nop 762#endif /* CONFIG_SMP */ 763 764 .align 4 765 .globl srmmu_fault 766srmmu_fault: 767 mov 0x400, %l5 768 mov 0x300, %l4 769 770LEON_PI(lda [%l5] ASI_LEON_MMUREGS, %l6) ! read sfar first 771SUN_PI_(lda [%l5] ASI_M_MMUREGS, %l6) ! read sfar first 772 773LEON_PI(lda [%l4] ASI_LEON_MMUREGS, %l5) ! read sfsr last 774SUN_PI_(lda [%l4] ASI_M_MMUREGS, %l5) ! read sfsr last 775 776 andn %l6, 0xfff, %l6 777 srl %l5, 6, %l5 ! and encode all info into l7 778 779 and %l5, 2, %l5 780 or %l5, %l6, %l6 781 782 or %l6, %l7, %l7 ! l7 = [addr,write,txtfault] 783 784 SAVE_ALL 785 786 mov %l7, %o1 787 mov %l7, %o2 788 and %o1, 1, %o1 ! arg2 = text_faultp 789 mov %l7, %o3 790 and %o2, 2, %o2 ! arg3 = writep 791 andn %o3, 0xfff, %o3 ! arg4 = faulting address 792 793 wr %l0, PSR_ET, %psr 794 WRITE_PAUSE 795 796 call do_sparc_fault 797 add %sp, STACKFRAME_SZ, %o0 ! arg1 = pt_regs ptr 798 799 RESTORE_ALL 800 801 .align 4 802 .globl sys_nis_syscall 803sys_nis_syscall: 804 mov %o7, %l5 805 add %sp, STACKFRAME_SZ, %o0 ! pt_regs *regs arg 806 call c_sys_nis_syscall 807 mov %l5, %o7 808 809 .align 4 810 .globl sys_execve 811sys_execve: 812 mov %o7, %l5 813 add %sp, STACKFRAME_SZ, %o0 ! pt_regs *regs arg 814 call sparc_execve 815 mov %l5, %o7 816 817 .globl sunos_execv 818sunos_execv: 819 st %g0, [%sp + STACKFRAME_SZ + PT_I2] 820 821 call sparc_execve 822 add %sp, STACKFRAME_SZ, %o0 823 824 b ret_sys_call 825 ld [%sp + STACKFRAME_SZ + PT_I0], %o0 826 827 .align 4 828 .globl sys_sparc_pipe 829sys_sparc_pipe: 830 mov %o7, %l5 831 add %sp, STACKFRAME_SZ, %o0 ! pt_regs *regs arg 832 call sparc_pipe 833 mov %l5, %o7 834 835 .align 4 836 .globl sys_sigaltstack 837sys_sigaltstack: 838 mov %o7, %l5 839 mov %fp, %o2 840 call do_sigaltstack 841 mov %l5, %o7 842 843 .align 4 844 .globl sys_sigstack 845sys_sigstack: 846 mov %o7, %l5 847 mov %fp, %o2 848 call do_sys_sigstack 849 mov %l5, %o7 850 851 .align 4 852 .globl sys_sigreturn 853sys_sigreturn: 854 call do_sigreturn 855 add %sp, STACKFRAME_SZ, %o0 856 857 ld [%curptr + TI_FLAGS], %l5 858 andcc %l5, _TIF_SYSCALL_TRACE, %g0 859 be 1f 860 nop 861 862 call syscall_trace 863 nop 864 8651: 866 /* We don't want to muck with user registers like a 867 * normal syscall, just return. 868 */ 869 RESTORE_ALL 870 871 .align 4 872 .globl sys_rt_sigreturn 873sys_rt_sigreturn: 874 call do_rt_sigreturn 875 add %sp, STACKFRAME_SZ, %o0 876 877 ld [%curptr + TI_FLAGS], %l5 878 andcc %l5, _TIF_SYSCALL_TRACE, %g0 879 be 1f 880 nop 881 882 add %sp, STACKFRAME_SZ, %o0 883 call syscall_trace 884 mov 1, %o1 885 8861: 887 /* We are returning to a signal handler. */ 888 RESTORE_ALL 889 890 /* Now that we have a real sys_clone, sys_fork() is 891 * implemented in terms of it. Our _real_ implementation 892 * of SunOS vfork() will use sys_vfork(). 893 * 894 * XXX These three should be consolidated into mostly shared 895 * XXX code just like on sparc64... -DaveM 896 */ 897 .align 4 898 .globl sys_fork, flush_patch_two 899sys_fork: 900 mov %o7, %l5 901flush_patch_two: 902 FLUSH_ALL_KERNEL_WINDOWS; 903 ld [%curptr + TI_TASK], %o4 904 rd %psr, %g4 905 WRITE_PAUSE 906 mov SIGCHLD, %o0 ! arg0: clone flags 907 rd %wim, %g5 908 WRITE_PAUSE 909 mov %fp, %o1 ! arg1: usp 910 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr] 911 add %sp, STACKFRAME_SZ, %o2 ! arg2: pt_regs ptr 912 mov 0, %o3 913 call sparc_do_fork 914 mov %l5, %o7 915 916 /* Whee, kernel threads! */ 917 .globl sys_clone, flush_patch_three 918sys_clone: 919 mov %o7, %l5 920flush_patch_three: 921 FLUSH_ALL_KERNEL_WINDOWS; 922 ld [%curptr + TI_TASK], %o4 923 rd %psr, %g4 924 WRITE_PAUSE 925 926 /* arg0,1: flags,usp -- loaded already */ 927 cmp %o1, 0x0 ! Is new_usp NULL? 928 rd %wim, %g5 929 WRITE_PAUSE 930 be,a 1f 931 mov %fp, %o1 ! yes, use callers usp 932 andn %o1, 7, %o1 ! no, align to 8 bytes 9331: 934 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr] 935 add %sp, STACKFRAME_SZ, %o2 ! arg2: pt_regs ptr 936 mov 0, %o3 937 call sparc_do_fork 938 mov %l5, %o7 939 940 /* Whee, real vfork! */ 941 .globl sys_vfork, flush_patch_four 942sys_vfork: 943flush_patch_four: 944 FLUSH_ALL_KERNEL_WINDOWS; 945 ld [%curptr + TI_TASK], %o4 946 rd %psr, %g4 947 WRITE_PAUSE 948 rd %wim, %g5 949 WRITE_PAUSE 950 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr] 951 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0 952 mov %fp, %o1 953 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0 954 sethi %hi(sparc_do_fork), %l1 955 mov 0, %o3 956 jmpl %l1 + %lo(sparc_do_fork), %g0 957 add %sp, STACKFRAME_SZ, %o2 958 959 .align 4 960linux_sparc_ni_syscall: 961 sethi %hi(sys_ni_syscall), %l7 962 b syscall_is_too_hard 963 or %l7, %lo(sys_ni_syscall), %l7 964 965linux_fast_syscall: 966 andn %l7, 3, %l7 967 mov %i0, %o0 968 mov %i1, %o1 969 mov %i2, %o2 970 jmpl %l7 + %g0, %g0 971 mov %i3, %o3 972 973linux_syscall_trace: 974 add %sp, STACKFRAME_SZ, %o0 975 call syscall_trace 976 mov 0, %o1 977 cmp %o0, 0 978 bne 3f 979 mov -ENOSYS, %o0 980 mov %i0, %o0 981 mov %i1, %o1 982 mov %i2, %o2 983 mov %i3, %o3 984 b 2f 985 mov %i4, %o4 986 987 .globl ret_from_fork 988ret_from_fork: 989 call schedule_tail 990 ld [%g3 + TI_TASK], %o0 991 b ret_sys_call 992 ld [%sp + STACKFRAME_SZ + PT_I0], %o0 993 994 /* Linux native system calls enter here... */ 995 .align 4 996 .globl linux_sparc_syscall 997linux_sparc_syscall: 998 sethi %hi(PSR_SYSCALL), %l4 999 or %l0, %l4, %l0 1000 /* Direct access to user regs, must faster. */ 1001 cmp %g1, NR_syscalls 1002 bgeu linux_sparc_ni_syscall 1003 sll %g1, 2, %l4 1004 ld [%l7 + %l4], %l7 1005 andcc %l7, 1, %g0 1006 bne linux_fast_syscall 1007 /* Just do first insn from SAVE_ALL in the delay slot */ 1008 1009syscall_is_too_hard: 1010 SAVE_ALL_HEAD 1011 rd %wim, %l3 1012 1013 wr %l0, PSR_ET, %psr 1014 mov %i0, %o0 1015 mov %i1, %o1 1016 mov %i2, %o2 1017 1018 ld [%curptr + TI_FLAGS], %l5 1019 mov %i3, %o3 1020 andcc %l5, _TIF_SYSCALL_TRACE, %g0 1021 mov %i4, %o4 1022 bne linux_syscall_trace 1023 mov %i0, %l5 10242: 1025 call %l7 1026 mov %i5, %o5 1027 10283: 1029 st %o0, [%sp + STACKFRAME_SZ + PT_I0] 1030 1031ret_sys_call: 1032 ld [%curptr + TI_FLAGS], %l6 1033 cmp %o0, -ERESTART_RESTARTBLOCK 1034 ld [%sp + STACKFRAME_SZ + PT_PSR], %g3 1035 set PSR_C, %g2 1036 bgeu 1f 1037 andcc %l6, _TIF_SYSCALL_TRACE, %g0 1038 1039 /* System call success, clear Carry condition code. */ 1040 andn %g3, %g2, %g3 1041 clr %l6 1042 st %g3, [%sp + STACKFRAME_SZ + PT_PSR] 1043 bne linux_syscall_trace2 1044 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 /* pc = npc */ 1045 add %l1, 0x4, %l2 /* npc = npc+4 */ 1046 st %l1, [%sp + STACKFRAME_SZ + PT_PC] 1047 b ret_trap_entry 1048 st %l2, [%sp + STACKFRAME_SZ + PT_NPC] 10491: 1050 /* System call failure, set Carry condition code. 1051 * Also, get abs(errno) to return to the process. 1052 */ 1053 sub %g0, %o0, %o0 1054 or %g3, %g2, %g3 1055 st %o0, [%sp + STACKFRAME_SZ + PT_I0] 1056 mov 1, %l6 1057 st %g3, [%sp + STACKFRAME_SZ + PT_PSR] 1058 bne linux_syscall_trace2 1059 ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 /* pc = npc */ 1060 add %l1, 0x4, %l2 /* npc = npc+4 */ 1061 st %l1, [%sp + STACKFRAME_SZ + PT_PC] 1062 b ret_trap_entry 1063 st %l2, [%sp + STACKFRAME_SZ + PT_NPC] 1064 1065linux_syscall_trace2: 1066 add %sp, STACKFRAME_SZ, %o0 1067 mov 1, %o1 1068 call syscall_trace 1069 add %l1, 0x4, %l2 /* npc = npc+4 */ 1070 st %l1, [%sp + STACKFRAME_SZ + PT_PC] 1071 b ret_trap_entry 1072 st %l2, [%sp + STACKFRAME_SZ + PT_NPC] 1073 1074 1075/* Saving and restoring the FPU state is best done from lowlevel code. 1076 * 1077 * void fpsave(unsigned long *fpregs, unsigned long *fsr, 1078 * void *fpqueue, unsigned long *fpqdepth) 1079 */ 1080 1081 .globl fpsave 1082fpsave: 1083 st %fsr, [%o1] ! this can trap on us if fpu is in bogon state 1084 ld [%o1], %g1 1085 set 0x2000, %g4 1086 andcc %g1, %g4, %g0 1087 be 2f 1088 mov 0, %g2 1089 1090 /* We have an fpqueue to save. */ 10911: 1092 std %fq, [%o2] 1093fpsave_magic: 1094 st %fsr, [%o1] 1095 ld [%o1], %g3 1096 andcc %g3, %g4, %g0 1097 add %g2, 1, %g2 1098 bne 1b 1099 add %o2, 8, %o2 1100 11012: 1102 st %g2, [%o3] 1103 1104 std %f0, [%o0 + 0x00] 1105 std %f2, [%o0 + 0x08] 1106 std %f4, [%o0 + 0x10] 1107 std %f6, [%o0 + 0x18] 1108 std %f8, [%o0 + 0x20] 1109 std %f10, [%o0 + 0x28] 1110 std %f12, [%o0 + 0x30] 1111 std %f14, [%o0 + 0x38] 1112 std %f16, [%o0 + 0x40] 1113 std %f18, [%o0 + 0x48] 1114 std %f20, [%o0 + 0x50] 1115 std %f22, [%o0 + 0x58] 1116 std %f24, [%o0 + 0x60] 1117 std %f26, [%o0 + 0x68] 1118 std %f28, [%o0 + 0x70] 1119 retl 1120 std %f30, [%o0 + 0x78] 1121 1122 /* Thanks for Theo Deraadt and the authors of the Sprite/netbsd/openbsd 1123 * code for pointing out this possible deadlock, while we save state 1124 * above we could trap on the fsr store so our low level fpu trap 1125 * code has to know how to deal with this. 1126 */ 1127fpsave_catch: 1128 b fpsave_magic + 4 1129 st %fsr, [%o1] 1130 1131fpsave_catch2: 1132 b fpsave + 4 1133 st %fsr, [%o1] 1134 1135 /* void fpload(unsigned long *fpregs, unsigned long *fsr); */ 1136 1137 .globl fpload 1138fpload: 1139 ldd [%o0 + 0x00], %f0 1140 ldd [%o0 + 0x08], %f2 1141 ldd [%o0 + 0x10], %f4 1142 ldd [%o0 + 0x18], %f6 1143 ldd [%o0 + 0x20], %f8 1144 ldd [%o0 + 0x28], %f10 1145 ldd [%o0 + 0x30], %f12 1146 ldd [%o0 + 0x38], %f14 1147 ldd [%o0 + 0x40], %f16 1148 ldd [%o0 + 0x48], %f18 1149 ldd [%o0 + 0x50], %f20 1150 ldd [%o0 + 0x58], %f22 1151 ldd [%o0 + 0x60], %f24 1152 ldd [%o0 + 0x68], %f26 1153 ldd [%o0 + 0x70], %f28 1154 ldd [%o0 + 0x78], %f30 1155 ld [%o1], %fsr 1156 retl 1157 nop 1158 1159 /* __ndelay and __udelay take two arguments: 1160 * 0 - nsecs or usecs to delay 1161 * 1 - per_cpu udelay_val (loops per jiffy) 1162 * 1163 * Note that ndelay gives HZ times higher resolution but has a 10ms 1164 * limit. udelay can handle up to 1s. 1165 */ 1166 .globl __ndelay 1167__ndelay: 1168 save %sp, -STACKFRAME_SZ, %sp 1169 mov %i0, %o0 ! round multiplier up so large ns ok 1170 mov 0x1ae, %o1 ! 2**32 / (1 000 000 000 / HZ) 1171 umul %o0, %o1, %o0 1172 rd %y, %o1 1173 mov %i1, %o1 ! udelay_val 1174 umul %o0, %o1, %o0 1175 rd %y, %o1 1176 ba delay_continue 1177 mov %o1, %o0 ! >>32 later for better resolution 1178 1179 .globl __udelay 1180__udelay: 1181 save %sp, -STACKFRAME_SZ, %sp 1182 mov %i0, %o0 1183 sethi %hi(0x10c7), %o1 ! round multiplier up so large us ok 1184 or %o1, %lo(0x10c7), %o1 ! 2**32 / 1 000 000 1185 umul %o0, %o1, %o0 1186 rd %y, %o1 1187 mov %i1, %o1 ! udelay_val 1188 umul %o0, %o1, %o0 1189 rd %y, %o1 1190 sethi %hi(0x028f4b62), %l0 ! Add in rounding constant * 2**32, 1191 or %g0, %lo(0x028f4b62), %l0 1192 addcc %o0, %l0, %o0 ! 2**32 * 0.009 999 1193 bcs,a 3f 1194 add %o1, 0x01, %o1 11953: 1196 mov HZ, %o0 ! >>32 earlier for wider range 1197 umul %o0, %o1, %o0 1198 rd %y, %o1 1199 1200delay_continue: 1201 cmp %o0, 0x0 12021: 1203 bne 1b 1204 subcc %o0, 1, %o0 1205 1206 ret 1207 restore 1208 1209 /* Handle a software breakpoint */ 1210 /* We have to inform parent that child has stopped */ 1211 .align 4 1212 .globl breakpoint_trap 1213breakpoint_trap: 1214 rd %wim,%l3 1215 SAVE_ALL 1216 wr %l0, PSR_ET, %psr 1217 WRITE_PAUSE 1218 1219 st %i0, [%sp + STACKFRAME_SZ + PT_G0] ! for restarting syscalls 1220 call sparc_breakpoint 1221 add %sp, STACKFRAME_SZ, %o0 1222 1223 RESTORE_ALL 1224 1225#ifdef CONFIG_KGDB 1226 .align 4 1227 .globl kgdb_trap_low 1228 .type kgdb_trap_low,#function 1229kgdb_trap_low: 1230 rd %wim,%l3 1231 SAVE_ALL 1232 wr %l0, PSR_ET, %psr 1233 WRITE_PAUSE 1234 1235 call kgdb_trap 1236 add %sp, STACKFRAME_SZ, %o0 1237 1238 RESTORE_ALL 1239 .size kgdb_trap_low,.-kgdb_trap_low 1240#endif 1241 1242 .align 4 1243 .globl flush_patch_exception 1244flush_patch_exception: 1245 FLUSH_ALL_KERNEL_WINDOWS; 1246 ldd [%o0], %o6 1247 jmpl %o7 + 0xc, %g0 ! see asm-sparc/processor.h 1248 mov 1, %g1 ! signal EFAULT condition 1249 1250 .align 4 1251 .globl kill_user_windows, kuw_patch1_7win 1252 .globl kuw_patch1 1253kuw_patch1_7win: sll %o3, 6, %o3 1254 1255 /* No matter how much overhead this routine has in the worst 1256 * case scenerio, it is several times better than taking the 1257 * traps with the old method of just doing flush_user_windows(). 1258 */ 1259kill_user_windows: 1260 ld [%g6 + TI_UWINMASK], %o0 ! get current umask 1261 orcc %g0, %o0, %g0 ! if no bits set, we are done 1262 be 3f ! nothing to do 1263 rd %psr, %o5 ! must clear interrupts 1264 or %o5, PSR_PIL, %o4 ! or else that could change 1265 wr %o4, 0x0, %psr ! the uwinmask state 1266 WRITE_PAUSE ! burn them cycles 12671: 1268 ld [%g6 + TI_UWINMASK], %o0 ! get consistent state 1269 orcc %g0, %o0, %g0 ! did an interrupt come in? 1270 be 4f ! yep, we are done 1271 rd %wim, %o3 ! get current wim 1272 srl %o3, 1, %o4 ! simulate a save 1273kuw_patch1: 1274 sll %o3, 7, %o3 ! compute next wim 1275 or %o4, %o3, %o3 ! result 1276 andncc %o0, %o3, %o0 ! clean this bit in umask 1277 bne kuw_patch1 ! not done yet 1278 srl %o3, 1, %o4 ! begin another save simulation 1279 wr %o3, 0x0, %wim ! set the new wim 1280 st %g0, [%g6 + TI_UWINMASK] ! clear uwinmask 12814: 1282 wr %o5, 0x0, %psr ! re-enable interrupts 1283 WRITE_PAUSE ! burn baby burn 12843: 1285 retl ! return 1286 st %g0, [%g6 + TI_W_SAVED] ! no windows saved 1287 1288 .align 4 1289 .globl restore_current 1290restore_current: 1291 LOAD_CURRENT(g6, o0) 1292 retl 1293 nop 1294 1295#ifdef CONFIG_PCIC_PCI 1296#include <asm/pcic.h> 1297 1298 .align 4 1299 .globl linux_trap_ipi15_pcic 1300linux_trap_ipi15_pcic: 1301 rd %wim, %l3 1302 SAVE_ALL 1303 1304 /* 1305 * First deactivate NMI 1306 * or we cannot drop ET, cannot get window spill traps. 1307 * The busy loop is necessary because the PIO error 1308 * sometimes does not go away quickly and we trap again. 1309 */ 1310 sethi %hi(pcic_regs), %o1 1311 ld [%o1 + %lo(pcic_regs)], %o2 1312 1313 ! Get pending status for printouts later. 1314 ld [%o2 + PCI_SYS_INT_PENDING], %o0 1315 1316 mov PCI_SYS_INT_PENDING_CLEAR_ALL, %o1 1317 stb %o1, [%o2 + PCI_SYS_INT_PENDING_CLEAR] 13181: 1319 ld [%o2 + PCI_SYS_INT_PENDING], %o1 1320 andcc %o1, ((PCI_SYS_INT_PENDING_PIO|PCI_SYS_INT_PENDING_PCI)>>24), %g0 1321 bne 1b 1322 nop 1323 1324 or %l0, PSR_PIL, %l4 1325 wr %l4, 0x0, %psr 1326 WRITE_PAUSE 1327 wr %l4, PSR_ET, %psr 1328 WRITE_PAUSE 1329 1330 call pcic_nmi 1331 add %sp, STACKFRAME_SZ, %o1 ! struct pt_regs *regs 1332 RESTORE_ALL 1333 1334 .globl pcic_nmi_trap_patch 1335pcic_nmi_trap_patch: 1336 sethi %hi(linux_trap_ipi15_pcic), %l3 1337 jmpl %l3 + %lo(linux_trap_ipi15_pcic), %g0 1338 rd %psr, %l0 1339 .word 0 1340 1341#endif /* CONFIG_PCIC_PCI */ 1342 1343 .globl flushw_all 1344flushw_all: 1345 save %sp, -0x40, %sp 1346 save %sp, -0x40, %sp 1347 save %sp, -0x40, %sp 1348 save %sp, -0x40, %sp 1349 save %sp, -0x40, %sp 1350 save %sp, -0x40, %sp 1351 save %sp, -0x40, %sp 1352 restore 1353 restore 1354 restore 1355 restore 1356 restore 1357 restore 1358 ret 1359 restore 1360 1361#ifdef CONFIG_SMP 1362ENTRY(hard_smp_processor_id) 1363661: rd %tbr, %g1 1364 srl %g1, 12, %o0 1365 and %o0, 3, %o0 1366 .section .cpuid_patch, "ax" 1367 /* Instruction location. */ 1368 .word 661b 1369 /* SUN4D implementation. */ 1370 lda [%g0] ASI_M_VIKING_TMP1, %o0 1371 nop 1372 nop 1373 /* LEON implementation. */ 1374 rd %asr17, %o0 1375 srl %o0, 0x1c, %o0 1376 nop 1377 .previous 1378 retl 1379 nop 1380ENDPROC(hard_smp_processor_id) 1381#endif 1382 1383/* End of entry.S */ 1384