1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2d34dd829SSam Ravnborg /* cpu.c: Dinky routines to look for the kind of Sparc cpu
3d34dd829SSam Ravnborg * we are on.
4d34dd829SSam Ravnborg *
5d34dd829SSam Ravnborg * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
6d34dd829SSam Ravnborg */
7d34dd829SSam Ravnborg
8cb1b8209SSam Ravnborg #include <linux/seq_file.h>
9d34dd829SSam Ravnborg #include <linux/kernel.h>
10066bcacaSPaul Gortmaker #include <linux/export.h>
11d34dd829SSam Ravnborg #include <linux/init.h>
12d34dd829SSam Ravnborg #include <linux/smp.h>
13d34dd829SSam Ravnborg #include <linux/threads.h>
14*65fddcfcSMike Rapoport #include <linux/pgtable.h>
15d34dd829SSam Ravnborg
16d34dd829SSam Ravnborg #include <asm/spitfire.h>
17d34dd829SSam Ravnborg #include <asm/oplib.h>
18cb1b8209SSam Ravnborg #include <asm/setup.h>
19d34dd829SSam Ravnborg #include <asm/page.h>
20d34dd829SSam Ravnborg #include <asm/head.h>
21d34dd829SSam Ravnborg #include <asm/psr.h>
22d34dd829SSam Ravnborg #include <asm/mbus.h>
23d34dd829SSam Ravnborg #include <asm/cpudata.h>
24d34dd829SSam Ravnborg
25d34dd829SSam Ravnborg #include "kernel.h"
26fd250a66SSam Ravnborg #include "entry.h"
27d34dd829SSam Ravnborg
28d34dd829SSam Ravnborg DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
296943f3daSSam Ravnborg EXPORT_PER_CPU_SYMBOL(__cpu_data);
30d34dd829SSam Ravnborg
31cb1b8209SSam Ravnborg int ncpus_probed;
32cb1b8209SSam Ravnborg unsigned int fsr_storage;
33cb1b8209SSam Ravnborg
34d34dd829SSam Ravnborg struct cpu_info {
35d34dd829SSam Ravnborg int psr_vers;
36d34dd829SSam Ravnborg const char *name;
37c3cf5e8cSDavid S. Miller const char *pmu_name;
38d34dd829SSam Ravnborg };
39d34dd829SSam Ravnborg
40d34dd829SSam Ravnborg struct fpu_info {
41d34dd829SSam Ravnborg int fp_vers;
42d34dd829SSam Ravnborg const char *name;
43d34dd829SSam Ravnborg };
44d34dd829SSam Ravnborg
45d34dd829SSam Ravnborg #define NOCPU 8
46d34dd829SSam Ravnborg #define NOFPU 8
47d34dd829SSam Ravnborg
48d34dd829SSam Ravnborg struct manufacturer_info {
49d34dd829SSam Ravnborg int psr_impl;
50d34dd829SSam Ravnborg struct cpu_info cpu_info[NOCPU];
51d34dd829SSam Ravnborg struct fpu_info fpu_info[NOFPU];
52d34dd829SSam Ravnborg };
53d34dd829SSam Ravnborg
54d34dd829SSam Ravnborg #define CPU(ver, _name) \
55d34dd829SSam Ravnborg { .psr_vers = ver, .name = _name }
56d34dd829SSam Ravnborg
57c3cf5e8cSDavid S. Miller #define CPU_PMU(ver, _name, _pmu_name) \
58c3cf5e8cSDavid S. Miller { .psr_vers = ver, .name = _name, .pmu_name = _pmu_name }
59c3cf5e8cSDavid S. Miller
60d34dd829SSam Ravnborg #define FPU(ver, _name) \
61d34dd829SSam Ravnborg { .fp_vers = ver, .name = _name }
62d34dd829SSam Ravnborg
63d34dd829SSam Ravnborg static const struct manufacturer_info __initconst manufacturer_info[] = {
64d34dd829SSam Ravnborg {
65d34dd829SSam Ravnborg 0,
66d34dd829SSam Ravnborg /* Sun4/100, 4/200, SLC */
67d34dd829SSam Ravnborg .cpu_info = {
68d34dd829SSam Ravnborg CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"),
69d34dd829SSam Ravnborg /* borned STP1012PGA */
70d34dd829SSam Ravnborg CPU(4, "Fujitsu MB86904"),
71d34dd829SSam Ravnborg CPU(5, "Fujitsu TurboSparc MB86907"),
72d34dd829SSam Ravnborg CPU(-1, NULL)
73d34dd829SSam Ravnborg },
74d34dd829SSam Ravnborg .fpu_info = {
75d34dd829SSam Ravnborg FPU(0, "Fujitsu MB86910 or Weitek WTL1164/5"),
76d34dd829SSam Ravnborg FPU(1, "Fujitsu MB86911 or Weitek WTL1164/5 or LSI L64831"),
77d34dd829SSam Ravnborg FPU(2, "LSI Logic L64802 or Texas Instruments ACT8847"),
78d34dd829SSam Ravnborg /* SparcStation SLC, SparcStation1 */
79d34dd829SSam Ravnborg FPU(3, "Weitek WTL3170/2"),
80d34dd829SSam Ravnborg /* SPARCstation-5 */
81d34dd829SSam Ravnborg FPU(4, "Lsi Logic/Meiko L64804 or compatible"),
82d34dd829SSam Ravnborg FPU(-1, NULL)
83d34dd829SSam Ravnborg }
84d34dd829SSam Ravnborg },{
85d34dd829SSam Ravnborg 1,
86d34dd829SSam Ravnborg .cpu_info = {
87d34dd829SSam Ravnborg /* SparcStation2, SparcServer 490 & 690 */
88d34dd829SSam Ravnborg CPU(0, "LSI Logic Corporation - L64811"),
89d34dd829SSam Ravnborg /* SparcStation2 */
90d34dd829SSam Ravnborg CPU(1, "Cypress/ROSS CY7C601"),
91d34dd829SSam Ravnborg /* Embedded controller */
92d34dd829SSam Ravnborg CPU(3, "Cypress/ROSS CY7C611"),
93d34dd829SSam Ravnborg /* Ross Technologies HyperSparc */
94d34dd829SSam Ravnborg CPU(0xf, "ROSS HyperSparc RT620"),
95d34dd829SSam Ravnborg CPU(0xe, "ROSS HyperSparc RT625 or RT626"),
96d34dd829SSam Ravnborg CPU(-1, NULL)
97d34dd829SSam Ravnborg },
98d34dd829SSam Ravnborg .fpu_info = {
99d34dd829SSam Ravnborg FPU(0, "ROSS HyperSparc combined IU/FPU"),
100d34dd829SSam Ravnborg FPU(1, "Lsi Logic L64814"),
101d34dd829SSam Ravnborg FPU(2, "Texas Instruments TMS390-C602A"),
102d34dd829SSam Ravnborg FPU(3, "Cypress CY7C602 FPU"),
103d34dd829SSam Ravnborg FPU(-1, NULL)
104d34dd829SSam Ravnborg }
105d34dd829SSam Ravnborg },{
106d34dd829SSam Ravnborg 2,
107d34dd829SSam Ravnborg .cpu_info = {
108d34dd829SSam Ravnborg /* ECL Implementation, CRAY S-MP Supercomputer... AIEEE! */
109d34dd829SSam Ravnborg /* Someone please write the code to support this beast! ;) */
110d34dd829SSam Ravnborg CPU(0, "Bipolar Integrated Technology - B5010"),
111d34dd829SSam Ravnborg CPU(-1, NULL)
112d34dd829SSam Ravnborg },
113d34dd829SSam Ravnborg .fpu_info = {
114d34dd829SSam Ravnborg FPU(-1, NULL)
115d34dd829SSam Ravnborg }
116d34dd829SSam Ravnborg },{
117d34dd829SSam Ravnborg 3,
118d34dd829SSam Ravnborg .cpu_info = {
119d34dd829SSam Ravnborg CPU(0, "LSI Logic Corporation - unknown-type"),
120d34dd829SSam Ravnborg CPU(-1, NULL)
121d34dd829SSam Ravnborg },
122d34dd829SSam Ravnborg .fpu_info = {
123d34dd829SSam Ravnborg FPU(-1, NULL)
124d34dd829SSam Ravnborg }
125d34dd829SSam Ravnborg },{
126d87d8c11SSam Ravnborg PSR_IMPL_TI,
127d34dd829SSam Ravnborg .cpu_info = {
128d34dd829SSam Ravnborg CPU(0, "Texas Instruments, Inc. - SuperSparc-(II)"),
129d34dd829SSam Ravnborg /* SparcClassic -- borned STP1010TAB-50*/
130d34dd829SSam Ravnborg CPU(1, "Texas Instruments, Inc. - MicroSparc"),
131d34dd829SSam Ravnborg CPU(2, "Texas Instruments, Inc. - MicroSparc II"),
132d34dd829SSam Ravnborg CPU(3, "Texas Instruments, Inc. - SuperSparc 51"),
133d34dd829SSam Ravnborg CPU(4, "Texas Instruments, Inc. - SuperSparc 61"),
134d34dd829SSam Ravnborg CPU(5, "Texas Instruments, Inc. - unknown"),
135d34dd829SSam Ravnborg CPU(-1, NULL)
136d34dd829SSam Ravnborg },
137d34dd829SSam Ravnborg .fpu_info = {
138d34dd829SSam Ravnborg /* SuperSparc 50 module */
139d34dd829SSam Ravnborg FPU(0, "SuperSparc on-chip FPU"),
140d34dd829SSam Ravnborg /* SparcClassic */
141d34dd829SSam Ravnborg FPU(4, "TI MicroSparc on chip FPU"),
142d34dd829SSam Ravnborg FPU(-1, NULL)
143d34dd829SSam Ravnborg }
144d34dd829SSam Ravnborg },{
145d34dd829SSam Ravnborg 5,
146d34dd829SSam Ravnborg .cpu_info = {
147d34dd829SSam Ravnborg CPU(0, "Matsushita - MN10501"),
148d34dd829SSam Ravnborg CPU(-1, NULL)
149d34dd829SSam Ravnborg },
150d34dd829SSam Ravnborg .fpu_info = {
151d34dd829SSam Ravnborg FPU(0, "Matsushita MN10501"),
152d34dd829SSam Ravnborg FPU(-1, NULL)
153d34dd829SSam Ravnborg }
154d34dd829SSam Ravnborg },{
155d34dd829SSam Ravnborg 6,
156d34dd829SSam Ravnborg .cpu_info = {
157d34dd829SSam Ravnborg CPU(0, "Philips Corporation - unknown"),
158d34dd829SSam Ravnborg CPU(-1, NULL)
159d34dd829SSam Ravnborg },
160d34dd829SSam Ravnborg .fpu_info = {
161d34dd829SSam Ravnborg FPU(-1, NULL)
162d34dd829SSam Ravnborg }
163d34dd829SSam Ravnborg },{
164d34dd829SSam Ravnborg 7,
165d34dd829SSam Ravnborg .cpu_info = {
166d34dd829SSam Ravnborg CPU(0, "Harvest VLSI Design Center, Inc. - unknown"),
167d34dd829SSam Ravnborg CPU(-1, NULL)
168d34dd829SSam Ravnborg },
169d34dd829SSam Ravnborg .fpu_info = {
170d34dd829SSam Ravnborg FPU(-1, NULL)
171d34dd829SSam Ravnborg }
172d34dd829SSam Ravnborg },{
173d34dd829SSam Ravnborg 8,
174d34dd829SSam Ravnborg .cpu_info = {
175d34dd829SSam Ravnborg CPU(0, "Systems and Processes Engineering Corporation (SPEC)"),
176d34dd829SSam Ravnborg CPU(-1, NULL)
177d34dd829SSam Ravnborg },
178d34dd829SSam Ravnborg .fpu_info = {
179d34dd829SSam Ravnborg FPU(-1, NULL)
180d34dd829SSam Ravnborg }
181d34dd829SSam Ravnborg },{
182d34dd829SSam Ravnborg 9,
183d34dd829SSam Ravnborg .cpu_info = {
184d34dd829SSam Ravnborg /* Gallium arsenide 200MHz, BOOOOGOOOOMIPS!!! */
185d34dd829SSam Ravnborg CPU(0, "Fujitsu or Weitek Power-UP"),
186d34dd829SSam Ravnborg CPU(1, "Fujitsu or Weitek Power-UP"),
187d34dd829SSam Ravnborg CPU(2, "Fujitsu or Weitek Power-UP"),
188d34dd829SSam Ravnborg CPU(3, "Fujitsu or Weitek Power-UP"),
189d34dd829SSam Ravnborg CPU(-1, NULL)
190d34dd829SSam Ravnborg },
191d34dd829SSam Ravnborg .fpu_info = {
192d34dd829SSam Ravnborg FPU(3, "Fujitsu or Weitek on-chip FPU"),
193d34dd829SSam Ravnborg FPU(-1, NULL)
194d34dd829SSam Ravnborg }
195d34dd829SSam Ravnborg },{
196d87d8c11SSam Ravnborg PSR_IMPL_LEON, /* Aeroflex Gaisler */
1973560f788SKristoffer Glembo .cpu_info = {
1983560f788SKristoffer Glembo CPU(3, "LEON"),
1993560f788SKristoffer Glembo CPU(-1, NULL)
2003560f788SKristoffer Glembo },
2013560f788SKristoffer Glembo .fpu_info = {
2023560f788SKristoffer Glembo FPU(2, "GRFPU"),
2033560f788SKristoffer Glembo FPU(3, "GRFPU-Lite"),
2043560f788SKristoffer Glembo FPU(-1, NULL)
2053560f788SKristoffer Glembo }
2063560f788SKristoffer Glembo },{
207d34dd829SSam Ravnborg 0x17,
208d34dd829SSam Ravnborg .cpu_info = {
209c3cf5e8cSDavid S. Miller CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
210c3cf5e8cSDavid S. Miller CPU_PMU(0x11, "TI UltraSparc II (BlackBird)", "ultra12"),
211c3cf5e8cSDavid S. Miller CPU_PMU(0x12, "TI UltraSparc IIi (Sabre)", "ultra12"),
212c3cf5e8cSDavid S. Miller CPU_PMU(0x13, "TI UltraSparc IIe (Hummingbird)", "ultra12"),
213d34dd829SSam Ravnborg CPU(-1, NULL)
214d34dd829SSam Ravnborg },
215d34dd829SSam Ravnborg .fpu_info = {
216d34dd829SSam Ravnborg FPU(0x10, "UltraSparc I integrated FPU"),
217d34dd829SSam Ravnborg FPU(0x11, "UltraSparc II integrated FPU"),
218d34dd829SSam Ravnborg FPU(0x12, "UltraSparc IIi integrated FPU"),
219d34dd829SSam Ravnborg FPU(0x13, "UltraSparc IIe integrated FPU"),
220d34dd829SSam Ravnborg FPU(-1, NULL)
221d34dd829SSam Ravnborg }
222d34dd829SSam Ravnborg },{
223d34dd829SSam Ravnborg 0x22,
224d34dd829SSam Ravnborg .cpu_info = {
225c3cf5e8cSDavid S. Miller CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
226d34dd829SSam Ravnborg CPU(-1, NULL)
227d34dd829SSam Ravnborg },
228d34dd829SSam Ravnborg .fpu_info = {
229d34dd829SSam Ravnborg FPU(0x10, "UltraSparc I integrated FPU"),
230d34dd829SSam Ravnborg FPU(-1, NULL)
231d34dd829SSam Ravnborg }
232d34dd829SSam Ravnborg },{
233d34dd829SSam Ravnborg 0x3e,
234d34dd829SSam Ravnborg .cpu_info = {
235c3cf5e8cSDavid S. Miller CPU_PMU(0x14, "TI UltraSparc III (Cheetah)", "ultra3"),
236c3cf5e8cSDavid S. Miller CPU_PMU(0x15, "TI UltraSparc III+ (Cheetah+)", "ultra3+"),
237c3cf5e8cSDavid S. Miller CPU_PMU(0x16, "TI UltraSparc IIIi (Jalapeno)", "ultra3i"),
238c3cf5e8cSDavid S. Miller CPU_PMU(0x18, "TI UltraSparc IV (Jaguar)", "ultra3+"),
239c3cf5e8cSDavid S. Miller CPU_PMU(0x19, "TI UltraSparc IV+ (Panther)", "ultra4+"),
240c3cf5e8cSDavid S. Miller CPU_PMU(0x22, "TI UltraSparc IIIi+ (Serrano)", "ultra3i"),
241d34dd829SSam Ravnborg CPU(-1, NULL)
242d34dd829SSam Ravnborg },
243d34dd829SSam Ravnborg .fpu_info = {
244d34dd829SSam Ravnborg FPU(0x14, "UltraSparc III integrated FPU"),
245d34dd829SSam Ravnborg FPU(0x15, "UltraSparc III+ integrated FPU"),
246d34dd829SSam Ravnborg FPU(0x16, "UltraSparc IIIi integrated FPU"),
247d34dd829SSam Ravnborg FPU(0x18, "UltraSparc IV integrated FPU"),
248d34dd829SSam Ravnborg FPU(0x19, "UltraSparc IV+ integrated FPU"),
249d34dd829SSam Ravnborg FPU(0x22, "UltraSparc IIIi+ integrated FPU"),
250d34dd829SSam Ravnborg FPU(-1, NULL)
251d34dd829SSam Ravnborg }
252d34dd829SSam Ravnborg }};
253d34dd829SSam Ravnborg
254d34dd829SSam Ravnborg /* In order to get the fpu type correct, you need to take the IDPROM's
255d34dd829SSam Ravnborg * machine type value into consideration too. I will fix this.
256d34dd829SSam Ravnborg */
257d34dd829SSam Ravnborg
258cb1b8209SSam Ravnborg static const char *sparc_cpu_type;
259cb1b8209SSam Ravnborg static const char *sparc_fpu_type;
260c3cf5e8cSDavid S. Miller const char *sparc_pmu_type;
261d34dd829SSam Ravnborg
262d34dd829SSam Ravnborg
set_cpu_and_fpu(int psr_impl,int psr_vers,int fpu_vers)2639c2853afSSam Ravnborg static void __init set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers)
264d34dd829SSam Ravnborg {
265c275ce44SSam Ravnborg const struct manufacturer_info *manuf;
266c275ce44SSam Ravnborg int i;
267c275ce44SSam Ravnborg
268d34dd829SSam Ravnborg sparc_cpu_type = NULL;
269d34dd829SSam Ravnborg sparc_fpu_type = NULL;
270c3cf5e8cSDavid S. Miller sparc_pmu_type = NULL;
271c275ce44SSam Ravnborg manuf = NULL;
272c275ce44SSam Ravnborg
273c275ce44SSam Ravnborg for (i = 0; i < ARRAY_SIZE(manufacturer_info); i++)
274c275ce44SSam Ravnborg {
275c275ce44SSam Ravnborg if (psr_impl == manufacturer_info[i].psr_impl) {
276c275ce44SSam Ravnborg manuf = &manufacturer_info[i];
277c275ce44SSam Ravnborg break;
278c275ce44SSam Ravnborg }
279c275ce44SSam Ravnborg }
280c275ce44SSam Ravnborg if (manuf != NULL)
281d34dd829SSam Ravnborg {
282d34dd829SSam Ravnborg const struct cpu_info *cpu;
283d34dd829SSam Ravnborg const struct fpu_info *fpu;
284d34dd829SSam Ravnborg
285c275ce44SSam Ravnborg cpu = &manuf->cpu_info[0];
286d34dd829SSam Ravnborg while (cpu->psr_vers != -1)
287d34dd829SSam Ravnborg {
288d34dd829SSam Ravnborg if (cpu->psr_vers == psr_vers) {
289d34dd829SSam Ravnborg sparc_cpu_type = cpu->name;
290c3cf5e8cSDavid S. Miller sparc_pmu_type = cpu->pmu_name;
291d34dd829SSam Ravnborg sparc_fpu_type = "No FPU";
292d34dd829SSam Ravnborg break;
293d34dd829SSam Ravnborg }
294d34dd829SSam Ravnborg cpu++;
295d34dd829SSam Ravnborg }
296c275ce44SSam Ravnborg fpu = &manuf->fpu_info[0];
297d34dd829SSam Ravnborg while (fpu->fp_vers != -1)
298d34dd829SSam Ravnborg {
299d34dd829SSam Ravnborg if (fpu->fp_vers == fpu_vers) {
300d34dd829SSam Ravnborg sparc_fpu_type = fpu->name;
301d34dd829SSam Ravnborg break;
302d34dd829SSam Ravnborg }
303d34dd829SSam Ravnborg fpu++;
304d34dd829SSam Ravnborg }
305d34dd829SSam Ravnborg }
306d34dd829SSam Ravnborg if (sparc_cpu_type == NULL)
307d34dd829SSam Ravnborg {
308d34dd829SSam Ravnborg printk(KERN_ERR "CPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
309d34dd829SSam Ravnborg psr_impl, psr_vers);
310d34dd829SSam Ravnborg sparc_cpu_type = "Unknown CPU";
311d34dd829SSam Ravnborg }
312d34dd829SSam Ravnborg if (sparc_fpu_type == NULL)
313d34dd829SSam Ravnborg {
314d34dd829SSam Ravnborg printk(KERN_ERR "FPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
315d34dd829SSam Ravnborg psr_impl, fpu_vers);
316d34dd829SSam Ravnborg sparc_fpu_type = "Unknown FPU";
317d34dd829SSam Ravnborg }
318c3cf5e8cSDavid S. Miller if (sparc_pmu_type == NULL)
319c3cf5e8cSDavid S. Miller sparc_pmu_type = "Unknown PMU";
320d34dd829SSam Ravnborg }
321d34dd829SSam Ravnborg
322d34dd829SSam Ravnborg #ifdef CONFIG_SPARC32
show_cpuinfo(struct seq_file * m,void * __unused)323cb1b8209SSam Ravnborg static int show_cpuinfo(struct seq_file *m, void *__unused)
324cb1b8209SSam Ravnborg {
325cb1b8209SSam Ravnborg seq_printf(m,
326cb1b8209SSam Ravnborg "cpu\t\t: %s\n"
327cb1b8209SSam Ravnborg "fpu\t\t: %s\n"
328cb1b8209SSam Ravnborg "promlib\t\t: Version %d Revision %d\n"
329cb1b8209SSam Ravnborg "prom\t\t: %d.%d\n"
330cb1b8209SSam Ravnborg "type\t\t: %s\n"
331cb1b8209SSam Ravnborg "ncpus probed\t: %d\n"
332cb1b8209SSam Ravnborg "ncpus active\t: %d\n"
333cb1b8209SSam Ravnborg #ifndef CONFIG_SMP
334cb1b8209SSam Ravnborg "CPU0Bogo\t: %lu.%02lu\n"
335cb1b8209SSam Ravnborg "CPU0ClkTck\t: %ld\n"
336cb1b8209SSam Ravnborg #endif
337cb1b8209SSam Ravnborg ,
338cb1b8209SSam Ravnborg sparc_cpu_type,
339cb1b8209SSam Ravnborg sparc_fpu_type ,
340cb1b8209SSam Ravnborg romvec->pv_romvers,
341cb1b8209SSam Ravnborg prom_rev,
342cb1b8209SSam Ravnborg romvec->pv_printrev >> 16,
343cb1b8209SSam Ravnborg romvec->pv_printrev & 0xffff,
344cb1b8209SSam Ravnborg &cputypval[0],
345cb1b8209SSam Ravnborg ncpus_probed,
346cb1b8209SSam Ravnborg num_online_cpus()
347cb1b8209SSam Ravnborg #ifndef CONFIG_SMP
348cb1b8209SSam Ravnborg , cpu_data(0).udelay_val/(500000/HZ),
349cb1b8209SSam Ravnborg (cpu_data(0).udelay_val/(5000/HZ)) % 100,
350cb1b8209SSam Ravnborg cpu_data(0).clock_tick
351cb1b8209SSam Ravnborg #endif
352cb1b8209SSam Ravnborg );
353cb1b8209SSam Ravnborg
354cb1b8209SSam Ravnborg #ifdef CONFIG_SMP
355cb1b8209SSam Ravnborg smp_bogo(m);
356cb1b8209SSam Ravnborg #endif
357cb1b8209SSam Ravnborg mmu_info(m);
358cb1b8209SSam Ravnborg #ifdef CONFIG_SMP
359cb1b8209SSam Ravnborg smp_info(m);
360cb1b8209SSam Ravnborg #endif
361cb1b8209SSam Ravnborg return 0;
362cb1b8209SSam Ravnborg }
363cb1b8209SSam Ravnborg #endif /* CONFIG_SPARC32 */
364cb1b8209SSam Ravnborg
365cb1b8209SSam Ravnborg #ifdef CONFIG_SPARC64
366cb1b8209SSam Ravnborg unsigned int dcache_parity_tl1_occurred;
367cb1b8209SSam Ravnborg unsigned int icache_parity_tl1_occurred;
368cb1b8209SSam Ravnborg
369cb1b8209SSam Ravnborg
show_cpuinfo(struct seq_file * m,void * __unused)370cb1b8209SSam Ravnborg static int show_cpuinfo(struct seq_file *m, void *__unused)
371cb1b8209SSam Ravnborg {
372cb1b8209SSam Ravnborg seq_printf(m,
373cb1b8209SSam Ravnborg "cpu\t\t: %s\n"
374cb1b8209SSam Ravnborg "fpu\t\t: %s\n"
375cb1b8209SSam Ravnborg "pmu\t\t: %s\n"
376cb1b8209SSam Ravnborg "prom\t\t: %s\n"
377cb1b8209SSam Ravnborg "type\t\t: %s\n"
378cb1b8209SSam Ravnborg "ncpus probed\t: %d\n"
379cb1b8209SSam Ravnborg "ncpus active\t: %d\n"
380cb1b8209SSam Ravnborg "D$ parity tl1\t: %u\n"
381cb1b8209SSam Ravnborg "I$ parity tl1\t: %u\n"
382cb1b8209SSam Ravnborg #ifndef CONFIG_SMP
383cb1b8209SSam Ravnborg "Cpu0ClkTck\t: %016lx\n"
384cb1b8209SSam Ravnborg #endif
385cb1b8209SSam Ravnborg ,
386cb1b8209SSam Ravnborg sparc_cpu_type,
387cb1b8209SSam Ravnborg sparc_fpu_type,
388cb1b8209SSam Ravnborg sparc_pmu_type,
389cb1b8209SSam Ravnborg prom_version,
390cb1b8209SSam Ravnborg ((tlb_type == hypervisor) ?
391cb1b8209SSam Ravnborg "sun4v" :
392cb1b8209SSam Ravnborg "sun4u"),
393cb1b8209SSam Ravnborg ncpus_probed,
394cb1b8209SSam Ravnborg num_online_cpus(),
395cb1b8209SSam Ravnborg dcache_parity_tl1_occurred,
396cb1b8209SSam Ravnborg icache_parity_tl1_occurred
397cb1b8209SSam Ravnborg #ifndef CONFIG_SMP
398cb1b8209SSam Ravnborg , cpu_data(0).clock_tick
399cb1b8209SSam Ravnborg #endif
400cb1b8209SSam Ravnborg );
401ac85fe8bSDavid S. Miller cpucap_info(m);
402cb1b8209SSam Ravnborg #ifdef CONFIG_SMP
403cb1b8209SSam Ravnborg smp_bogo(m);
404cb1b8209SSam Ravnborg #endif
405cb1b8209SSam Ravnborg mmu_info(m);
406cb1b8209SSam Ravnborg #ifdef CONFIG_SMP
407cb1b8209SSam Ravnborg smp_info(m);
408cb1b8209SSam Ravnborg #endif
409cb1b8209SSam Ravnborg return 0;
410cb1b8209SSam Ravnborg }
411cb1b8209SSam Ravnborg #endif /* CONFIG_SPARC64 */
412cb1b8209SSam Ravnborg
c_start(struct seq_file * m,loff_t * pos)413cb1b8209SSam Ravnborg static void *c_start(struct seq_file *m, loff_t *pos)
414cb1b8209SSam Ravnborg {
415cb1b8209SSam Ravnborg /* The pointer we are returning is arbitrary,
416cb1b8209SSam Ravnborg * it just has to be non-NULL and not IS_ERR
417cb1b8209SSam Ravnborg * in the success case.
418cb1b8209SSam Ravnborg */
419cb1b8209SSam Ravnborg return *pos == 0 ? &c_start : NULL;
420cb1b8209SSam Ravnborg }
421cb1b8209SSam Ravnborg
c_next(struct seq_file * m,void * v,loff_t * pos)422cb1b8209SSam Ravnborg static void *c_next(struct seq_file *m, void *v, loff_t *pos)
423cb1b8209SSam Ravnborg {
424cb1b8209SSam Ravnborg ++*pos;
425cb1b8209SSam Ravnborg return c_start(m, pos);
426cb1b8209SSam Ravnborg }
427cb1b8209SSam Ravnborg
c_stop(struct seq_file * m,void * v)428cb1b8209SSam Ravnborg static void c_stop(struct seq_file *m, void *v)
429cb1b8209SSam Ravnborg {
430cb1b8209SSam Ravnborg }
431cb1b8209SSam Ravnborg
432cb1b8209SSam Ravnborg const struct seq_operations cpuinfo_op = {
433cb1b8209SSam Ravnborg .start =c_start,
434cb1b8209SSam Ravnborg .next = c_next,
435cb1b8209SSam Ravnborg .stop = c_stop,
436cb1b8209SSam Ravnborg .show = show_cpuinfo,
437cb1b8209SSam Ravnborg };
438cb1b8209SSam Ravnborg
439cb1b8209SSam Ravnborg #ifdef CONFIG_SPARC32
cpu_type_probe(void)4409c2853afSSam Ravnborg static int __init cpu_type_probe(void)
441d34dd829SSam Ravnborg {
442d34dd829SSam Ravnborg int psr_impl, psr_vers, fpu_vers;
443d34dd829SSam Ravnborg int psr;
444d34dd829SSam Ravnborg
445d87d8c11SSam Ravnborg psr_impl = ((get_psr() >> PSR_IMPL_SHIFT) & PSR_IMPL_SHIFTED_MASK);
446d87d8c11SSam Ravnborg psr_vers = ((get_psr() >> PSR_VERS_SHIFT) & PSR_VERS_SHIFTED_MASK);
447d34dd829SSam Ravnborg
448d34dd829SSam Ravnborg psr = get_psr();
449d34dd829SSam Ravnborg put_psr(psr | PSR_EF);
450d87d8c11SSam Ravnborg
451d87d8c11SSam Ravnborg if (psr_impl == PSR_IMPL_LEON)
4522666e476SDaniel Hellstrom fpu_vers = get_psr() & PSR_EF ? ((get_fsr() >> 17) & 0x7) : 7;
453d87d8c11SSam Ravnborg else
454d34dd829SSam Ravnborg fpu_vers = ((get_fsr() >> 17) & 0x7);
4550fd7ef1fSKonrad Eisele
456d34dd829SSam Ravnborg put_psr(psr);
457d34dd829SSam Ravnborg
458d34dd829SSam Ravnborg set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers);
4599c2853afSSam Ravnborg
4609c2853afSSam Ravnborg return 0;
461d34dd829SSam Ravnborg }
4629c2853afSSam Ravnborg #endif /* CONFIG_SPARC32 */
4639c2853afSSam Ravnborg
4649c2853afSSam Ravnborg #ifdef CONFIG_SPARC64
sun4v_cpu_probe(void)465d34dd829SSam Ravnborg static void __init sun4v_cpu_probe(void)
466d34dd829SSam Ravnborg {
467d34dd829SSam Ravnborg switch (sun4v_chip_type) {
468d34dd829SSam Ravnborg case SUN4V_CHIP_NIAGARA1:
469d34dd829SSam Ravnborg sparc_cpu_type = "UltraSparc T1 (Niagara)";
470d34dd829SSam Ravnborg sparc_fpu_type = "UltraSparc T1 integrated FPU";
471c3cf5e8cSDavid S. Miller sparc_pmu_type = "niagara";
472d34dd829SSam Ravnborg break;
473d34dd829SSam Ravnborg
474d34dd829SSam Ravnborg case SUN4V_CHIP_NIAGARA2:
475d34dd829SSam Ravnborg sparc_cpu_type = "UltraSparc T2 (Niagara2)";
476d34dd829SSam Ravnborg sparc_fpu_type = "UltraSparc T2 integrated FPU";
477c3cf5e8cSDavid S. Miller sparc_pmu_type = "niagara2";
478d34dd829SSam Ravnborg break;
479d34dd829SSam Ravnborg
4804ba991d3SDavid S. Miller case SUN4V_CHIP_NIAGARA3:
4814ba991d3SDavid S. Miller sparc_cpu_type = "UltraSparc T3 (Niagara3)";
4824ba991d3SDavid S. Miller sparc_fpu_type = "UltraSparc T3 integrated FPU";
4834ba991d3SDavid S. Miller sparc_pmu_type = "niagara3";
4844ba991d3SDavid S. Miller break;
4854ba991d3SDavid S. Miller
48608cefa9fSDavid S. Miller case SUN4V_CHIP_NIAGARA4:
48708cefa9fSDavid S. Miller sparc_cpu_type = "UltraSparc T4 (Niagara4)";
48808cefa9fSDavid S. Miller sparc_fpu_type = "UltraSparc T4 integrated FPU";
48908cefa9fSDavid S. Miller sparc_pmu_type = "niagara4";
49008cefa9fSDavid S. Miller break;
49108cefa9fSDavid S. Miller
49208cefa9fSDavid S. Miller case SUN4V_CHIP_NIAGARA5:
49308cefa9fSDavid S. Miller sparc_cpu_type = "UltraSparc T5 (Niagara5)";
49408cefa9fSDavid S. Miller sparc_fpu_type = "UltraSparc T5 integrated FPU";
49508cefa9fSDavid S. Miller sparc_pmu_type = "niagara5";
49608cefa9fSDavid S. Miller break;
49708cefa9fSDavid S. Miller
498cadbb580SAllen Pais case SUN4V_CHIP_SPARC_M6:
499cadbb580SAllen Pais sparc_cpu_type = "SPARC-M6";
500cadbb580SAllen Pais sparc_fpu_type = "SPARC-M6 integrated FPU";
501cadbb580SAllen Pais sparc_pmu_type = "sparc-m6";
502cadbb580SAllen Pais break;
503cadbb580SAllen Pais
504cadbb580SAllen Pais case SUN4V_CHIP_SPARC_M7:
505cadbb580SAllen Pais sparc_cpu_type = "SPARC-M7";
506cadbb580SAllen Pais sparc_fpu_type = "SPARC-M7 integrated FPU";
507cadbb580SAllen Pais sparc_pmu_type = "sparc-m7";
508cadbb580SAllen Pais break;
509cadbb580SAllen Pais
5107d484acbSAllen Pais case SUN4V_CHIP_SPARC_M8:
5117d484acbSAllen Pais sparc_cpu_type = "SPARC-M8";
5127d484acbSAllen Pais sparc_fpu_type = "SPARC-M8 integrated FPU";
5137d484acbSAllen Pais sparc_pmu_type = "sparc-m8";
5147d484acbSAllen Pais break;
5157d484acbSAllen Pais
516c5b8b5beSKhalid Aziz case SUN4V_CHIP_SPARC_SN:
517c5b8b5beSKhalid Aziz sparc_cpu_type = "SPARC-SN";
518c5b8b5beSKhalid Aziz sparc_fpu_type = "SPARC-SN integrated FPU";
519c5b8b5beSKhalid Aziz sparc_pmu_type = "sparc-sn";
520c5b8b5beSKhalid Aziz break;
521c5b8b5beSKhalid Aziz
52276950e6eSAllen Pais case SUN4V_CHIP_SPARC64X:
52376950e6eSAllen Pais sparc_cpu_type = "SPARC64-X";
52476950e6eSAllen Pais sparc_fpu_type = "SPARC64-X integrated FPU";
52576950e6eSAllen Pais sparc_pmu_type = "sparc64-x";
52676950e6eSAllen Pais break;
52776950e6eSAllen Pais
528d34dd829SSam Ravnborg default:
529d34dd829SSam Ravnborg printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
530d34dd829SSam Ravnborg prom_cpu_compatible);
531d34dd829SSam Ravnborg sparc_cpu_type = "Unknown SUN4V CPU";
532d34dd829SSam Ravnborg sparc_fpu_type = "Unknown SUN4V FPU";
533facfddefSDavid S. Miller sparc_pmu_type = "Unknown SUN4V PMU";
534d34dd829SSam Ravnborg break;
535d34dd829SSam Ravnborg }
536d34dd829SSam Ravnborg }
537d34dd829SSam Ravnborg
cpu_type_probe(void)538d34dd829SSam Ravnborg static int __init cpu_type_probe(void)
539d34dd829SSam Ravnborg {
540d34dd829SSam Ravnborg if (tlb_type == hypervisor) {
541d34dd829SSam Ravnborg sun4v_cpu_probe();
542d34dd829SSam Ravnborg } else {
543d34dd829SSam Ravnborg unsigned long ver;
544d34dd829SSam Ravnborg int manuf, impl;
545d34dd829SSam Ravnborg
546d34dd829SSam Ravnborg __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
547d34dd829SSam Ravnborg
548d34dd829SSam Ravnborg manuf = ((ver >> 48) & 0xffff);
549d34dd829SSam Ravnborg impl = ((ver >> 32) & 0xffff);
550d34dd829SSam Ravnborg set_cpu_and_fpu(manuf, impl, impl);
551d34dd829SSam Ravnborg }
552d34dd829SSam Ravnborg return 0;
553d34dd829SSam Ravnborg }
5549c2853afSSam Ravnborg #endif /* CONFIG_SPARC64 */
555d34dd829SSam Ravnborg
5565edddaabSDavid S. Miller early_initcall(cpu_type_probe);
557