1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a439fe51SSam Ravnborg /*
3a439fe51SSam Ravnborg * turbosparc.h: Defines specific to the TurboSparc module.
4a439fe51SSam Ravnborg * This is SRMMU stuff.
5a439fe51SSam Ravnborg *
6a439fe51SSam Ravnborg * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7a439fe51SSam Ravnborg */
8a439fe51SSam Ravnborg #ifndef _SPARC_TURBOSPARC_H
9a439fe51SSam Ravnborg #define _SPARC_TURBOSPARC_H
10a439fe51SSam Ravnborg
11a439fe51SSam Ravnborg #include <asm/asi.h>
12a439fe51SSam Ravnborg #include <asm/pgtsrmmu.h>
13a439fe51SSam Ravnborg
14a439fe51SSam Ravnborg /* Bits in the SRMMU control register for TurboSparc modules.
15a439fe51SSam Ravnborg *
16a439fe51SSam Ravnborg * -------------------------------------------------------------------
17a439fe51SSam Ravnborg * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
18a439fe51SSam Ravnborg * -------------------------------------------------------------------
19a439fe51SSam Ravnborg * 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0
20a439fe51SSam Ravnborg *
21a439fe51SSam Ravnborg * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
22a439fe51SSam Ravnborg *
23a439fe51SSam Ravnborg * This indicates whether the TurboSparc is in boot-mode or not.
24a439fe51SSam Ravnborg *
25a439fe51SSam Ravnborg * IC: Instruction Cache -- 0 = off, 1 = on
26a439fe51SSam Ravnborg * DC: Data Cache -- 0 = off, 1 = 0n
27a439fe51SSam Ravnborg *
28a439fe51SSam Ravnborg * These bits enable the on-cpu TurboSparc split I/D caches.
29a439fe51SSam Ravnborg *
30a439fe51SSam Ravnborg * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
31a439fe51SSam Ravnborg * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
32a439fe51SSam Ravnborg * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
33a439fe51SSam Ravnborg *
34a439fe51SSam Ravnborg */
35a439fe51SSam Ravnborg
36a439fe51SSam Ravnborg #define TURBOSPARC_MMUENABLE 0x00000001
37a439fe51SSam Ravnborg #define TURBOSPARC_NOFAULT 0x00000002
38a439fe51SSam Ravnborg #define TURBOSPARC_ICSNOOP 0x00000004
39a439fe51SSam Ravnborg #define TURBOSPARC_PSO 0x00000080
40a439fe51SSam Ravnborg #define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
41a439fe51SSam Ravnborg #define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
42a439fe51SSam Ravnborg #define TURBOSPARC_BMODE 0x00004000
43a439fe51SSam Ravnborg #define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
44a439fe51SSam Ravnborg #define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
45a439fe51SSam Ravnborg
46a439fe51SSam Ravnborg /* Bits in the CPU configuration register for TurboSparc modules.
47a439fe51SSam Ravnborg *
48a439fe51SSam Ravnborg * -------------------------------------------------------
49a439fe51SSam Ravnborg * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
50a439fe51SSam Ravnborg * -------------------------------------------------------
51a439fe51SSam Ravnborg * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
52a439fe51SSam Ravnborg *
53a439fe51SSam Ravnborg */
54a439fe51SSam Ravnborg
55a439fe51SSam Ravnborg #define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
56a439fe51SSam Ravnborg #define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
57a439fe51SSam Ravnborg #define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
58a439fe51SSam Ravnborg #define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
59a439fe51SSam Ravnborg
60a439fe51SSam Ravnborg #ifndef __ASSEMBLY__
61a439fe51SSam Ravnborg
62a439fe51SSam Ravnborg /* Bits [13:5] select one of 512 instruction cache tags */
turbosparc_inv_insn_tag(unsigned long addr)63a439fe51SSam Ravnborg static inline void turbosparc_inv_insn_tag(unsigned long addr)
64a439fe51SSam Ravnborg {
65a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
66a439fe51SSam Ravnborg : /* no outputs */
67a439fe51SSam Ravnborg : "r" (addr), "i" (ASI_M_TXTC_TAG)
68a439fe51SSam Ravnborg : "memory");
69a439fe51SSam Ravnborg }
70a439fe51SSam Ravnborg
71a439fe51SSam Ravnborg /* Bits [13:5] select one of 512 data cache tags */
turbosparc_inv_data_tag(unsigned long addr)72a439fe51SSam Ravnborg static inline void turbosparc_inv_data_tag(unsigned long addr)
73a439fe51SSam Ravnborg {
74a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
75a439fe51SSam Ravnborg : /* no outputs */
76a439fe51SSam Ravnborg : "r" (addr), "i" (ASI_M_DATAC_TAG)
77a439fe51SSam Ravnborg : "memory");
78a439fe51SSam Ravnborg }
79a439fe51SSam Ravnborg
turbosparc_flush_icache(void)80a439fe51SSam Ravnborg static inline void turbosparc_flush_icache(void)
81a439fe51SSam Ravnborg {
82a439fe51SSam Ravnborg unsigned long addr;
83a439fe51SSam Ravnborg
84a439fe51SSam Ravnborg for (addr = 0; addr < 0x4000; addr += 0x20)
85a439fe51SSam Ravnborg turbosparc_inv_insn_tag(addr);
86a439fe51SSam Ravnborg }
87a439fe51SSam Ravnborg
turbosparc_flush_dcache(void)88a439fe51SSam Ravnborg static inline void turbosparc_flush_dcache(void)
89a439fe51SSam Ravnborg {
90a439fe51SSam Ravnborg unsigned long addr;
91a439fe51SSam Ravnborg
92a439fe51SSam Ravnborg for (addr = 0; addr < 0x4000; addr += 0x20)
93a439fe51SSam Ravnborg turbosparc_inv_data_tag(addr);
94a439fe51SSam Ravnborg }
95a439fe51SSam Ravnborg
turbosparc_idflash_clear(void)96a439fe51SSam Ravnborg static inline void turbosparc_idflash_clear(void)
97a439fe51SSam Ravnborg {
98a439fe51SSam Ravnborg unsigned long addr;
99a439fe51SSam Ravnborg
100a439fe51SSam Ravnborg for (addr = 0; addr < 0x4000; addr += 0x20) {
101a439fe51SSam Ravnborg turbosparc_inv_insn_tag(addr);
102a439fe51SSam Ravnborg turbosparc_inv_data_tag(addr);
103a439fe51SSam Ravnborg }
104a439fe51SSam Ravnborg }
105a439fe51SSam Ravnborg
turbosparc_set_ccreg(unsigned long regval)106a439fe51SSam Ravnborg static inline void turbosparc_set_ccreg(unsigned long regval)
107a439fe51SSam Ravnborg {
108a439fe51SSam Ravnborg __asm__ __volatile__("sta %0, [%1] %2\n\t"
109a439fe51SSam Ravnborg : /* no outputs */
110a439fe51SSam Ravnborg : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
111a439fe51SSam Ravnborg : "memory");
112a439fe51SSam Ravnborg }
113a439fe51SSam Ravnborg
turbosparc_get_ccreg(void)114a439fe51SSam Ravnborg static inline unsigned long turbosparc_get_ccreg(void)
115a439fe51SSam Ravnborg {
116a439fe51SSam Ravnborg unsigned long regval;
117a439fe51SSam Ravnborg
118a439fe51SSam Ravnborg __asm__ __volatile__("lda [%1] %2, %0\n\t"
119a439fe51SSam Ravnborg : "=r" (regval)
120a439fe51SSam Ravnborg : "r" (0x600), "i" (ASI_M_MMUREGS));
121a439fe51SSam Ravnborg return regval;
122a439fe51SSam Ravnborg }
123a439fe51SSam Ravnborg
124a439fe51SSam Ravnborg #endif /* !__ASSEMBLY__ */
125a439fe51SSam Ravnborg
126a439fe51SSam Ravnborg #endif /* !(_SPARC_TURBOSPARC_H) */
127