1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a439fe51SSam Ravnborg /* swift.h: Specific definitions for the _broken_ Swift SRMMU
3a439fe51SSam Ravnborg * MMU module.
4a439fe51SSam Ravnborg *
5a439fe51SSam Ravnborg * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
6a439fe51SSam Ravnborg */
7a439fe51SSam Ravnborg
8a439fe51SSam Ravnborg #ifndef _SPARC_SWIFT_H
9a439fe51SSam Ravnborg #define _SPARC_SWIFT_H
10a439fe51SSam Ravnborg
11a439fe51SSam Ravnborg /* Swift is so brain damaged, here is the mmu control register. */
12a439fe51SSam Ravnborg #define SWIFT_ST 0x00800000 /* SW tablewalk enable */
13a439fe51SSam Ravnborg #define SWIFT_WP 0x00400000 /* Watchpoint enable */
14a439fe51SSam Ravnborg
15a439fe51SSam Ravnborg /* Branch folding (buggy, disable on production systems!) */
16a439fe51SSam Ravnborg #define SWIFT_BF 0x00200000
17a439fe51SSam Ravnborg #define SWIFT_PMC 0x00180000 /* Page mode control */
18a439fe51SSam Ravnborg #define SWIFT_PE 0x00040000 /* Parity enable */
19a439fe51SSam Ravnborg #define SWIFT_PC 0x00020000 /* Parity control */
20a439fe51SSam Ravnborg #define SWIFT_AP 0x00010000 /* Graphics page mode control (TCX/SX) */
21a439fe51SSam Ravnborg #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
22a439fe51SSam Ravnborg #define SWIFT_BM 0x00004000 /* Boot mode */
23a439fe51SSam Ravnborg #define SWIFT_RC 0x00003c00 /* DRAM refresh control */
24a439fe51SSam Ravnborg #define SWIFT_IE 0x00000200 /* Instruction cache enable */
25a439fe51SSam Ravnborg #define SWIFT_DE 0x00000100 /* Data cache enable */
26a439fe51SSam Ravnborg #define SWIFT_SA 0x00000080 /* Store Allocate */
27a439fe51SSam Ravnborg #define SWIFT_NF 0x00000002 /* No fault mode */
28a439fe51SSam Ravnborg #define SWIFT_EN 0x00000001 /* MMU enable */
29a439fe51SSam Ravnborg
30a439fe51SSam Ravnborg /* Bits [13:5] select one of 512 instruction cache tags */
swift_inv_insn_tag(unsigned long addr)31a439fe51SSam Ravnborg static inline void swift_inv_insn_tag(unsigned long addr)
32a439fe51SSam Ravnborg {
33a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
34a439fe51SSam Ravnborg : /* no outputs */
35a439fe51SSam Ravnborg : "r" (addr), "i" (ASI_M_TXTC_TAG)
36a439fe51SSam Ravnborg : "memory");
37a439fe51SSam Ravnborg }
38a439fe51SSam Ravnborg
39a439fe51SSam Ravnborg /* Bits [12:4] select one of 512 data cache tags */
swift_inv_data_tag(unsigned long addr)40a439fe51SSam Ravnborg static inline void swift_inv_data_tag(unsigned long addr)
41a439fe51SSam Ravnborg {
42a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
43a439fe51SSam Ravnborg : /* no outputs */
44a439fe51SSam Ravnborg : "r" (addr), "i" (ASI_M_DATAC_TAG)
45a439fe51SSam Ravnborg : "memory");
46a439fe51SSam Ravnborg }
47a439fe51SSam Ravnborg
swift_flush_dcache(void)48a439fe51SSam Ravnborg static inline void swift_flush_dcache(void)
49a439fe51SSam Ravnborg {
50a439fe51SSam Ravnborg unsigned long addr;
51a439fe51SSam Ravnborg
52a439fe51SSam Ravnborg for (addr = 0; addr < 0x2000; addr += 0x10)
53a439fe51SSam Ravnborg swift_inv_data_tag(addr);
54a439fe51SSam Ravnborg }
55a439fe51SSam Ravnborg
swift_flush_icache(void)56a439fe51SSam Ravnborg static inline void swift_flush_icache(void)
57a439fe51SSam Ravnborg {
58a439fe51SSam Ravnborg unsigned long addr;
59a439fe51SSam Ravnborg
60a439fe51SSam Ravnborg for (addr = 0; addr < 0x4000; addr += 0x20)
61a439fe51SSam Ravnborg swift_inv_insn_tag(addr);
62a439fe51SSam Ravnborg }
63a439fe51SSam Ravnborg
swift_idflash_clear(void)64a439fe51SSam Ravnborg static inline void swift_idflash_clear(void)
65a439fe51SSam Ravnborg {
66a439fe51SSam Ravnborg unsigned long addr;
67a439fe51SSam Ravnborg
68a439fe51SSam Ravnborg for (addr = 0; addr < 0x2000; addr += 0x10) {
69a439fe51SSam Ravnborg swift_inv_insn_tag(addr<<1);
70a439fe51SSam Ravnborg swift_inv_data_tag(addr);
71a439fe51SSam Ravnborg }
72a439fe51SSam Ravnborg }
73a439fe51SSam Ravnborg
74a439fe51SSam Ravnborg /* Swift is so broken, it isn't even safe to use the following. */
swift_flush_page(unsigned long page)75a439fe51SSam Ravnborg static inline void swift_flush_page(unsigned long page)
76a439fe51SSam Ravnborg {
77a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
78a439fe51SSam Ravnborg : /* no outputs */
79a439fe51SSam Ravnborg : "r" (page), "i" (ASI_M_FLUSH_PAGE)
80a439fe51SSam Ravnborg : "memory");
81a439fe51SSam Ravnborg }
82a439fe51SSam Ravnborg
swift_flush_segment(unsigned long addr)83a439fe51SSam Ravnborg static inline void swift_flush_segment(unsigned long addr)
84a439fe51SSam Ravnborg {
85a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
86a439fe51SSam Ravnborg : /* no outputs */
87a439fe51SSam Ravnborg : "r" (addr), "i" (ASI_M_FLUSH_SEG)
88a439fe51SSam Ravnborg : "memory");
89a439fe51SSam Ravnborg }
90a439fe51SSam Ravnborg
swift_flush_region(unsigned long addr)91a439fe51SSam Ravnborg static inline void swift_flush_region(unsigned long addr)
92a439fe51SSam Ravnborg {
93a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
94a439fe51SSam Ravnborg : /* no outputs */
95a439fe51SSam Ravnborg : "r" (addr), "i" (ASI_M_FLUSH_REGION)
96a439fe51SSam Ravnborg : "memory");
97a439fe51SSam Ravnborg }
98a439fe51SSam Ravnborg
swift_flush_context(void)99a439fe51SSam Ravnborg static inline void swift_flush_context(void)
100a439fe51SSam Ravnborg {
101a439fe51SSam Ravnborg __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
102a439fe51SSam Ravnborg : /* no outputs */
103a439fe51SSam Ravnborg : "i" (ASI_M_FLUSH_CTX)
104a439fe51SSam Ravnborg : "memory");
105a439fe51SSam Ravnborg }
106a439fe51SSam Ravnborg
107a439fe51SSam Ravnborg #endif /* !(_SPARC_SWIFT_H) */
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