1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg /* 3a439fe51SSam Ravnborg * include/asm/sunbpp.h 4a439fe51SSam Ravnborg */ 5a439fe51SSam Ravnborg 6a439fe51SSam Ravnborg #ifndef _ASM_SPARC_SUNBPP_H 7a439fe51SSam Ravnborg #define _ASM_SPARC_SUNBPP_H 8a439fe51SSam Ravnborg 9a439fe51SSam Ravnborg struct bpp_regs { 10a439fe51SSam Ravnborg /* DMA registers */ 11a439fe51SSam Ravnborg __volatile__ __u32 p_csr; /* DMA Control/Status Register */ 12a439fe51SSam Ravnborg __volatile__ __u32 p_addr; /* Address Register */ 13a439fe51SSam Ravnborg __volatile__ __u32 p_bcnt; /* Byte Count Register */ 14a439fe51SSam Ravnborg __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */ 15a439fe51SSam Ravnborg /* Parallel Port registers */ 16a439fe51SSam Ravnborg __volatile__ __u16 p_hcr; /* Hardware Configuration Register */ 17a439fe51SSam Ravnborg __volatile__ __u16 p_ocr; /* Operation Configuration Register */ 18a439fe51SSam Ravnborg __volatile__ __u8 p_dr; /* Parallel Data Register */ 19a439fe51SSam Ravnborg __volatile__ __u8 p_tcr; /* Transfer Control Register */ 20a439fe51SSam Ravnborg __volatile__ __u8 p_or; /* Output Register */ 21a439fe51SSam Ravnborg __volatile__ __u8 p_ir; /* Input Register */ 22a439fe51SSam Ravnborg __volatile__ __u16 p_icr; /* Interrupt Control Register */ 23a439fe51SSam Ravnborg }; 24a439fe51SSam Ravnborg 25a439fe51SSam Ravnborg /* P_HCR. Time is in increments of SBus clock. */ 26a439fe51SSam Ravnborg #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */ 27a439fe51SSam Ravnborg #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */ 28a439fe51SSam Ravnborg #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */ 29a439fe51SSam Ravnborg 30a439fe51SSam Ravnborg /* P_OCR. */ 31a439fe51SSam Ravnborg #define P_OCR_MEM_CLR 0x8000 32a439fe51SSam Ravnborg #define P_OCR_DATA_SRC 0x4000 /* ) */ 33a439fe51SSam Ravnborg #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */ 34a439fe51SSam Ravnborg #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */ 35a439fe51SSam Ravnborg #define P_OCR_ACK_DSEL 0x0800 /* ) */ 36a439fe51SSam Ravnborg #define P_OCR_EN_DIAG 0x0400 37a439fe51SSam Ravnborg #define P_OCR_BUSY_OP 0x0200 /* Busy operation */ 38a439fe51SSam Ravnborg #define P_OCR_ACK_OP 0x0100 /* Ack operation */ 39a439fe51SSam Ravnborg #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */ 40a439fe51SSam Ravnborg #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */ 41a439fe51SSam Ravnborg #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */ 42a439fe51SSam Ravnborg #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */ 43a439fe51SSam Ravnborg 44a439fe51SSam Ravnborg /* P_TCR */ 45a439fe51SSam Ravnborg #define P_TCR_DIR 0x08 46a439fe51SSam Ravnborg #define P_TCR_BUSY 0x04 47a439fe51SSam Ravnborg #define P_TCR_ACK 0x02 48a439fe51SSam Ravnborg #define P_TCR_DS 0x01 /* Strobe */ 49a439fe51SSam Ravnborg 50a439fe51SSam Ravnborg /* P_OR */ 51a439fe51SSam Ravnborg #define P_OR_V3 0x20 /* ) */ 52a439fe51SSam Ravnborg #define P_OR_V2 0x10 /* ) on Zebra only */ 53a439fe51SSam Ravnborg #define P_OR_V1 0x08 /* ) */ 54a439fe51SSam Ravnborg #define P_OR_INIT 0x04 55a439fe51SSam Ravnborg #define P_OR_AFXN 0x02 /* Auto Feed */ 56a439fe51SSam Ravnborg #define P_OR_SLCT_IN 0x01 57a439fe51SSam Ravnborg 58a439fe51SSam Ravnborg /* P_IR */ 59a439fe51SSam Ravnborg #define P_IR_PE 0x04 60a439fe51SSam Ravnborg #define P_IR_SLCT 0x02 61a439fe51SSam Ravnborg #define P_IR_ERR 0x01 62a439fe51SSam Ravnborg 63a439fe51SSam Ravnborg /* P_ICR */ 64a439fe51SSam Ravnborg #define P_DS_IRQ 0x8000 /* RW1 */ 65a439fe51SSam Ravnborg #define P_ACK_IRQ 0x4000 /* RW1 */ 66a439fe51SSam Ravnborg #define P_BUSY_IRQ 0x2000 /* RW1 */ 67a439fe51SSam Ravnborg #define P_PE_IRQ 0x1000 /* RW1 */ 68a439fe51SSam Ravnborg #define P_SLCT_IRQ 0x0800 /* RW1 */ 69a439fe51SSam Ravnborg #define P_ERR_IRQ 0x0400 /* RW1 */ 70a439fe51SSam Ravnborg #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */ 71a439fe51SSam Ravnborg #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */ 72a439fe51SSam Ravnborg #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */ 73a439fe51SSam Ravnborg #define P_BUSY_IRQ_EN 0x0040 /* RW */ 74a439fe51SSam Ravnborg #define P_PE_IRP 0x0020 /* RW 1= rising edge */ 75a439fe51SSam Ravnborg #define P_PE_IRQ_EN 0x0010 /* RW */ 76a439fe51SSam Ravnborg #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */ 77a439fe51SSam Ravnborg #define P_SLCT_IRQ_EN 0x0004 /* RW */ 78a439fe51SSam Ravnborg #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */ 79a439fe51SSam Ravnborg #define P_ERR_IRQ_EN 0x0001 /* RW */ 80a439fe51SSam Ravnborg 81a439fe51SSam Ravnborg #endif /* !(_ASM_SPARC_SUNBPP_H) */ 82