1 /* 2 * psr.h: This file holds the macros for masking off various parts of 3 * the processor status register on the Sparc. This is valid 4 * for Version 8. On the V9 this is renamed to the PSTATE 5 * register and its members are accessed as fields like 6 * PSTATE.PRIV for the current CPU privilege level. 7 * 8 * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu) 9 */ 10 11 #ifndef __LINUX_SPARC_PSR_H 12 #define __LINUX_SPARC_PSR_H 13 14 /* The Sparc PSR fields are laid out as the following: 15 * 16 * ------------------------------------------------------------------------ 17 * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP | 18 * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 | 19 * ------------------------------------------------------------------------ 20 */ 21 #define PSR_CWP 0x0000001f /* current window pointer */ 22 #define PSR_ET 0x00000020 /* enable traps field */ 23 #define PSR_PS 0x00000040 /* previous privilege level */ 24 #define PSR_S 0x00000080 /* current privilege level */ 25 #define PSR_PIL 0x00000f00 /* processor interrupt level */ 26 #define PSR_EF 0x00001000 /* enable floating point */ 27 #define PSR_EC 0x00002000 /* enable co-processor */ 28 #define PSR_SYSCALL 0x00004000 /* inside of a syscall */ 29 #define PSR_LE 0x00008000 /* SuperSparcII little-endian */ 30 #define PSR_ICC 0x00f00000 /* integer condition codes */ 31 #define PSR_C 0x00100000 /* carry bit */ 32 #define PSR_V 0x00200000 /* overflow bit */ 33 #define PSR_Z 0x00400000 /* zero bit */ 34 #define PSR_N 0x00800000 /* negative bit */ 35 #define PSR_VERS 0x0f000000 /* cpu-version field */ 36 #define PSR_IMPL 0xf0000000 /* cpu-implementation field */ 37 38 #define PSR_VERS_SHIFT 24 39 #define PSR_IMPL_SHIFT 28 40 #define PSR_VERS_SHIFTED_MASK 0xf 41 #define PSR_IMPL_SHIFTED_MASK 0xf 42 43 #define PSR_IMPL_TI 0x4 44 #define PSR_IMPL_LEON 0xf 45 46 #ifdef __KERNEL__ 47 48 #ifndef __ASSEMBLY__ 49 /* Get the %psr register. */ 50 static inline unsigned int get_psr(void) 51 { 52 unsigned int psr; 53 __asm__ __volatile__( 54 "rd %%psr, %0\n\t" 55 "nop\n\t" 56 "nop\n\t" 57 "nop\n\t" 58 : "=r" (psr) 59 : /* no inputs */ 60 : "memory"); 61 62 return psr; 63 } 64 65 static inline void put_psr(unsigned int new_psr) 66 { 67 __asm__ __volatile__( 68 "wr %0, 0x0, %%psr\n\t" 69 "nop\n\t" 70 "nop\n\t" 71 "nop\n\t" 72 : /* no outputs */ 73 : "r" (new_psr) 74 : "memory", "cc"); 75 } 76 77 /* Get the %fsr register. Be careful, make sure the floating point 78 * enable bit is set in the %psr when you execute this or you will 79 * incur a trap. 80 */ 81 82 extern unsigned int fsr_storage; 83 84 static inline unsigned int get_fsr(void) 85 { 86 unsigned int fsr = 0; 87 88 __asm__ __volatile__( 89 "st %%fsr, %1\n\t" 90 "ld %1, %0\n\t" 91 : "=r" (fsr) 92 : "m" (fsr_storage)); 93 94 return fsr; 95 } 96 97 #endif /* !(__ASSEMBLY__) */ 98 99 #endif /* (__KERNEL__) */ 100 101 #endif /* !(__LINUX_SPARC_PSR_H) */ 102