1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pgtable.h: SpitFire page table operations. 4 * 5 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 */ 8 9 #ifndef _SPARC64_PGTABLE_H 10 #define _SPARC64_PGTABLE_H 11 12 /* This file contains the functions and defines necessary to modify and use 13 * the SpitFire page tables. 14 */ 15 16 #include <asm-generic/pgtable-nop4d.h> 17 #include <linux/compiler.h> 18 #include <linux/const.h> 19 #include <asm/types.h> 20 #include <asm/spitfire.h> 21 #include <asm/asi.h> 22 #include <asm/adi.h> 23 #include <asm/page.h> 24 #include <asm/processor.h> 25 26 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 27 * The page copy blockops can use 0x6000000 to 0x8000000. 28 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range. 29 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range. 30 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 31 * The vmalloc area spans 0x100000000 to 0x200000000. 32 * Since modules need to be in the lowest 32-bits of the address space, 33 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 34 * There is a single static kernel PMD which maps from 0x0 to address 35 * 0x400000000. 36 */ 37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 38 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL) 39 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL) 40 #define MODULES_VADDR _AC(0x0000000010000000,UL) 41 #define MODULES_LEN _AC(0x00000000e0000000,UL) 42 #define MODULES_END _AC(0x00000000f0000000,UL) 43 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 44 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 45 #define VMALLOC_START _AC(0x0000000100000000,UL) 46 #define VMEMMAP_BASE VMALLOC_END 47 48 /* PMD_SHIFT determines the size of the area a second-level page 49 * table can map 50 */ 51 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 53 #define PMD_MASK (~(PMD_SIZE-1)) 54 #define PMD_BITS (PAGE_SHIFT - 3) 55 56 /* PUD_SHIFT determines the size of the area a third-level page 57 * table can map 58 */ 59 #define PUD_SHIFT (PMD_SHIFT + PMD_BITS) 60 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) 61 #define PUD_MASK (~(PUD_SIZE-1)) 62 #define PUD_BITS (PAGE_SHIFT - 3) 63 64 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 65 #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS) 66 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 67 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 68 #define PGDIR_BITS (PAGE_SHIFT - 3) 69 70 #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS) 71 #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support 72 #endif 73 74 #if (PGDIR_SHIFT + PGDIR_BITS) != 53 75 #error Page table parameters do not cover virtual address space properly. 76 #endif 77 78 #if (PMD_SHIFT != HPAGE_SHIFT) 79 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. 80 #endif 81 82 #ifndef __ASSEMBLER__ 83 84 extern unsigned long VMALLOC_END; 85 86 #define vmemmap ((struct page *)VMEMMAP_BASE) 87 88 #include <linux/sched.h> 89 #include <asm/tlbflush.h> 90 91 bool kern_addr_valid(unsigned long addr); 92 93 /* Entries per page directory level. */ 94 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 95 #define PTRS_PER_PMD (1UL << PMD_BITS) 96 #define PTRS_PER_PUD (1UL << PUD_BITS) 97 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 98 99 #define pmd_ERROR(e) \ 100 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ 101 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) 102 #define pud_ERROR(e) \ 103 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \ 104 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0)) 105 #define pgd_ERROR(e) \ 106 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ 107 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) 108 109 #endif /* !(__ASSEMBLER__) */ 110 111 /* PTE bits which are the same in SUN4U and SUN4V format. */ 112 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 113 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 114 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 115 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ 116 #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE 117 118 /* SUN4U pte bits... */ 119 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 120 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 121 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 122 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 123 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 124 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 125 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 126 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 127 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ 128 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 129 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 130 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 131 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 132 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 133 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 134 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 135 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 136 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 137 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 138 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 139 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 140 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 141 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 142 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 143 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 144 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 145 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 146 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 147 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 148 149 /* SUN4V pte bits... */ 150 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 151 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 152 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 153 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 154 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 155 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 156 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 157 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ 158 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 159 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 160 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 161 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 162 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 163 /* Bit 9 is used to enable MCD corruption detection instead on M7 */ 164 #define _PAGE_MCD_4V _AC(0x0000000000000200,UL) /* Memory Corruption */ 165 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 166 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 167 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 168 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 169 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 170 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 171 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 172 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 173 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 174 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 175 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 176 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 177 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 178 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 179 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 180 181 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 182 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 183 184 #if REAL_HPAGE_SHIFT != 22 185 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up 186 #endif 187 188 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 189 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 190 191 /* We borrow bit 20 to store the exclusive marker in swap PTEs. */ 192 #define _PAGE_SWP_EXCLUSIVE _AC(0x0000000000100000, UL) 193 194 #ifndef __ASSEMBLER__ 195 196 pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 197 198 unsigned long pte_sz_bits(unsigned long size); 199 200 extern pgprot_t PAGE_KERNEL; 201 extern pgprot_t PAGE_KERNEL_LOCKED; 202 extern pgprot_t PAGE_COPY; 203 extern pgprot_t PAGE_SHARED; 204 205 /* XXX This ugliness is for the atyfb driver's sparc mmap() support. XXX */ 206 extern unsigned long _PAGE_IE; 207 extern unsigned long _PAGE_E; 208 extern unsigned long _PAGE_CACHE; 209 210 extern unsigned long pg_iobits; 211 extern unsigned long _PAGE_ALL_SZ_BITS; 212 213 /* PFNs are real physical page numbers. However, mem_map only begins to record 214 * per-page information starting at pfn_base. This is to handle systems where 215 * the first physical page in the machine is at some huge physical address, 216 * such as 4GB. This is common on a partitioned E10000, for example. 217 */ 218 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 219 { 220 unsigned long paddr = pfn << PAGE_SHIFT; 221 222 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 223 return __pte(paddr | pgprot_val(prot)); 224 } 225 226 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 227 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 228 { 229 pte_t pte = pfn_pte(page_nr, pgprot); 230 231 return __pmd(pte_val(pte)); 232 } 233 #endif 234 235 /* This one can be done with two shifts. */ 236 static inline unsigned long pte_pfn(pte_t pte) 237 { 238 unsigned long ret; 239 240 __asm__ __volatile__( 241 "\n661: sllx %1, %2, %0\n" 242 " srlx %0, %3, %0\n" 243 " .section .sun4v_2insn_patch, \"ax\"\n" 244 " .word 661b\n" 245 " sllx %1, %4, %0\n" 246 " srlx %0, %5, %0\n" 247 " .previous\n" 248 : "=r" (ret) 249 : "r" (pte_val(pte)), 250 "i" (21), "i" (21 + PAGE_SHIFT), 251 "i" (8), "i" (8 + PAGE_SHIFT)); 252 253 return ret; 254 } 255 #define pte_page(x) pfn_to_page(pte_pfn(x)) 256 257 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 258 { 259 unsigned long mask, tmp; 260 261 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) 262 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) 263 * 264 * Even if we use negation tricks the result is still a 6 265 * instruction sequence, so don't try to play fancy and just 266 * do the most straightforward implementation. 267 * 268 * Note: We encode this into 3 sun4v 2-insn patch sequences. 269 */ 270 271 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 272 __asm__ __volatile__( 273 "\n661: sethi %%uhi(%2), %1\n" 274 " sethi %%hi(%2), %0\n" 275 "\n662: or %1, %%ulo(%2), %1\n" 276 " or %0, %%lo(%2), %0\n" 277 "\n663: sllx %1, 32, %1\n" 278 " or %0, %1, %0\n" 279 " .section .sun4v_2insn_patch, \"ax\"\n" 280 " .word 661b\n" 281 " sethi %%uhi(%3), %1\n" 282 " sethi %%hi(%3), %0\n" 283 " .word 662b\n" 284 " or %1, %%ulo(%3), %1\n" 285 " or %0, %%lo(%3), %0\n" 286 " .word 663b\n" 287 " sllx %1, 32, %1\n" 288 " or %0, %1, %0\n" 289 " .previous\n" 290 " .section .sun_m7_2insn_patch, \"ax\"\n" 291 " .word 661b\n" 292 " sethi %%uhi(%4), %1\n" 293 " sethi %%hi(%4), %0\n" 294 " .word 662b\n" 295 " or %1, %%ulo(%4), %1\n" 296 " or %0, %%lo(%4), %0\n" 297 " .word 663b\n" 298 " sllx %1, 32, %1\n" 299 " or %0, %1, %0\n" 300 " .previous\n" 301 : "=r" (mask), "=r" (tmp) 302 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 303 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | 304 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), 305 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 306 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | 307 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V), 308 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 309 _PAGE_CP_4V | _PAGE_E_4V | 310 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); 311 312 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 313 } 314 315 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 316 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 317 { 318 pte_t pte = __pte(pmd_val(pmd)); 319 320 pte = pte_modify(pte, newprot); 321 322 return __pmd(pte_val(pte)); 323 } 324 #endif 325 326 static inline pgprot_t pgprot_noncached(pgprot_t prot) 327 { 328 unsigned long val = pgprot_val(prot); 329 330 __asm__ __volatile__( 331 "\n661: andn %0, %2, %0\n" 332 " or %0, %3, %0\n" 333 " .section .sun4v_2insn_patch, \"ax\"\n" 334 " .word 661b\n" 335 " andn %0, %4, %0\n" 336 " or %0, %5, %0\n" 337 " .previous\n" 338 " .section .sun_m7_2insn_patch, \"ax\"\n" 339 " .word 661b\n" 340 " andn %0, %6, %0\n" 341 " or %0, %5, %0\n" 342 " .previous\n" 343 : "=r" (val) 344 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 345 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V), 346 "i" (_PAGE_CP_4V)); 347 348 return __pgprot(val); 349 } 350 /* Various pieces of code check for platform support by ifdef testing 351 * on "pgprot_noncached". That's broken and should be fixed, but for 352 * now... 353 */ 354 #define pgprot_noncached pgprot_noncached 355 356 static inline unsigned long pte_dirty(pte_t pte) 357 { 358 unsigned long mask; 359 360 __asm__ __volatile__( 361 "\n661: mov %1, %0\n" 362 " nop\n" 363 " .section .sun4v_2insn_patch, \"ax\"\n" 364 " .word 661b\n" 365 " sethi %%uhi(%2), %0\n" 366 " sllx %0, 32, %0\n" 367 " .previous\n" 368 : "=r" (mask) 369 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 370 371 return (pte_val(pte) & mask); 372 } 373 374 static inline unsigned long pte_write(pte_t pte) 375 { 376 unsigned long mask; 377 378 __asm__ __volatile__( 379 "\n661: mov %1, %0\n" 380 " nop\n" 381 " .section .sun4v_2insn_patch, \"ax\"\n" 382 " .word 661b\n" 383 " sethi %%uhi(%2), %0\n" 384 " sllx %0, 32, %0\n" 385 " .previous\n" 386 : "=r" (mask) 387 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 388 389 return (pte_val(pte) & mask); 390 } 391 392 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 393 pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags); 394 #define arch_make_huge_pte arch_make_huge_pte 395 static inline unsigned long __pte_default_huge_mask(void) 396 { 397 unsigned long mask; 398 399 __asm__ __volatile__( 400 "\n661: sethi %%uhi(%1), %0\n" 401 " sllx %0, 32, %0\n" 402 " .section .sun4v_2insn_patch, \"ax\"\n" 403 " .word 661b\n" 404 " mov %2, %0\n" 405 " nop\n" 406 " .previous\n" 407 : "=r" (mask) 408 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 409 410 return mask; 411 } 412 413 static inline pte_t pte_mkhuge(pte_t pte) 414 { 415 return __pte(pte_val(pte) | __pte_default_huge_mask()); 416 } 417 418 static inline bool is_default_hugetlb_pte(pte_t pte) 419 { 420 unsigned long mask = __pte_default_huge_mask(); 421 422 return (pte_val(pte) & mask) == mask; 423 } 424 425 static inline bool is_hugetlb_pmd(pmd_t pmd) 426 { 427 return !!(pmd_val(pmd) & _PAGE_PMD_HUGE); 428 } 429 430 static inline bool is_hugetlb_pud(pud_t pud) 431 { 432 return !!(pud_val(pud) & _PAGE_PUD_HUGE); 433 } 434 435 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 436 static inline pmd_t pmd_mkhuge(pmd_t pmd) 437 { 438 pte_t pte = __pte(pmd_val(pmd)); 439 440 pte = pte_mkhuge(pte); 441 pte_val(pte) |= _PAGE_PMD_HUGE; 442 443 return __pmd(pte_val(pte)); 444 } 445 #endif 446 #else 447 static inline bool is_hugetlb_pte(pte_t pte) 448 { 449 return false; 450 } 451 #endif 452 453 static inline pte_t __pte_mkhwwrite(pte_t pte) 454 { 455 unsigned long val = pte_val(pte); 456 457 /* 458 * Note: we only want to set the HW writable bit if the SW writable bit 459 * and the SW dirty bit are set. 460 */ 461 __asm__ __volatile__( 462 "\n661: or %0, %2, %0\n" 463 " .section .sun4v_1insn_patch, \"ax\"\n" 464 " .word 661b\n" 465 " or %0, %3, %0\n" 466 " .previous\n" 467 : "=r" (val) 468 : "0" (val), "i" (_PAGE_W_4U), "i" (_PAGE_W_4V)); 469 470 return __pte(val); 471 } 472 473 static inline pte_t pte_mkdirty(pte_t pte) 474 { 475 unsigned long val = pte_val(pte), mask; 476 477 __asm__ __volatile__( 478 "\n661: mov %1, %0\n" 479 " nop\n" 480 " .section .sun4v_2insn_patch, \"ax\"\n" 481 " .word 661b\n" 482 " sethi %%uhi(%2), %0\n" 483 " sllx %0, 32, %0\n" 484 " .previous\n" 485 : "=r" (mask) 486 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 487 488 pte = __pte(val | mask); 489 return pte_write(pte) ? __pte_mkhwwrite(pte) : pte; 490 } 491 492 static inline pte_t pte_mkclean(pte_t pte) 493 { 494 unsigned long val = pte_val(pte), tmp; 495 496 __asm__ __volatile__( 497 "\n661: andn %0, %3, %0\n" 498 " nop\n" 499 "\n662: nop\n" 500 " nop\n" 501 " .section .sun4v_2insn_patch, \"ax\"\n" 502 " .word 661b\n" 503 " sethi %%uhi(%4), %1\n" 504 " sllx %1, 32, %1\n" 505 " .word 662b\n" 506 " or %1, %%lo(%4), %1\n" 507 " andn %0, %1, %0\n" 508 " .previous\n" 509 : "=r" (val), "=r" (tmp) 510 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 511 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 512 513 return __pte(val); 514 } 515 516 static inline pte_t pte_mkwrite_novma(pte_t pte) 517 { 518 unsigned long val = pte_val(pte), mask; 519 520 __asm__ __volatile__( 521 "\n661: mov %1, %0\n" 522 " nop\n" 523 " .section .sun4v_2insn_patch, \"ax\"\n" 524 " .word 661b\n" 525 " sethi %%uhi(%2), %0\n" 526 " sllx %0, 32, %0\n" 527 " .previous\n" 528 : "=r" (mask) 529 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 530 531 pte = __pte(val | mask); 532 return pte_dirty(pte) ? __pte_mkhwwrite(pte) : pte; 533 } 534 535 static inline pte_t pte_wrprotect(pte_t pte) 536 { 537 unsigned long val = pte_val(pte), tmp; 538 539 __asm__ __volatile__( 540 "\n661: andn %0, %3, %0\n" 541 " nop\n" 542 "\n662: nop\n" 543 " nop\n" 544 " .section .sun4v_2insn_patch, \"ax\"\n" 545 " .word 661b\n" 546 " sethi %%uhi(%4), %1\n" 547 " sllx %1, 32, %1\n" 548 " .word 662b\n" 549 " or %1, %%lo(%4), %1\n" 550 " andn %0, %1, %0\n" 551 " .previous\n" 552 : "=r" (val), "=r" (tmp) 553 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 554 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 555 556 return __pte(val); 557 } 558 559 static inline pte_t pte_mkold(pte_t pte) 560 { 561 unsigned long mask; 562 563 __asm__ __volatile__( 564 "\n661: mov %1, %0\n" 565 " nop\n" 566 " .section .sun4v_2insn_patch, \"ax\"\n" 567 " .word 661b\n" 568 " sethi %%uhi(%2), %0\n" 569 " sllx %0, 32, %0\n" 570 " .previous\n" 571 : "=r" (mask) 572 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 573 574 mask |= _PAGE_R; 575 576 return __pte(pte_val(pte) & ~mask); 577 } 578 579 static inline pte_t pte_mkyoung(pte_t pte) 580 { 581 unsigned long mask; 582 583 __asm__ __volatile__( 584 "\n661: mov %1, %0\n" 585 " nop\n" 586 " .section .sun4v_2insn_patch, \"ax\"\n" 587 " .word 661b\n" 588 " sethi %%uhi(%2), %0\n" 589 " sllx %0, 32, %0\n" 590 " .previous\n" 591 : "=r" (mask) 592 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 593 594 mask |= _PAGE_R; 595 596 return __pte(pte_val(pte) | mask); 597 } 598 599 static inline pte_t pte_mkspecial(pte_t pte) 600 { 601 pte_val(pte) |= _PAGE_SPECIAL; 602 return pte; 603 } 604 605 static inline pte_t pte_mkmcd(pte_t pte) 606 { 607 pte_val(pte) |= _PAGE_MCD_4V; 608 return pte; 609 } 610 611 static inline pte_t pte_mknotmcd(pte_t pte) 612 { 613 pte_val(pte) &= ~_PAGE_MCD_4V; 614 return pte; 615 } 616 617 static inline unsigned long pte_young(pte_t pte) 618 { 619 unsigned long mask; 620 621 __asm__ __volatile__( 622 "\n661: mov %1, %0\n" 623 " nop\n" 624 " .section .sun4v_2insn_patch, \"ax\"\n" 625 " .word 661b\n" 626 " sethi %%uhi(%2), %0\n" 627 " sllx %0, 32, %0\n" 628 " .previous\n" 629 : "=r" (mask) 630 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 631 632 return (pte_val(pte) & mask); 633 } 634 635 static inline unsigned long pte_exec(pte_t pte) 636 { 637 unsigned long mask; 638 639 __asm__ __volatile__( 640 "\n661: sethi %%hi(%1), %0\n" 641 " .section .sun4v_1insn_patch, \"ax\"\n" 642 " .word 661b\n" 643 " mov %2, %0\n" 644 " .previous\n" 645 : "=r" (mask) 646 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 647 648 return (pte_val(pte) & mask); 649 } 650 651 static inline unsigned long pte_present(pte_t pte) 652 { 653 unsigned long val = pte_val(pte); 654 655 __asm__ __volatile__( 656 "\n661: and %0, %2, %0\n" 657 " .section .sun4v_1insn_patch, \"ax\"\n" 658 " .word 661b\n" 659 " and %0, %3, %0\n" 660 " .previous\n" 661 : "=r" (val) 662 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 663 664 return val; 665 } 666 667 #define pte_accessible pte_accessible 668 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 669 { 670 return pte_val(a) & _PAGE_VALID; 671 } 672 673 static inline unsigned long pte_special(pte_t pte) 674 { 675 return pte_val(pte) & _PAGE_SPECIAL; 676 } 677 678 #define pmd_leaf pmd_leaf 679 static inline bool pmd_leaf(pmd_t pmd) 680 { 681 pte_t pte = __pte(pmd_val(pmd)); 682 683 return pte_val(pte) & _PAGE_PMD_HUGE; 684 } 685 686 static inline unsigned long pmd_pfn(pmd_t pmd) 687 { 688 pte_t pte = __pte(pmd_val(pmd)); 689 690 return pte_pfn(pte); 691 } 692 693 #define pmd_write pmd_write 694 static inline unsigned long pmd_write(pmd_t pmd) 695 { 696 pte_t pte = __pte(pmd_val(pmd)); 697 698 return pte_write(pte); 699 } 700 701 #define pud_write(pud) pte_write(__pte(pud_val(pud))) 702 703 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 704 #define pmd_dirty pmd_dirty 705 static inline unsigned long pmd_dirty(pmd_t pmd) 706 { 707 pte_t pte = __pte(pmd_val(pmd)); 708 709 return pte_dirty(pte); 710 } 711 712 #define pmd_young pmd_young 713 static inline unsigned long pmd_young(pmd_t pmd) 714 { 715 pte_t pte = __pte(pmd_val(pmd)); 716 717 return pte_young(pte); 718 } 719 720 static inline unsigned long pmd_trans_huge(pmd_t pmd) 721 { 722 pte_t pte = __pte(pmd_val(pmd)); 723 724 return pte_val(pte) & _PAGE_PMD_HUGE; 725 } 726 727 static inline pmd_t pmd_mkold(pmd_t pmd) 728 { 729 pte_t pte = __pte(pmd_val(pmd)); 730 731 pte = pte_mkold(pte); 732 733 return __pmd(pte_val(pte)); 734 } 735 736 static inline pmd_t pmd_wrprotect(pmd_t pmd) 737 { 738 pte_t pte = __pte(pmd_val(pmd)); 739 740 pte = pte_wrprotect(pte); 741 742 return __pmd(pte_val(pte)); 743 } 744 745 static inline pmd_t pmd_mkdirty(pmd_t pmd) 746 { 747 pte_t pte = __pte(pmd_val(pmd)); 748 749 pte = pte_mkdirty(pte); 750 751 return __pmd(pte_val(pte)); 752 } 753 754 static inline pmd_t pmd_mkclean(pmd_t pmd) 755 { 756 pte_t pte = __pte(pmd_val(pmd)); 757 758 pte = pte_mkclean(pte); 759 760 return __pmd(pte_val(pte)); 761 } 762 763 static inline pmd_t pmd_mkyoung(pmd_t pmd) 764 { 765 pte_t pte = __pte(pmd_val(pmd)); 766 767 pte = pte_mkyoung(pte); 768 769 return __pmd(pte_val(pte)); 770 } 771 772 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 773 { 774 pte_t pte = __pte(pmd_val(pmd)); 775 776 pte = pte_mkwrite_novma(pte); 777 778 return __pmd(pte_val(pte)); 779 } 780 781 #define pmd_pgprot pmd_pgprot 782 static inline pgprot_t pmd_pgprot(pmd_t entry) 783 { 784 unsigned long val = pmd_val(entry); 785 786 return __pgprot(val); 787 } 788 #endif 789 790 static inline int pmd_present(pmd_t pmd) 791 { 792 return pmd_val(pmd) != 0UL; 793 } 794 795 #define pmd_none(pmd) (!pmd_val(pmd)) 796 797 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is 798 * very simple, it's just the physical address. PTE tables are of 799 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and 800 * the top bits outside of the range of any physical address size we 801 * support are clear as well. We also validate the physical itself. 802 */ 803 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 804 805 #define pud_none(pud) (!pud_val(pud)) 806 807 #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK) 808 809 #define p4d_none(p4d) (!p4d_val(p4d)) 810 811 #define p4d_bad(p4d) (p4d_val(p4d) & ~PAGE_MASK) 812 813 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 814 void set_pmd_at(struct mm_struct *mm, unsigned long addr, 815 pmd_t *pmdp, pmd_t pmd); 816 #else 817 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 818 pmd_t *pmdp, pmd_t pmd) 819 { 820 *pmdp = pmd; 821 } 822 #endif 823 824 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 825 { 826 unsigned long val = __pa((unsigned long) (ptep)); 827 828 pmd_val(*pmdp) = val; 829 } 830 831 #define pud_set(pudp, pmdp) \ 832 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) 833 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 834 { 835 pte_t pte = __pte(pmd_val(pmd)); 836 unsigned long pfn; 837 838 pfn = pte_pfn(pte); 839 840 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 841 } 842 843 static inline pmd_t *pud_pgtable(pud_t pud) 844 { 845 pte_t pte = __pte(pud_val(pud)); 846 unsigned long pfn; 847 848 pfn = pte_pfn(pte); 849 850 return ((pmd_t *) __va(pfn << PAGE_SHIFT)); 851 } 852 853 #define pmd_page(pmd) virt_to_page((void *)pmd_page_vaddr(pmd)) 854 #define pud_page(pud) virt_to_page((void *)pud_pgtable(pud)) 855 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 856 #define pud_present(pud) (pud_val(pud) != 0U) 857 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 858 #define p4d_pgtable(p4d) \ 859 ((pud_t *) __va(p4d_val(p4d))) 860 #define p4d_present(p4d) (p4d_val(p4d) != 0U) 861 #define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL) 862 863 /* only used by the stubbed out hugetlb gup code, should never be called */ 864 #define p4d_page(p4d) NULL 865 866 #define pud_leaf pud_leaf 867 static inline bool pud_leaf(pud_t pud) 868 { 869 pte_t pte = __pte(pud_val(pud)); 870 871 return pte_val(pte) & _PAGE_PMD_HUGE; 872 } 873 874 #define pud_pfn pud_pfn 875 static inline unsigned long pud_pfn(pud_t pud) 876 { 877 pte_t pte = __pte(pud_val(pud)); 878 879 return pte_pfn(pte); 880 } 881 882 /* Same in both SUN4V and SUN4U. */ 883 #define pte_none(pte) (!pte_val(pte)) 884 885 #define p4d_set(p4dp, pudp) \ 886 (p4d_val(*(p4dp)) = (__pa((unsigned long) (pudp)))) 887 888 /* We cannot include <linux/mm_types.h> at this point yet: */ 889 extern struct mm_struct init_mm; 890 891 /* Actual page table PTE updates. */ 892 void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 893 pte_t *ptep, pte_t orig, int fullmm, 894 unsigned int hugepage_shift); 895 896 static void maybe_tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 897 pte_t *ptep, pte_t orig, int fullmm, 898 unsigned int hugepage_shift) 899 { 900 /* It is more efficient to let flush_tlb_kernel_range() 901 * handle init_mm tlb flushes. 902 * 903 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 904 * and SUN4V pte layout, so this inline test is fine. 905 */ 906 if (likely(mm != &init_mm) && pte_accessible(mm, orig)) 907 tlb_batch_add(mm, vaddr, ptep, orig, fullmm, hugepage_shift); 908 } 909 910 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 911 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 912 unsigned long addr, 913 pmd_t *pmdp) 914 { 915 pmd_t pmd = *pmdp; 916 set_pmd_at(mm, addr, pmdp, __pmd(0UL)); 917 return pmd; 918 } 919 920 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 921 pte_t *ptep, pte_t pte, int fullmm) 922 { 923 pte_t orig = *ptep; 924 925 *ptep = pte; 926 maybe_tlb_batch_add(mm, addr, ptep, orig, fullmm, PAGE_SHIFT); 927 } 928 929 #define PFN_PTE_SHIFT PAGE_SHIFT 930 931 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 932 pte_t *ptep, pte_t pte, unsigned int nr) 933 { 934 for (;;) { 935 __set_pte_at(mm, addr, ptep, pte, 0); 936 if (--nr == 0) 937 break; 938 ptep++; 939 pte_val(pte) += PAGE_SIZE; 940 addr += PAGE_SIZE; 941 } 942 } 943 #define set_ptes set_ptes 944 945 #define pte_clear(mm,addr,ptep) \ 946 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 947 948 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 949 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 950 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 951 952 #ifdef DCACHE_ALIASING_POSSIBLE 953 #define __HAVE_ARCH_MOVE_PTE 954 #define move_pte(pte, old_addr, new_addr) \ 955 ({ \ 956 pte_t newpte = (pte); \ 957 if (tlb_type != hypervisor && pte_present(pte)) { \ 958 unsigned long this_pfn = pte_pfn(pte); \ 959 \ 960 if (pfn_valid(this_pfn) && \ 961 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 962 flush_dcache_folio_all(current->mm, \ 963 page_folio(pfn_to_page(this_pfn))); \ 964 } \ 965 newpte; \ 966 }) 967 #endif 968 969 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 970 971 void paging_init(void); 972 unsigned long find_ecache_flush_span(unsigned long size); 973 974 struct seq_file; 975 void mmu_info(struct seq_file *); 976 977 struct vm_area_struct; 978 void update_mmu_cache_range(struct vm_fault *, struct vm_area_struct *, 979 unsigned long addr, pte_t *ptep, unsigned int nr); 980 #define update_mmu_cache(vma, addr, ptep) \ 981 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 982 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 983 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 984 pmd_t *pmd); 985 986 #define __HAVE_ARCH_PMDP_INVALIDATE 987 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 988 pmd_t *pmdp); 989 990 #define __HAVE_ARCH_PGTABLE_DEPOSIT 991 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 992 pgtable_t pgtable); 993 994 #define __HAVE_ARCH_PGTABLE_WITHDRAW 995 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 996 #endif 997 998 /* 999 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 1000 * are !pte_none() && !pte_present(). 1001 * 1002 * Format of swap PTEs: 1003 * 1004 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 1005 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1006 * <--------------------------- offset --------------------------- 1007 * 1008 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1009 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1010 * --------------------> E <-- type ---> <------- zeroes --------> 1011 */ 1012 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0x7fUL) 1013 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 1014 #define __swp_entry(type, offset) \ 1015 ( (swp_entry_t) \ 1016 { \ 1017 ((((long)(type) & 0x7fUL) << PAGE_SHIFT) | \ 1018 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 1019 } ) 1020 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1021 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1022 1023 static inline bool pte_swp_exclusive(pte_t pte) 1024 { 1025 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 1026 } 1027 1028 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1029 { 1030 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 1031 } 1032 1033 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1034 { 1035 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 1036 } 1037 1038 int page_in_phys_avail(unsigned long paddr); 1039 1040 /* 1041 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 1042 * its high 4 bits. These macros/functions put it there or get it from there. 1043 */ 1044 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 1045 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 1046 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 1047 1048 void adi_restore_tags(struct mm_struct *mm, struct vm_area_struct *vma, 1049 unsigned long addr, pte_t pte); 1050 1051 int adi_save_tags(struct mm_struct *mm, struct vm_area_struct *vma, 1052 unsigned long addr, pte_t oldpte); 1053 1054 #define __HAVE_ARCH_DO_SWAP_PAGE 1055 static inline void arch_do_swap_page(struct mm_struct *mm, 1056 struct vm_area_struct *vma, 1057 unsigned long addr, 1058 pte_t pte, pte_t oldpte) 1059 { 1060 /* If this is a new page being mapped in, there can be no 1061 * ADI tags stored away for this page. Skip looking for 1062 * stored tags 1063 */ 1064 if (pte_none(oldpte)) 1065 return; 1066 1067 if (adi_state.enabled && (pte_val(pte) & _PAGE_MCD_4V)) 1068 adi_restore_tags(mm, vma, addr, pte); 1069 } 1070 1071 #define __HAVE_ARCH_UNMAP_ONE 1072 static inline int arch_unmap_one(struct mm_struct *mm, 1073 struct vm_area_struct *vma, 1074 unsigned long addr, pte_t oldpte) 1075 { 1076 if (adi_state.enabled && (pte_val(oldpte) & _PAGE_MCD_4V)) 1077 return adi_save_tags(mm, vma, addr, oldpte); 1078 return 0; 1079 } 1080 1081 static inline unsigned long io_remap_pfn_range_pfn(unsigned long pfn, 1082 unsigned long size) 1083 { 1084 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 1085 int space = GET_IOSPACE(pfn); 1086 unsigned long phys_base; 1087 1088 phys_base = offset | (((unsigned long) space) << 32UL); 1089 1090 return phys_base >> PAGE_SHIFT; 1091 } 1092 #define io_remap_pfn_range_pfn io_remap_pfn_range_pfn 1093 1094 static inline unsigned long __untagged_addr(unsigned long start) 1095 { 1096 if (adi_capable()) { 1097 long addr = start; 1098 1099 /* If userspace has passed a versioned address, kernel 1100 * will not find it in the VMAs since it does not store 1101 * the version tags in the list of VMAs. Storing version 1102 * tags in list of VMAs is impractical since they can be 1103 * changed any time from userspace without dropping into 1104 * kernel. Any address search in VMAs will be done with 1105 * non-versioned addresses. Ensure the ADI version bits 1106 * are dropped here by sign extending the last bit before 1107 * ADI bits. IOMMU does not implement version tags. 1108 */ 1109 return (addr << (long)adi_nbits()) >> (long)adi_nbits(); 1110 } 1111 1112 return start; 1113 } 1114 #define untagged_addr(addr) \ 1115 ((__typeof__(addr))(__untagged_addr((unsigned long)(addr)))) 1116 1117 static inline bool pte_access_permitted(pte_t pte, bool write) 1118 { 1119 u64 prot; 1120 1121 if (tlb_type == hypervisor) { 1122 prot = _PAGE_PRESENT_4V | _PAGE_P_4V; 1123 if (write) 1124 prot |= _PAGE_WRITE_4V; 1125 } else { 1126 prot = _PAGE_PRESENT_4U | _PAGE_P_4U; 1127 if (write) 1128 prot |= _PAGE_WRITE_4U; 1129 } 1130 1131 return (pte_val(pte) & (prot | _PAGE_SPECIAL)) == prot; 1132 } 1133 #define pte_access_permitted pte_access_permitted 1134 1135 /* We provide our own get_unmapped_area to cope with VA holes and 1136 * SHM area cache aliasing for userland. 1137 */ 1138 #define HAVE_ARCH_UNMAPPED_AREA 1139 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1140 1141 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 1142 * the largest alignment possible such that larget PTEs can be used. 1143 */ 1144 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 1145 unsigned long, unsigned long, 1146 unsigned long); 1147 #define HAVE_ARCH_FB_UNMAPPED_AREA 1148 1149 void sun4v_register_fault_status(void); 1150 void sun4v_ktsb_register(void); 1151 void __init cheetah_ecache_flush_init(void); 1152 void sun4v_patch_tlb_handlers(void); 1153 1154 extern unsigned long cmdline_memory_size; 1155 1156 asmlinkage void do_sparc64_fault(struct pt_regs *regs); 1157 1158 #define pmd_pgtable(PMD) ((pte_t *)pmd_page_vaddr(PMD)) 1159 1160 #ifdef CONFIG_HUGETLB_PAGE 1161 1162 #define pud_leaf_size pud_leaf_size 1163 extern unsigned long pud_leaf_size(pud_t pud); 1164 1165 #define pmd_leaf_size pmd_leaf_size 1166 extern unsigned long pmd_leaf_size(pmd_t pmd); 1167 1168 #define pte_leaf_size pte_leaf_size 1169 extern unsigned long pte_leaf_size(pte_t pte); 1170 1171 #endif /* CONFIG_HUGETLB_PAGE */ 1172 1173 #endif /* !(__ASSEMBLER__) */ 1174 1175 #endif /* !(_SPARC64_PGTABLE_H) */ 1176