1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pgtable.h: SpitFire page table operations. 4 * 5 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 */ 8 9 #ifndef _SPARC64_PGTABLE_H 10 #define _SPARC64_PGTABLE_H 11 12 /* This file contains the functions and defines necessary to modify and use 13 * the SpitFire page tables. 14 */ 15 16 #include <asm-generic/pgtable-nop4d.h> 17 #include <linux/compiler.h> 18 #include <linux/const.h> 19 #include <asm/types.h> 20 #include <asm/spitfire.h> 21 #include <asm/asi.h> 22 #include <asm/adi.h> 23 #include <asm/page.h> 24 #include <asm/processor.h> 25 26 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 27 * The page copy blockops can use 0x6000000 to 0x8000000. 28 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range. 29 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range. 30 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 31 * The vmalloc area spans 0x100000000 to 0x200000000. 32 * Since modules need to be in the lowest 32-bits of the address space, 33 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 34 * There is a single static kernel PMD which maps from 0x0 to address 35 * 0x400000000. 36 */ 37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 38 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL) 39 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL) 40 #define MODULES_VADDR _AC(0x0000000010000000,UL) 41 #define MODULES_LEN _AC(0x00000000e0000000,UL) 42 #define MODULES_END _AC(0x00000000f0000000,UL) 43 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 44 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 45 #define VMALLOC_START _AC(0x0000000100000000,UL) 46 #define VMEMMAP_BASE VMALLOC_END 47 48 /* PMD_SHIFT determines the size of the area a second-level page 49 * table can map 50 */ 51 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 53 #define PMD_MASK (~(PMD_SIZE-1)) 54 #define PMD_BITS (PAGE_SHIFT - 3) 55 56 /* PUD_SHIFT determines the size of the area a third-level page 57 * table can map 58 */ 59 #define PUD_SHIFT (PMD_SHIFT + PMD_BITS) 60 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) 61 #define PUD_MASK (~(PUD_SIZE-1)) 62 #define PUD_BITS (PAGE_SHIFT - 3) 63 64 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 65 #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS) 66 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 67 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 68 #define PGDIR_BITS (PAGE_SHIFT - 3) 69 70 #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS) 71 #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support 72 #endif 73 74 #if (PGDIR_SHIFT + PGDIR_BITS) != 53 75 #error Page table parameters do not cover virtual address space properly. 76 #endif 77 78 #if (PMD_SHIFT != HPAGE_SHIFT) 79 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. 80 #endif 81 82 #ifndef __ASSEMBLY__ 83 84 extern unsigned long VMALLOC_END; 85 86 #define vmemmap ((struct page *)VMEMMAP_BASE) 87 88 #include <linux/sched.h> 89 90 bool kern_addr_valid(unsigned long addr); 91 92 /* Entries per page directory level. */ 93 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 94 #define PTRS_PER_PMD (1UL << PMD_BITS) 95 #define PTRS_PER_PUD (1UL << PUD_BITS) 96 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 97 98 #define pmd_ERROR(e) \ 99 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ 100 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) 101 #define pud_ERROR(e) \ 102 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \ 103 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0)) 104 #define pgd_ERROR(e) \ 105 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ 106 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) 107 108 #endif /* !(__ASSEMBLY__) */ 109 110 /* PTE bits which are the same in SUN4U and SUN4V format. */ 111 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 112 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 113 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 114 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ 115 #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE 116 117 /* SUN4U pte bits... */ 118 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 119 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 120 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 121 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 122 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 123 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 124 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 125 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 126 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ 127 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 128 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 129 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 130 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 131 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 132 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 133 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 134 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 135 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 136 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 137 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 138 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 139 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 140 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 141 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 142 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 143 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 144 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 145 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 146 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 147 148 /* SUN4V pte bits... */ 149 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 150 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 151 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 152 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 153 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 154 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 155 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 156 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ 157 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 158 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 159 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 160 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 161 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 162 /* Bit 9 is used to enable MCD corruption detection instead on M7 */ 163 #define _PAGE_MCD_4V _AC(0x0000000000000200,UL) /* Memory Corruption */ 164 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 165 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 166 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 167 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 168 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 169 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 170 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 171 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 172 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 173 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 174 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 175 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 176 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 177 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 178 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 179 180 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 181 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 182 183 #if REAL_HPAGE_SHIFT != 22 184 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up 185 #endif 186 187 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 188 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 189 190 /* We borrow bit 20 to store the exclusive marker in swap PTEs. */ 191 #define _PAGE_SWP_EXCLUSIVE _AC(0x0000000000100000, UL) 192 193 #ifndef __ASSEMBLY__ 194 195 pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 196 197 unsigned long pte_sz_bits(unsigned long size); 198 199 extern pgprot_t PAGE_KERNEL; 200 extern pgprot_t PAGE_KERNEL_LOCKED; 201 extern pgprot_t PAGE_COPY; 202 extern pgprot_t PAGE_SHARED; 203 204 /* XXX This ugliness is for the atyfb driver's sparc mmap() support. XXX */ 205 extern unsigned long _PAGE_IE; 206 extern unsigned long _PAGE_E; 207 extern unsigned long _PAGE_CACHE; 208 209 extern unsigned long pg_iobits; 210 extern unsigned long _PAGE_ALL_SZ_BITS; 211 212 extern struct page *mem_map_zero; 213 #define ZERO_PAGE(vaddr) (mem_map_zero) 214 215 /* PFNs are real physical page numbers. However, mem_map only begins to record 216 * per-page information starting at pfn_base. This is to handle systems where 217 * the first physical page in the machine is at some huge physical address, 218 * such as 4GB. This is common on a partitioned E10000, for example. 219 */ 220 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 221 { 222 unsigned long paddr = pfn << PAGE_SHIFT; 223 224 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 225 return __pte(paddr | pgprot_val(prot)); 226 } 227 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 228 229 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 230 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 231 { 232 pte_t pte = pfn_pte(page_nr, pgprot); 233 234 return __pmd(pte_val(pte)); 235 } 236 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 237 #endif 238 239 /* This one can be done with two shifts. */ 240 static inline unsigned long pte_pfn(pte_t pte) 241 { 242 unsigned long ret; 243 244 __asm__ __volatile__( 245 "\n661: sllx %1, %2, %0\n" 246 " srlx %0, %3, %0\n" 247 " .section .sun4v_2insn_patch, \"ax\"\n" 248 " .word 661b\n" 249 " sllx %1, %4, %0\n" 250 " srlx %0, %5, %0\n" 251 " .previous\n" 252 : "=r" (ret) 253 : "r" (pte_val(pte)), 254 "i" (21), "i" (21 + PAGE_SHIFT), 255 "i" (8), "i" (8 + PAGE_SHIFT)); 256 257 return ret; 258 } 259 #define pte_page(x) pfn_to_page(pte_pfn(x)) 260 261 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 262 { 263 unsigned long mask, tmp; 264 265 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) 266 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) 267 * 268 * Even if we use negation tricks the result is still a 6 269 * instruction sequence, so don't try to play fancy and just 270 * do the most straightforward implementation. 271 * 272 * Note: We encode this into 3 sun4v 2-insn patch sequences. 273 */ 274 275 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 276 __asm__ __volatile__( 277 "\n661: sethi %%uhi(%2), %1\n" 278 " sethi %%hi(%2), %0\n" 279 "\n662: or %1, %%ulo(%2), %1\n" 280 " or %0, %%lo(%2), %0\n" 281 "\n663: sllx %1, 32, %1\n" 282 " or %0, %1, %0\n" 283 " .section .sun4v_2insn_patch, \"ax\"\n" 284 " .word 661b\n" 285 " sethi %%uhi(%3), %1\n" 286 " sethi %%hi(%3), %0\n" 287 " .word 662b\n" 288 " or %1, %%ulo(%3), %1\n" 289 " or %0, %%lo(%3), %0\n" 290 " .word 663b\n" 291 " sllx %1, 32, %1\n" 292 " or %0, %1, %0\n" 293 " .previous\n" 294 " .section .sun_m7_2insn_patch, \"ax\"\n" 295 " .word 661b\n" 296 " sethi %%uhi(%4), %1\n" 297 " sethi %%hi(%4), %0\n" 298 " .word 662b\n" 299 " or %1, %%ulo(%4), %1\n" 300 " or %0, %%lo(%4), %0\n" 301 " .word 663b\n" 302 " sllx %1, 32, %1\n" 303 " or %0, %1, %0\n" 304 " .previous\n" 305 : "=r" (mask), "=r" (tmp) 306 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 307 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | 308 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), 309 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 310 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | 311 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V), 312 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 313 _PAGE_CP_4V | _PAGE_E_4V | 314 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); 315 316 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 317 } 318 319 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 320 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 321 { 322 pte_t pte = __pte(pmd_val(pmd)); 323 324 pte = pte_modify(pte, newprot); 325 326 return __pmd(pte_val(pte)); 327 } 328 #endif 329 330 static inline pgprot_t pgprot_noncached(pgprot_t prot) 331 { 332 unsigned long val = pgprot_val(prot); 333 334 __asm__ __volatile__( 335 "\n661: andn %0, %2, %0\n" 336 " or %0, %3, %0\n" 337 " .section .sun4v_2insn_patch, \"ax\"\n" 338 " .word 661b\n" 339 " andn %0, %4, %0\n" 340 " or %0, %5, %0\n" 341 " .previous\n" 342 " .section .sun_m7_2insn_patch, \"ax\"\n" 343 " .word 661b\n" 344 " andn %0, %6, %0\n" 345 " or %0, %5, %0\n" 346 " .previous\n" 347 : "=r" (val) 348 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 349 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V), 350 "i" (_PAGE_CP_4V)); 351 352 return __pgprot(val); 353 } 354 /* Various pieces of code check for platform support by ifdef testing 355 * on "pgprot_noncached". That's broken and should be fixed, but for 356 * now... 357 */ 358 #define pgprot_noncached pgprot_noncached 359 360 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 361 pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags); 362 #define arch_make_huge_pte arch_make_huge_pte 363 static inline unsigned long __pte_default_huge_mask(void) 364 { 365 unsigned long mask; 366 367 __asm__ __volatile__( 368 "\n661: sethi %%uhi(%1), %0\n" 369 " sllx %0, 32, %0\n" 370 " .section .sun4v_2insn_patch, \"ax\"\n" 371 " .word 661b\n" 372 " mov %2, %0\n" 373 " nop\n" 374 " .previous\n" 375 : "=r" (mask) 376 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 377 378 return mask; 379 } 380 381 static inline pte_t pte_mkhuge(pte_t pte) 382 { 383 return __pte(pte_val(pte) | __pte_default_huge_mask()); 384 } 385 386 static inline bool is_default_hugetlb_pte(pte_t pte) 387 { 388 unsigned long mask = __pte_default_huge_mask(); 389 390 return (pte_val(pte) & mask) == mask; 391 } 392 393 static inline bool is_hugetlb_pmd(pmd_t pmd) 394 { 395 return !!(pmd_val(pmd) & _PAGE_PMD_HUGE); 396 } 397 398 static inline bool is_hugetlb_pud(pud_t pud) 399 { 400 return !!(pud_val(pud) & _PAGE_PUD_HUGE); 401 } 402 403 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 404 static inline pmd_t pmd_mkhuge(pmd_t pmd) 405 { 406 pte_t pte = __pte(pmd_val(pmd)); 407 408 pte = pte_mkhuge(pte); 409 pte_val(pte) |= _PAGE_PMD_HUGE; 410 411 return __pmd(pte_val(pte)); 412 } 413 #endif 414 #else 415 static inline bool is_hugetlb_pte(pte_t pte) 416 { 417 return false; 418 } 419 #endif 420 421 static inline pte_t pte_mkdirty(pte_t pte) 422 { 423 unsigned long val = pte_val(pte), tmp; 424 425 __asm__ __volatile__( 426 "\n661: or %0, %3, %0\n" 427 " nop\n" 428 "\n662: nop\n" 429 " nop\n" 430 " .section .sun4v_2insn_patch, \"ax\"\n" 431 " .word 661b\n" 432 " sethi %%uhi(%4), %1\n" 433 " sllx %1, 32, %1\n" 434 " .word 662b\n" 435 " or %1, %%lo(%4), %1\n" 436 " or %0, %1, %0\n" 437 " .previous\n" 438 : "=r" (val), "=r" (tmp) 439 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 440 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 441 442 return __pte(val); 443 } 444 445 static inline pte_t pte_mkclean(pte_t pte) 446 { 447 unsigned long val = pte_val(pte), tmp; 448 449 __asm__ __volatile__( 450 "\n661: andn %0, %3, %0\n" 451 " nop\n" 452 "\n662: nop\n" 453 " nop\n" 454 " .section .sun4v_2insn_patch, \"ax\"\n" 455 " .word 661b\n" 456 " sethi %%uhi(%4), %1\n" 457 " sllx %1, 32, %1\n" 458 " .word 662b\n" 459 " or %1, %%lo(%4), %1\n" 460 " andn %0, %1, %0\n" 461 " .previous\n" 462 : "=r" (val), "=r" (tmp) 463 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 464 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 465 466 return __pte(val); 467 } 468 469 static inline pte_t pte_mkwrite(pte_t pte) 470 { 471 unsigned long val = pte_val(pte), mask; 472 473 __asm__ __volatile__( 474 "\n661: mov %1, %0\n" 475 " nop\n" 476 " .section .sun4v_2insn_patch, \"ax\"\n" 477 " .word 661b\n" 478 " sethi %%uhi(%2), %0\n" 479 " sllx %0, 32, %0\n" 480 " .previous\n" 481 : "=r" (mask) 482 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 483 484 return __pte(val | mask); 485 } 486 487 static inline pte_t pte_wrprotect(pte_t pte) 488 { 489 unsigned long val = pte_val(pte), tmp; 490 491 __asm__ __volatile__( 492 "\n661: andn %0, %3, %0\n" 493 " nop\n" 494 "\n662: nop\n" 495 " nop\n" 496 " .section .sun4v_2insn_patch, \"ax\"\n" 497 " .word 661b\n" 498 " sethi %%uhi(%4), %1\n" 499 " sllx %1, 32, %1\n" 500 " .word 662b\n" 501 " or %1, %%lo(%4), %1\n" 502 " andn %0, %1, %0\n" 503 " .previous\n" 504 : "=r" (val), "=r" (tmp) 505 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 506 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 507 508 return __pte(val); 509 } 510 511 static inline pte_t pte_mkold(pte_t pte) 512 { 513 unsigned long mask; 514 515 __asm__ __volatile__( 516 "\n661: mov %1, %0\n" 517 " nop\n" 518 " .section .sun4v_2insn_patch, \"ax\"\n" 519 " .word 661b\n" 520 " sethi %%uhi(%2), %0\n" 521 " sllx %0, 32, %0\n" 522 " .previous\n" 523 : "=r" (mask) 524 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 525 526 mask |= _PAGE_R; 527 528 return __pte(pte_val(pte) & ~mask); 529 } 530 531 static inline pte_t pte_mkyoung(pte_t pte) 532 { 533 unsigned long mask; 534 535 __asm__ __volatile__( 536 "\n661: mov %1, %0\n" 537 " nop\n" 538 " .section .sun4v_2insn_patch, \"ax\"\n" 539 " .word 661b\n" 540 " sethi %%uhi(%2), %0\n" 541 " sllx %0, 32, %0\n" 542 " .previous\n" 543 : "=r" (mask) 544 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 545 546 mask |= _PAGE_R; 547 548 return __pte(pte_val(pte) | mask); 549 } 550 551 static inline pte_t pte_mkspecial(pte_t pte) 552 { 553 pte_val(pte) |= _PAGE_SPECIAL; 554 return pte; 555 } 556 557 static inline pte_t pte_mkmcd(pte_t pte) 558 { 559 pte_val(pte) |= _PAGE_MCD_4V; 560 return pte; 561 } 562 563 static inline pte_t pte_mknotmcd(pte_t pte) 564 { 565 pte_val(pte) &= ~_PAGE_MCD_4V; 566 return pte; 567 } 568 569 static inline unsigned long pte_young(pte_t pte) 570 { 571 unsigned long mask; 572 573 __asm__ __volatile__( 574 "\n661: mov %1, %0\n" 575 " nop\n" 576 " .section .sun4v_2insn_patch, \"ax\"\n" 577 " .word 661b\n" 578 " sethi %%uhi(%2), %0\n" 579 " sllx %0, 32, %0\n" 580 " .previous\n" 581 : "=r" (mask) 582 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 583 584 return (pte_val(pte) & mask); 585 } 586 587 static inline unsigned long pte_dirty(pte_t pte) 588 { 589 unsigned long mask; 590 591 __asm__ __volatile__( 592 "\n661: mov %1, %0\n" 593 " nop\n" 594 " .section .sun4v_2insn_patch, \"ax\"\n" 595 " .word 661b\n" 596 " sethi %%uhi(%2), %0\n" 597 " sllx %0, 32, %0\n" 598 " .previous\n" 599 : "=r" (mask) 600 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 601 602 return (pte_val(pte) & mask); 603 } 604 605 static inline unsigned long pte_write(pte_t pte) 606 { 607 unsigned long mask; 608 609 __asm__ __volatile__( 610 "\n661: mov %1, %0\n" 611 " nop\n" 612 " .section .sun4v_2insn_patch, \"ax\"\n" 613 " .word 661b\n" 614 " sethi %%uhi(%2), %0\n" 615 " sllx %0, 32, %0\n" 616 " .previous\n" 617 : "=r" (mask) 618 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 619 620 return (pte_val(pte) & mask); 621 } 622 623 static inline unsigned long pte_exec(pte_t pte) 624 { 625 unsigned long mask; 626 627 __asm__ __volatile__( 628 "\n661: sethi %%hi(%1), %0\n" 629 " .section .sun4v_1insn_patch, \"ax\"\n" 630 " .word 661b\n" 631 " mov %2, %0\n" 632 " .previous\n" 633 : "=r" (mask) 634 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 635 636 return (pte_val(pte) & mask); 637 } 638 639 static inline unsigned long pte_present(pte_t pte) 640 { 641 unsigned long val = pte_val(pte); 642 643 __asm__ __volatile__( 644 "\n661: and %0, %2, %0\n" 645 " .section .sun4v_1insn_patch, \"ax\"\n" 646 " .word 661b\n" 647 " and %0, %3, %0\n" 648 " .previous\n" 649 : "=r" (val) 650 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 651 652 return val; 653 } 654 655 #define pte_accessible pte_accessible 656 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 657 { 658 return pte_val(a) & _PAGE_VALID; 659 } 660 661 static inline unsigned long pte_special(pte_t pte) 662 { 663 return pte_val(pte) & _PAGE_SPECIAL; 664 } 665 666 #define pmd_leaf pmd_large 667 static inline unsigned long pmd_large(pmd_t pmd) 668 { 669 pte_t pte = __pte(pmd_val(pmd)); 670 671 return pte_val(pte) & _PAGE_PMD_HUGE; 672 } 673 674 static inline unsigned long pmd_pfn(pmd_t pmd) 675 { 676 pte_t pte = __pte(pmd_val(pmd)); 677 678 return pte_pfn(pte); 679 } 680 681 #define pmd_write pmd_write 682 static inline unsigned long pmd_write(pmd_t pmd) 683 { 684 pte_t pte = __pte(pmd_val(pmd)); 685 686 return pte_write(pte); 687 } 688 689 #define pud_write(pud) pte_write(__pte(pud_val(pud))) 690 691 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 692 static inline unsigned long pmd_dirty(pmd_t pmd) 693 { 694 pte_t pte = __pte(pmd_val(pmd)); 695 696 return pte_dirty(pte); 697 } 698 699 #define pmd_young pmd_young 700 static inline unsigned long pmd_young(pmd_t pmd) 701 { 702 pte_t pte = __pte(pmd_val(pmd)); 703 704 return pte_young(pte); 705 } 706 707 static inline unsigned long pmd_trans_huge(pmd_t pmd) 708 { 709 pte_t pte = __pte(pmd_val(pmd)); 710 711 return pte_val(pte) & _PAGE_PMD_HUGE; 712 } 713 714 static inline pmd_t pmd_mkold(pmd_t pmd) 715 { 716 pte_t pte = __pte(pmd_val(pmd)); 717 718 pte = pte_mkold(pte); 719 720 return __pmd(pte_val(pte)); 721 } 722 723 static inline pmd_t pmd_wrprotect(pmd_t pmd) 724 { 725 pte_t pte = __pte(pmd_val(pmd)); 726 727 pte = pte_wrprotect(pte); 728 729 return __pmd(pte_val(pte)); 730 } 731 732 static inline pmd_t pmd_mkdirty(pmd_t pmd) 733 { 734 pte_t pte = __pte(pmd_val(pmd)); 735 736 pte = pte_mkdirty(pte); 737 738 return __pmd(pte_val(pte)); 739 } 740 741 static inline pmd_t pmd_mkclean(pmd_t pmd) 742 { 743 pte_t pte = __pte(pmd_val(pmd)); 744 745 pte = pte_mkclean(pte); 746 747 return __pmd(pte_val(pte)); 748 } 749 750 static inline pmd_t pmd_mkyoung(pmd_t pmd) 751 { 752 pte_t pte = __pte(pmd_val(pmd)); 753 754 pte = pte_mkyoung(pte); 755 756 return __pmd(pte_val(pte)); 757 } 758 759 static inline pmd_t pmd_mkwrite(pmd_t pmd) 760 { 761 pte_t pte = __pte(pmd_val(pmd)); 762 763 pte = pte_mkwrite(pte); 764 765 return __pmd(pte_val(pte)); 766 } 767 768 static inline pgprot_t pmd_pgprot(pmd_t entry) 769 { 770 unsigned long val = pmd_val(entry); 771 772 return __pgprot(val); 773 } 774 #endif 775 776 static inline int pmd_present(pmd_t pmd) 777 { 778 return pmd_val(pmd) != 0UL; 779 } 780 781 #define pmd_none(pmd) (!pmd_val(pmd)) 782 783 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is 784 * very simple, it's just the physical address. PTE tables are of 785 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and 786 * the top bits outside of the range of any physical address size we 787 * support are clear as well. We also validate the physical itself. 788 */ 789 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 790 791 #define pud_none(pud) (!pud_val(pud)) 792 793 #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK) 794 795 #define p4d_none(p4d) (!p4d_val(p4d)) 796 797 #define p4d_bad(p4d) (p4d_val(p4d) & ~PAGE_MASK) 798 799 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 800 void set_pmd_at(struct mm_struct *mm, unsigned long addr, 801 pmd_t *pmdp, pmd_t pmd); 802 #else 803 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 804 pmd_t *pmdp, pmd_t pmd) 805 { 806 *pmdp = pmd; 807 } 808 #endif 809 810 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 811 { 812 unsigned long val = __pa((unsigned long) (ptep)); 813 814 pmd_val(*pmdp) = val; 815 } 816 817 #define pud_set(pudp, pmdp) \ 818 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) 819 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 820 { 821 pte_t pte = __pte(pmd_val(pmd)); 822 unsigned long pfn; 823 824 pfn = pte_pfn(pte); 825 826 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 827 } 828 829 static inline pmd_t *pud_pgtable(pud_t pud) 830 { 831 pte_t pte = __pte(pud_val(pud)); 832 unsigned long pfn; 833 834 pfn = pte_pfn(pte); 835 836 return ((pmd_t *) __va(pfn << PAGE_SHIFT)); 837 } 838 839 #define pmd_page(pmd) virt_to_page((void *)pmd_page_vaddr(pmd)) 840 #define pud_page(pud) virt_to_page((void *)pud_pgtable(pud)) 841 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 842 #define pud_present(pud) (pud_val(pud) != 0U) 843 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 844 #define p4d_pgtable(p4d) \ 845 ((pud_t *) __va(p4d_val(p4d))) 846 #define p4d_present(p4d) (p4d_val(p4d) != 0U) 847 #define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL) 848 849 /* only used by the stubbed out hugetlb gup code, should never be called */ 850 #define p4d_page(p4d) NULL 851 852 #define pud_leaf pud_large 853 static inline unsigned long pud_large(pud_t pud) 854 { 855 pte_t pte = __pte(pud_val(pud)); 856 857 return pte_val(pte) & _PAGE_PMD_HUGE; 858 } 859 860 static inline unsigned long pud_pfn(pud_t pud) 861 { 862 pte_t pte = __pte(pud_val(pud)); 863 864 return pte_pfn(pte); 865 } 866 867 /* Same in both SUN4V and SUN4U. */ 868 #define pte_none(pte) (!pte_val(pte)) 869 870 #define p4d_set(p4dp, pudp) \ 871 (p4d_val(*(p4dp)) = (__pa((unsigned long) (pudp)))) 872 873 /* We cannot include <linux/mm_types.h> at this point yet: */ 874 extern struct mm_struct init_mm; 875 876 /* Actual page table PTE updates. */ 877 void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 878 pte_t *ptep, pte_t orig, int fullmm, 879 unsigned int hugepage_shift); 880 881 static void maybe_tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 882 pte_t *ptep, pte_t orig, int fullmm, 883 unsigned int hugepage_shift) 884 { 885 /* It is more efficient to let flush_tlb_kernel_range() 886 * handle init_mm tlb flushes. 887 * 888 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 889 * and SUN4V pte layout, so this inline test is fine. 890 */ 891 if (likely(mm != &init_mm) && pte_accessible(mm, orig)) 892 tlb_batch_add(mm, vaddr, ptep, orig, fullmm, hugepage_shift); 893 } 894 895 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 896 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 897 unsigned long addr, 898 pmd_t *pmdp) 899 { 900 pmd_t pmd = *pmdp; 901 set_pmd_at(mm, addr, pmdp, __pmd(0UL)); 902 return pmd; 903 } 904 905 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 906 pte_t *ptep, pte_t pte, int fullmm) 907 { 908 pte_t orig = *ptep; 909 910 *ptep = pte; 911 maybe_tlb_batch_add(mm, addr, ptep, orig, fullmm, PAGE_SHIFT); 912 } 913 914 #define set_pte_at(mm,addr,ptep,pte) \ 915 __set_pte_at((mm), (addr), (ptep), (pte), 0) 916 917 #define pte_clear(mm,addr,ptep) \ 918 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 919 920 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 921 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 922 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 923 924 #ifdef DCACHE_ALIASING_POSSIBLE 925 #define __HAVE_ARCH_MOVE_PTE 926 #define move_pte(pte, prot, old_addr, new_addr) \ 927 ({ \ 928 pte_t newpte = (pte); \ 929 if (tlb_type != hypervisor && pte_present(pte)) { \ 930 unsigned long this_pfn = pte_pfn(pte); \ 931 \ 932 if (pfn_valid(this_pfn) && \ 933 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 934 flush_dcache_page_all(current->mm, \ 935 pfn_to_page(this_pfn)); \ 936 } \ 937 newpte; \ 938 }) 939 #endif 940 941 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 942 943 void paging_init(void); 944 unsigned long find_ecache_flush_span(unsigned long size); 945 946 struct seq_file; 947 void mmu_info(struct seq_file *); 948 949 struct vm_area_struct; 950 void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 951 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 952 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 953 pmd_t *pmd); 954 955 #define __HAVE_ARCH_PMDP_INVALIDATE 956 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 957 pmd_t *pmdp); 958 959 #define __HAVE_ARCH_PGTABLE_DEPOSIT 960 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 961 pgtable_t pgtable); 962 963 #define __HAVE_ARCH_PGTABLE_WITHDRAW 964 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 965 #endif 966 967 /* 968 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 969 * are !pte_none() && !pte_present(). 970 * 971 * Format of swap PTEs: 972 * 973 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 974 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 975 * <--------------------------- offset --------------------------- 976 * 977 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 978 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 979 * --------------------> E <-- type ---> <------- zeroes --------> 980 */ 981 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0x7fUL) 982 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 983 #define __swp_entry(type, offset) \ 984 ( (swp_entry_t) \ 985 { \ 986 ((((long)(type) & 0x7fUL) << PAGE_SHIFT) | \ 987 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 988 } ) 989 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 990 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 991 992 static inline int pte_swp_exclusive(pte_t pte) 993 { 994 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 995 } 996 997 static inline pte_t pte_swp_mkexclusive(pte_t pte) 998 { 999 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 1000 } 1001 1002 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1003 { 1004 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 1005 } 1006 1007 int page_in_phys_avail(unsigned long paddr); 1008 1009 /* 1010 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 1011 * its high 4 bits. These macros/functions put it there or get it from there. 1012 */ 1013 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 1014 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 1015 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 1016 1017 int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, 1018 unsigned long, pgprot_t); 1019 1020 void adi_restore_tags(struct mm_struct *mm, struct vm_area_struct *vma, 1021 unsigned long addr, pte_t pte); 1022 1023 int adi_save_tags(struct mm_struct *mm, struct vm_area_struct *vma, 1024 unsigned long addr, pte_t oldpte); 1025 1026 #define __HAVE_ARCH_DO_SWAP_PAGE 1027 static inline void arch_do_swap_page(struct mm_struct *mm, 1028 struct vm_area_struct *vma, 1029 unsigned long addr, 1030 pte_t pte, pte_t oldpte) 1031 { 1032 /* If this is a new page being mapped in, there can be no 1033 * ADI tags stored away for this page. Skip looking for 1034 * stored tags 1035 */ 1036 if (pte_none(oldpte)) 1037 return; 1038 1039 if (adi_state.enabled && (pte_val(pte) & _PAGE_MCD_4V)) 1040 adi_restore_tags(mm, vma, addr, pte); 1041 } 1042 1043 #define __HAVE_ARCH_UNMAP_ONE 1044 static inline int arch_unmap_one(struct mm_struct *mm, 1045 struct vm_area_struct *vma, 1046 unsigned long addr, pte_t oldpte) 1047 { 1048 if (adi_state.enabled && (pte_val(oldpte) & _PAGE_MCD_4V)) 1049 return adi_save_tags(mm, vma, addr, oldpte); 1050 return 0; 1051 } 1052 1053 static inline int io_remap_pfn_range(struct vm_area_struct *vma, 1054 unsigned long from, unsigned long pfn, 1055 unsigned long size, pgprot_t prot) 1056 { 1057 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 1058 int space = GET_IOSPACE(pfn); 1059 unsigned long phys_base; 1060 1061 phys_base = offset | (((unsigned long) space) << 32UL); 1062 1063 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); 1064 } 1065 #define io_remap_pfn_range io_remap_pfn_range 1066 1067 static inline unsigned long __untagged_addr(unsigned long start) 1068 { 1069 if (adi_capable()) { 1070 long addr = start; 1071 1072 /* If userspace has passed a versioned address, kernel 1073 * will not find it in the VMAs since it does not store 1074 * the version tags in the list of VMAs. Storing version 1075 * tags in list of VMAs is impractical since they can be 1076 * changed any time from userspace without dropping into 1077 * kernel. Any address search in VMAs will be done with 1078 * non-versioned addresses. Ensure the ADI version bits 1079 * are dropped here by sign extending the last bit before 1080 * ADI bits. IOMMU does not implement version tags. 1081 */ 1082 return (addr << (long)adi_nbits()) >> (long)adi_nbits(); 1083 } 1084 1085 return start; 1086 } 1087 #define untagged_addr(addr) \ 1088 ((__typeof__(addr))(__untagged_addr((unsigned long)(addr)))) 1089 1090 static inline bool pte_access_permitted(pte_t pte, bool write) 1091 { 1092 u64 prot; 1093 1094 if (tlb_type == hypervisor) { 1095 prot = _PAGE_PRESENT_4V | _PAGE_P_4V; 1096 if (write) 1097 prot |= _PAGE_WRITE_4V; 1098 } else { 1099 prot = _PAGE_PRESENT_4U | _PAGE_P_4U; 1100 if (write) 1101 prot |= _PAGE_WRITE_4U; 1102 } 1103 1104 return (pte_val(pte) & (prot | _PAGE_SPECIAL)) == prot; 1105 } 1106 #define pte_access_permitted pte_access_permitted 1107 1108 #include <asm/tlbflush.h> 1109 1110 /* We provide our own get_unmapped_area to cope with VA holes and 1111 * SHM area cache aliasing for userland. 1112 */ 1113 #define HAVE_ARCH_UNMAPPED_AREA 1114 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1115 1116 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 1117 * the largest alignment possible such that larget PTEs can be used. 1118 */ 1119 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 1120 unsigned long, unsigned long, 1121 unsigned long); 1122 #define HAVE_ARCH_FB_UNMAPPED_AREA 1123 1124 void sun4v_register_fault_status(void); 1125 void sun4v_ktsb_register(void); 1126 void __init cheetah_ecache_flush_init(void); 1127 void sun4v_patch_tlb_handlers(void); 1128 1129 extern unsigned long cmdline_memory_size; 1130 1131 asmlinkage void do_sparc64_fault(struct pt_regs *regs); 1132 1133 #define pmd_pgtable(PMD) ((pte_t *)pmd_page_vaddr(PMD)) 1134 1135 #ifdef CONFIG_HUGETLB_PAGE 1136 1137 #define pud_leaf_size pud_leaf_size 1138 extern unsigned long pud_leaf_size(pud_t pud); 1139 1140 #define pmd_leaf_size pmd_leaf_size 1141 extern unsigned long pmd_leaf_size(pmd_t pmd); 1142 1143 #define pte_leaf_size pte_leaf_size 1144 extern unsigned long pte_leaf_size(pte_t pte); 1145 1146 #endif /* CONFIG_HUGETLB_PAGE */ 1147 1148 #endif /* !(__ASSEMBLY__) */ 1149 1150 #endif /* !(_SPARC64_PGTABLE_H) */ 1151