1 /* 2 * pgtable.h: SpitFire page table operations. 3 * 4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #ifndef _SPARC64_PGTABLE_H 9 #define _SPARC64_PGTABLE_H 10 11 /* This file contains the functions and defines necessary to modify and use 12 * the SpitFire page tables. 13 */ 14 15 #include <linux/compiler.h> 16 #include <linux/const.h> 17 #include <asm/types.h> 18 #include <asm/spitfire.h> 19 #include <asm/asi.h> 20 #include <asm/page.h> 21 #include <asm/processor.h> 22 23 #include <asm-generic/pgtable-nopud.h> 24 25 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 26 * The page copy blockops can use 0x6000000 to 0x8000000. 27 * The TSB is mapped in the 0x8000000 to 0xa000000 range. 28 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 29 * The vmalloc area spans 0x100000000 to 0x200000000. 30 * Since modules need to be in the lowest 32-bits of the address space, 31 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 32 * There is a single static kernel PMD which maps from 0x0 to address 33 * 0x400000000. 34 */ 35 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 36 #define TSBMAP_BASE _AC(0x0000000008000000,UL) 37 #define MODULES_VADDR _AC(0x0000000010000000,UL) 38 #define MODULES_LEN _AC(0x00000000e0000000,UL) 39 #define MODULES_END _AC(0x00000000f0000000,UL) 40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 42 #define VMALLOC_START _AC(0x0000000100000000,UL) 43 #define VMALLOC_END _AC(0x0000010000000000,UL) 44 #define VMEMMAP_BASE _AC(0x0000010000000000,UL) 45 46 #define vmemmap ((struct page *)VMEMMAP_BASE) 47 48 /* PMD_SHIFT determines the size of the area a second-level page 49 * table can map 50 */ 51 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 53 #define PMD_MASK (~(PMD_SIZE-1)) 54 #define PMD_BITS (PAGE_SHIFT - 3) 55 56 /* PGDIR_SHIFT determines what a third-level page table entry can map */ 57 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS) 58 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 59 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 60 #define PGDIR_BITS (PAGE_SHIFT - 3) 61 62 #if (PGDIR_SHIFT + PGDIR_BITS) != 43 63 #error Page table parameters do not cover virtual address space properly. 64 #endif 65 66 #if (PMD_SHIFT != HPAGE_SHIFT) 67 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. 68 #endif 69 70 #ifndef __ASSEMBLY__ 71 72 #include <linux/sched.h> 73 74 extern unsigned long sparc64_valid_addr_bitmap[]; 75 76 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 77 static inline bool __kern_addr_valid(unsigned long paddr) 78 { 79 if ((paddr >> MAX_PHYS_ADDRESS_BITS) != 0UL) 80 return false; 81 return test_bit(paddr >> ILOG2_4MB, sparc64_valid_addr_bitmap); 82 } 83 84 static inline bool kern_addr_valid(unsigned long addr) 85 { 86 unsigned long paddr = __pa(addr); 87 88 return __kern_addr_valid(paddr); 89 } 90 91 /* Entries per page directory level. */ 92 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 93 #define PTRS_PER_PMD (1UL << PMD_BITS) 94 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 95 96 /* Kernel has a separate 44bit address space. */ 97 #define FIRST_USER_ADDRESS 0 98 99 #define pmd_ERROR(e) \ 100 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ 101 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) 102 #define pgd_ERROR(e) \ 103 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ 104 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) 105 106 #endif /* !(__ASSEMBLY__) */ 107 108 /* PTE bits which are the same in SUN4U and SUN4V format. */ 109 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 110 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 111 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 112 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ 113 114 /* Advertise support for _PAGE_SPECIAL */ 115 #define __HAVE_ARCH_PTE_SPECIAL 116 117 /* SUN4U pte bits... */ 118 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 119 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 120 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 121 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 122 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 123 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 124 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 125 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 126 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ 127 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 128 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 129 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 130 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 131 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 132 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 133 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 134 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 135 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 136 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 137 #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */ 138 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 139 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 140 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 141 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 142 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 143 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 144 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 145 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 146 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 147 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 148 149 /* SUN4V pte bits... */ 150 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 151 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 152 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 153 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 154 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 155 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 156 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 157 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ 158 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 159 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 160 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 161 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 162 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 163 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 164 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 165 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 166 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 167 #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */ 168 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 169 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 170 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 171 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 172 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 173 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 174 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 175 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 176 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 177 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 178 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 179 180 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 181 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 182 183 #if REAL_HPAGE_SHIFT != 22 184 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up 185 #endif 186 187 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 188 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 189 190 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 191 #define __P000 __pgprot(0) 192 #define __P001 __pgprot(0) 193 #define __P010 __pgprot(0) 194 #define __P011 __pgprot(0) 195 #define __P100 __pgprot(0) 196 #define __P101 __pgprot(0) 197 #define __P110 __pgprot(0) 198 #define __P111 __pgprot(0) 199 200 #define __S000 __pgprot(0) 201 #define __S001 __pgprot(0) 202 #define __S010 __pgprot(0) 203 #define __S011 __pgprot(0) 204 #define __S100 __pgprot(0) 205 #define __S101 __pgprot(0) 206 #define __S110 __pgprot(0) 207 #define __S111 __pgprot(0) 208 209 #ifndef __ASSEMBLY__ 210 211 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 212 213 extern unsigned long pte_sz_bits(unsigned long size); 214 215 extern pgprot_t PAGE_KERNEL; 216 extern pgprot_t PAGE_KERNEL_LOCKED; 217 extern pgprot_t PAGE_COPY; 218 extern pgprot_t PAGE_SHARED; 219 220 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */ 221 extern unsigned long _PAGE_IE; 222 extern unsigned long _PAGE_E; 223 extern unsigned long _PAGE_CACHE; 224 225 extern unsigned long pg_iobits; 226 extern unsigned long _PAGE_ALL_SZ_BITS; 227 228 extern struct page *mem_map_zero; 229 #define ZERO_PAGE(vaddr) (mem_map_zero) 230 231 /* PFNs are real physical page numbers. However, mem_map only begins to record 232 * per-page information starting at pfn_base. This is to handle systems where 233 * the first physical page in the machine is at some huge physical address, 234 * such as 4GB. This is common on a partitioned E10000, for example. 235 */ 236 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 237 { 238 unsigned long paddr = pfn << PAGE_SHIFT; 239 240 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 241 return __pte(paddr | pgprot_val(prot)); 242 } 243 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 244 245 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 246 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 247 { 248 pte_t pte = pfn_pte(page_nr, pgprot); 249 250 return __pmd(pte_val(pte)); 251 } 252 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 253 #endif 254 255 /* This one can be done with two shifts. */ 256 static inline unsigned long pte_pfn(pte_t pte) 257 { 258 unsigned long ret; 259 260 __asm__ __volatile__( 261 "\n661: sllx %1, %2, %0\n" 262 " srlx %0, %3, %0\n" 263 " .section .sun4v_2insn_patch, \"ax\"\n" 264 " .word 661b\n" 265 " sllx %1, %4, %0\n" 266 " srlx %0, %5, %0\n" 267 " .previous\n" 268 : "=r" (ret) 269 : "r" (pte_val(pte)), 270 "i" (21), "i" (21 + PAGE_SHIFT), 271 "i" (8), "i" (8 + PAGE_SHIFT)); 272 273 return ret; 274 } 275 #define pte_page(x) pfn_to_page(pte_pfn(x)) 276 277 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 278 { 279 unsigned long mask, tmp; 280 281 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) 282 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) 283 * 284 * Even if we use negation tricks the result is still a 6 285 * instruction sequence, so don't try to play fancy and just 286 * do the most straightforward implementation. 287 * 288 * Note: We encode this into 3 sun4v 2-insn patch sequences. 289 */ 290 291 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 292 __asm__ __volatile__( 293 "\n661: sethi %%uhi(%2), %1\n" 294 " sethi %%hi(%2), %0\n" 295 "\n662: or %1, %%ulo(%2), %1\n" 296 " or %0, %%lo(%2), %0\n" 297 "\n663: sllx %1, 32, %1\n" 298 " or %0, %1, %0\n" 299 " .section .sun4v_2insn_patch, \"ax\"\n" 300 " .word 661b\n" 301 " sethi %%uhi(%3), %1\n" 302 " sethi %%hi(%3), %0\n" 303 " .word 662b\n" 304 " or %1, %%ulo(%3), %1\n" 305 " or %0, %%lo(%3), %0\n" 306 " .word 663b\n" 307 " sllx %1, 32, %1\n" 308 " or %0, %1, %0\n" 309 " .previous\n" 310 : "=r" (mask), "=r" (tmp) 311 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 312 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | 313 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), 314 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 315 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | 316 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); 317 318 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 319 } 320 321 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 322 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 323 { 324 pte_t pte = __pte(pmd_val(pmd)); 325 326 pte = pte_modify(pte, newprot); 327 328 return __pmd(pte_val(pte)); 329 } 330 #endif 331 332 static inline pte_t pgoff_to_pte(unsigned long off) 333 { 334 off <<= PAGE_SHIFT; 335 336 __asm__ __volatile__( 337 "\n661: or %0, %2, %0\n" 338 " .section .sun4v_1insn_patch, \"ax\"\n" 339 " .word 661b\n" 340 " or %0, %3, %0\n" 341 " .previous\n" 342 : "=r" (off) 343 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 344 345 return __pte(off); 346 } 347 348 static inline pgprot_t pgprot_noncached(pgprot_t prot) 349 { 350 unsigned long val = pgprot_val(prot); 351 352 __asm__ __volatile__( 353 "\n661: andn %0, %2, %0\n" 354 " or %0, %3, %0\n" 355 " .section .sun4v_2insn_patch, \"ax\"\n" 356 " .word 661b\n" 357 " andn %0, %4, %0\n" 358 " or %0, %5, %0\n" 359 " .previous\n" 360 : "=r" (val) 361 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 362 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V)); 363 364 return __pgprot(val); 365 } 366 /* Various pieces of code check for platform support by ifdef testing 367 * on "pgprot_noncached". That's broken and should be fixed, but for 368 * now... 369 */ 370 #define pgprot_noncached pgprot_noncached 371 372 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 373 static inline pte_t pte_mkhuge(pte_t pte) 374 { 375 unsigned long mask; 376 377 __asm__ __volatile__( 378 "\n661: sethi %%uhi(%1), %0\n" 379 " sllx %0, 32, %0\n" 380 " .section .sun4v_2insn_patch, \"ax\"\n" 381 " .word 661b\n" 382 " mov %2, %0\n" 383 " nop\n" 384 " .previous\n" 385 : "=r" (mask) 386 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 387 388 return __pte(pte_val(pte) | mask); 389 } 390 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 391 static inline pmd_t pmd_mkhuge(pmd_t pmd) 392 { 393 pte_t pte = __pte(pmd_val(pmd)); 394 395 pte = pte_mkhuge(pte); 396 pte_val(pte) |= _PAGE_PMD_HUGE; 397 398 return __pmd(pte_val(pte)); 399 } 400 #endif 401 #endif 402 403 static inline pte_t pte_mkdirty(pte_t pte) 404 { 405 unsigned long val = pte_val(pte), tmp; 406 407 __asm__ __volatile__( 408 "\n661: or %0, %3, %0\n" 409 " nop\n" 410 "\n662: nop\n" 411 " nop\n" 412 " .section .sun4v_2insn_patch, \"ax\"\n" 413 " .word 661b\n" 414 " sethi %%uhi(%4), %1\n" 415 " sllx %1, 32, %1\n" 416 " .word 662b\n" 417 " or %1, %%lo(%4), %1\n" 418 " or %0, %1, %0\n" 419 " .previous\n" 420 : "=r" (val), "=r" (tmp) 421 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 422 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 423 424 return __pte(val); 425 } 426 427 static inline pte_t pte_mkclean(pte_t pte) 428 { 429 unsigned long val = pte_val(pte), tmp; 430 431 __asm__ __volatile__( 432 "\n661: andn %0, %3, %0\n" 433 " nop\n" 434 "\n662: nop\n" 435 " nop\n" 436 " .section .sun4v_2insn_patch, \"ax\"\n" 437 " .word 661b\n" 438 " sethi %%uhi(%4), %1\n" 439 " sllx %1, 32, %1\n" 440 " .word 662b\n" 441 " or %1, %%lo(%4), %1\n" 442 " andn %0, %1, %0\n" 443 " .previous\n" 444 : "=r" (val), "=r" (tmp) 445 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 446 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 447 448 return __pte(val); 449 } 450 451 static inline pte_t pte_mkwrite(pte_t pte) 452 { 453 unsigned long val = pte_val(pte), mask; 454 455 __asm__ __volatile__( 456 "\n661: mov %1, %0\n" 457 " nop\n" 458 " .section .sun4v_2insn_patch, \"ax\"\n" 459 " .word 661b\n" 460 " sethi %%uhi(%2), %0\n" 461 " sllx %0, 32, %0\n" 462 " .previous\n" 463 : "=r" (mask) 464 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 465 466 return __pte(val | mask); 467 } 468 469 static inline pte_t pte_wrprotect(pte_t pte) 470 { 471 unsigned long val = pte_val(pte), tmp; 472 473 __asm__ __volatile__( 474 "\n661: andn %0, %3, %0\n" 475 " nop\n" 476 "\n662: nop\n" 477 " nop\n" 478 " .section .sun4v_2insn_patch, \"ax\"\n" 479 " .word 661b\n" 480 " sethi %%uhi(%4), %1\n" 481 " sllx %1, 32, %1\n" 482 " .word 662b\n" 483 " or %1, %%lo(%4), %1\n" 484 " andn %0, %1, %0\n" 485 " .previous\n" 486 : "=r" (val), "=r" (tmp) 487 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 488 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 489 490 return __pte(val); 491 } 492 493 static inline pte_t pte_mkold(pte_t pte) 494 { 495 unsigned long mask; 496 497 __asm__ __volatile__( 498 "\n661: mov %1, %0\n" 499 " nop\n" 500 " .section .sun4v_2insn_patch, \"ax\"\n" 501 " .word 661b\n" 502 " sethi %%uhi(%2), %0\n" 503 " sllx %0, 32, %0\n" 504 " .previous\n" 505 : "=r" (mask) 506 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 507 508 mask |= _PAGE_R; 509 510 return __pte(pte_val(pte) & ~mask); 511 } 512 513 static inline pte_t pte_mkyoung(pte_t pte) 514 { 515 unsigned long mask; 516 517 __asm__ __volatile__( 518 "\n661: mov %1, %0\n" 519 " nop\n" 520 " .section .sun4v_2insn_patch, \"ax\"\n" 521 " .word 661b\n" 522 " sethi %%uhi(%2), %0\n" 523 " sllx %0, 32, %0\n" 524 " .previous\n" 525 : "=r" (mask) 526 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 527 528 mask |= _PAGE_R; 529 530 return __pte(pte_val(pte) | mask); 531 } 532 533 static inline pte_t pte_mkspecial(pte_t pte) 534 { 535 pte_val(pte) |= _PAGE_SPECIAL; 536 return pte; 537 } 538 539 static inline unsigned long pte_young(pte_t pte) 540 { 541 unsigned long mask; 542 543 __asm__ __volatile__( 544 "\n661: mov %1, %0\n" 545 " nop\n" 546 " .section .sun4v_2insn_patch, \"ax\"\n" 547 " .word 661b\n" 548 " sethi %%uhi(%2), %0\n" 549 " sllx %0, 32, %0\n" 550 " .previous\n" 551 : "=r" (mask) 552 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 553 554 return (pte_val(pte) & mask); 555 } 556 557 static inline unsigned long pte_dirty(pte_t pte) 558 { 559 unsigned long mask; 560 561 __asm__ __volatile__( 562 "\n661: mov %1, %0\n" 563 " nop\n" 564 " .section .sun4v_2insn_patch, \"ax\"\n" 565 " .word 661b\n" 566 " sethi %%uhi(%2), %0\n" 567 " sllx %0, 32, %0\n" 568 " .previous\n" 569 : "=r" (mask) 570 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 571 572 return (pte_val(pte) & mask); 573 } 574 575 static inline unsigned long pte_write(pte_t pte) 576 { 577 unsigned long mask; 578 579 __asm__ __volatile__( 580 "\n661: mov %1, %0\n" 581 " nop\n" 582 " .section .sun4v_2insn_patch, \"ax\"\n" 583 " .word 661b\n" 584 " sethi %%uhi(%2), %0\n" 585 " sllx %0, 32, %0\n" 586 " .previous\n" 587 : "=r" (mask) 588 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 589 590 return (pte_val(pte) & mask); 591 } 592 593 static inline unsigned long pte_exec(pte_t pte) 594 { 595 unsigned long mask; 596 597 __asm__ __volatile__( 598 "\n661: sethi %%hi(%1), %0\n" 599 " .section .sun4v_1insn_patch, \"ax\"\n" 600 " .word 661b\n" 601 " mov %2, %0\n" 602 " .previous\n" 603 : "=r" (mask) 604 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 605 606 return (pte_val(pte) & mask); 607 } 608 609 static inline unsigned long pte_file(pte_t pte) 610 { 611 unsigned long val = pte_val(pte); 612 613 __asm__ __volatile__( 614 "\n661: and %0, %2, %0\n" 615 " .section .sun4v_1insn_patch, \"ax\"\n" 616 " .word 661b\n" 617 " and %0, %3, %0\n" 618 " .previous\n" 619 : "=r" (val) 620 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 621 622 return val; 623 } 624 625 static inline unsigned long pte_present(pte_t pte) 626 { 627 unsigned long val = pte_val(pte); 628 629 __asm__ __volatile__( 630 "\n661: and %0, %2, %0\n" 631 " .section .sun4v_1insn_patch, \"ax\"\n" 632 " .word 661b\n" 633 " and %0, %3, %0\n" 634 " .previous\n" 635 : "=r" (val) 636 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 637 638 return val; 639 } 640 641 #define pte_accessible pte_accessible 642 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 643 { 644 return pte_val(a) & _PAGE_VALID; 645 } 646 647 static inline unsigned long pte_special(pte_t pte) 648 { 649 return pte_val(pte) & _PAGE_SPECIAL; 650 } 651 652 static inline unsigned long pmd_large(pmd_t pmd) 653 { 654 pte_t pte = __pte(pmd_val(pmd)); 655 656 return pte_val(pte) & _PAGE_PMD_HUGE; 657 } 658 659 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 660 static inline unsigned long pmd_young(pmd_t pmd) 661 { 662 pte_t pte = __pte(pmd_val(pmd)); 663 664 return pte_young(pte); 665 } 666 667 static inline unsigned long pmd_write(pmd_t pmd) 668 { 669 pte_t pte = __pte(pmd_val(pmd)); 670 671 return pte_write(pte); 672 } 673 674 static inline unsigned long pmd_pfn(pmd_t pmd) 675 { 676 pte_t pte = __pte(pmd_val(pmd)); 677 678 return pte_pfn(pte); 679 } 680 681 static inline unsigned long pmd_trans_huge(pmd_t pmd) 682 { 683 pte_t pte = __pte(pmd_val(pmd)); 684 685 return pte_val(pte) & _PAGE_PMD_HUGE; 686 } 687 688 static inline unsigned long pmd_trans_splitting(pmd_t pmd) 689 { 690 pte_t pte = __pte(pmd_val(pmd)); 691 692 return pmd_trans_huge(pmd) && pte_special(pte); 693 } 694 695 #define has_transparent_hugepage() 1 696 697 static inline pmd_t pmd_mkold(pmd_t pmd) 698 { 699 pte_t pte = __pte(pmd_val(pmd)); 700 701 pte = pte_mkold(pte); 702 703 return __pmd(pte_val(pte)); 704 } 705 706 static inline pmd_t pmd_wrprotect(pmd_t pmd) 707 { 708 pte_t pte = __pte(pmd_val(pmd)); 709 710 pte = pte_wrprotect(pte); 711 712 return __pmd(pte_val(pte)); 713 } 714 715 static inline pmd_t pmd_mkdirty(pmd_t pmd) 716 { 717 pte_t pte = __pte(pmd_val(pmd)); 718 719 pte = pte_mkdirty(pte); 720 721 return __pmd(pte_val(pte)); 722 } 723 724 static inline pmd_t pmd_mkyoung(pmd_t pmd) 725 { 726 pte_t pte = __pte(pmd_val(pmd)); 727 728 pte = pte_mkyoung(pte); 729 730 return __pmd(pte_val(pte)); 731 } 732 733 static inline pmd_t pmd_mkwrite(pmd_t pmd) 734 { 735 pte_t pte = __pte(pmd_val(pmd)); 736 737 pte = pte_mkwrite(pte); 738 739 return __pmd(pte_val(pte)); 740 } 741 742 static inline pmd_t pmd_mksplitting(pmd_t pmd) 743 { 744 pte_t pte = __pte(pmd_val(pmd)); 745 746 pte = pte_mkspecial(pte); 747 748 return __pmd(pte_val(pte)); 749 } 750 751 static inline pgprot_t pmd_pgprot(pmd_t entry) 752 { 753 unsigned long val = pmd_val(entry); 754 755 return __pgprot(val); 756 } 757 #endif 758 759 static inline int pmd_present(pmd_t pmd) 760 { 761 return pmd_val(pmd) != 0UL; 762 } 763 764 #define pmd_none(pmd) (!pmd_val(pmd)) 765 766 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is 767 * very simple, it's just the physical address. PTE tables are of 768 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and 769 * the top bits outside of the range of any physical address size we 770 * support are clear as well. We also validate the physical itself. 771 */ 772 #define pmd_bad(pmd) ((pmd_val(pmd) & ~PAGE_MASK) || \ 773 !__kern_addr_valid(pmd_val(pmd))) 774 775 #define pud_none(pud) (!pud_val(pud)) 776 777 #define pud_bad(pud) ((pud_val(pud) & ~PAGE_MASK) || \ 778 !__kern_addr_valid(pud_val(pud))) 779 780 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 781 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 782 pmd_t *pmdp, pmd_t pmd); 783 #else 784 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 785 pmd_t *pmdp, pmd_t pmd) 786 { 787 *pmdp = pmd; 788 } 789 #endif 790 791 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 792 { 793 unsigned long val = __pa((unsigned long) (ptep)); 794 795 pmd_val(*pmdp) = val; 796 } 797 798 #define pud_set(pudp, pmdp) \ 799 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) 800 static inline unsigned long __pmd_page(pmd_t pmd) 801 { 802 pte_t pte = __pte(pmd_val(pmd)); 803 unsigned long pfn; 804 805 pfn = pte_pfn(pte); 806 807 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 808 } 809 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 810 #define pud_page_vaddr(pud) \ 811 ((unsigned long) __va(pud_val(pud))) 812 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 813 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 814 #define pud_present(pud) (pud_val(pud) != 0U) 815 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 816 817 /* Same in both SUN4V and SUN4U. */ 818 #define pte_none(pte) (!pte_val(pte)) 819 820 /* to find an entry in a page-table-directory. */ 821 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 822 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 823 824 /* to find an entry in a kernel page-table-directory */ 825 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 826 827 /* Find an entry in the second-level page table.. */ 828 #define pmd_offset(pudp, address) \ 829 ((pmd_t *) pud_page_vaddr(*(pudp)) + \ 830 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) 831 832 /* Find an entry in the third-level page table.. */ 833 #define pte_index(dir, address) \ 834 ((pte_t *) __pmd_page(*(dir)) + \ 835 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 836 #define pte_offset_kernel pte_index 837 #define pte_offset_map pte_index 838 #define pte_unmap(pte) do { } while (0) 839 840 /* Actual page table PTE updates. */ 841 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 842 pte_t *ptep, pte_t orig, int fullmm); 843 844 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 845 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 846 unsigned long addr, 847 pmd_t *pmdp) 848 { 849 pmd_t pmd = *pmdp; 850 set_pmd_at(mm, addr, pmdp, __pmd(0UL)); 851 return pmd; 852 } 853 854 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 855 pte_t *ptep, pte_t pte, int fullmm) 856 { 857 pte_t orig = *ptep; 858 859 *ptep = pte; 860 861 /* It is more efficient to let flush_tlb_kernel_range() 862 * handle init_mm tlb flushes. 863 * 864 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 865 * and SUN4V pte layout, so this inline test is fine. 866 */ 867 if (likely(mm != &init_mm) && pte_accessible(mm, orig)) 868 tlb_batch_add(mm, addr, ptep, orig, fullmm); 869 } 870 871 #define set_pte_at(mm,addr,ptep,pte) \ 872 __set_pte_at((mm), (addr), (ptep), (pte), 0) 873 874 #define pte_clear(mm,addr,ptep) \ 875 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 876 877 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 878 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 879 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 880 881 #ifdef DCACHE_ALIASING_POSSIBLE 882 #define __HAVE_ARCH_MOVE_PTE 883 #define move_pte(pte, prot, old_addr, new_addr) \ 884 ({ \ 885 pte_t newpte = (pte); \ 886 if (tlb_type != hypervisor && pte_present(pte)) { \ 887 unsigned long this_pfn = pte_pfn(pte); \ 888 \ 889 if (pfn_valid(this_pfn) && \ 890 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 891 flush_dcache_page_all(current->mm, \ 892 pfn_to_page(this_pfn)); \ 893 } \ 894 newpte; \ 895 }) 896 #endif 897 898 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 899 extern pmd_t swapper_low_pmd_dir[PTRS_PER_PMD]; 900 901 extern void paging_init(void); 902 extern unsigned long find_ecache_flush_span(unsigned long size); 903 904 struct seq_file; 905 extern void mmu_info(struct seq_file *); 906 907 struct vm_area_struct; 908 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 909 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 910 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 911 pmd_t *pmd); 912 913 #define __HAVE_ARCH_PMDP_INVALIDATE 914 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 915 pmd_t *pmdp); 916 917 #define __HAVE_ARCH_PGTABLE_DEPOSIT 918 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 919 pgtable_t pgtable); 920 921 #define __HAVE_ARCH_PGTABLE_WITHDRAW 922 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 923 #endif 924 925 /* Encode and de-code a swap entry */ 926 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) 927 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 928 #define __swp_entry(type, offset) \ 929 ( (swp_entry_t) \ 930 { \ 931 (((long)(type) << PAGE_SHIFT) | \ 932 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 933 } ) 934 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 935 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 936 937 /* File offset in PTE support. */ 938 extern unsigned long pte_file(pte_t); 939 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT) 940 extern pte_t pgoff_to_pte(unsigned long); 941 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL) 942 943 extern int page_in_phys_avail(unsigned long paddr); 944 945 /* 946 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 947 * its high 4 bits. These macros/functions put it there or get it from there. 948 */ 949 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 950 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 951 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 952 953 extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, 954 unsigned long, pgprot_t); 955 956 static inline int io_remap_pfn_range(struct vm_area_struct *vma, 957 unsigned long from, unsigned long pfn, 958 unsigned long size, pgprot_t prot) 959 { 960 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 961 int space = GET_IOSPACE(pfn); 962 unsigned long phys_base; 963 964 phys_base = offset | (((unsigned long) space) << 32UL); 965 966 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); 967 } 968 #define io_remap_pfn_range io_remap_pfn_range 969 970 #include <asm/tlbflush.h> 971 #include <asm-generic/pgtable.h> 972 973 /* We provide our own get_unmapped_area to cope with VA holes and 974 * SHM area cache aliasing for userland. 975 */ 976 #define HAVE_ARCH_UNMAPPED_AREA 977 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 978 979 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 980 * the largest alignment possible such that larget PTEs can be used. 981 */ 982 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 983 unsigned long, unsigned long, 984 unsigned long); 985 #define HAVE_ARCH_FB_UNMAPPED_AREA 986 987 extern void pgtable_cache_init(void); 988 extern void sun4v_register_fault_status(void); 989 extern void sun4v_ktsb_register(void); 990 extern void __init cheetah_ecache_flush_init(void); 991 extern void sun4v_patch_tlb_handlers(void); 992 993 extern unsigned long cmdline_memory_size; 994 995 extern asmlinkage void do_sparc64_fault(struct pt_regs *regs); 996 997 #endif /* !(__ASSEMBLY__) */ 998 999 #endif /* !(_SPARC64_PGTABLE_H) */ 1000