1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg /* 3a439fe51SSam Ravnborg * pcic.h: JavaEngine 1 specific PCI definitions. 4a439fe51SSam Ravnborg * 5a439fe51SSam Ravnborg * Copyright (C) 1998 V. Roganov and G. Raiko 6a439fe51SSam Ravnborg */ 7a439fe51SSam Ravnborg 8a439fe51SSam Ravnborg #ifndef __SPARC_PCIC_H 9a439fe51SSam Ravnborg #define __SPARC_PCIC_H 10a439fe51SSam Ravnborg 11a439fe51SSam Ravnborg #ifndef __ASSEMBLY__ 12a439fe51SSam Ravnborg 13a439fe51SSam Ravnborg #include <linux/types.h> 14a439fe51SSam Ravnborg #include <linux/smp.h> 15a439fe51SSam Ravnborg #include <linux/pci.h> 16a439fe51SSam Ravnborg #include <linux/ioport.h> 17a439fe51SSam Ravnborg #include <asm/pbm.h> 18a439fe51SSam Ravnborg 19a439fe51SSam Ravnborg struct linux_pcic { 20a439fe51SSam Ravnborg void __iomem *pcic_regs; 21a439fe51SSam Ravnborg unsigned long pcic_io; 22a439fe51SSam Ravnborg void __iomem *pcic_config_space_addr; 23a439fe51SSam Ravnborg void __iomem *pcic_config_space_data; 24a439fe51SSam Ravnborg struct resource pcic_res_regs; 25a439fe51SSam Ravnborg struct resource pcic_res_io; 26a439fe51SSam Ravnborg struct resource pcic_res_cfg_addr; 27a439fe51SSam Ravnborg struct resource pcic_res_cfg_data; 28a439fe51SSam Ravnborg struct linux_pbm_info pbm; 29a439fe51SSam Ravnborg struct pcic_ca2irq *pcic_imap; 30a439fe51SSam Ravnborg int pcic_imdim; 31a439fe51SSam Ravnborg }; 32a439fe51SSam Ravnborg 33cfe3af5dSDaniel Hellstrom #ifdef CONFIG_PCIC_PCI 34f05a6865SSam Ravnborg int pcic_present(void); 35f05a6865SSam Ravnborg int pcic_probe(void); 36f05a6865SSam Ravnborg void pci_time_init(void); 37f05a6865SSam Ravnborg void sun4m_pci_init_IRQ(void); 3806010fb5SSam Ravnborg #else pcic_present(void)3906010fb5SSam Ravnborgstatic inline int pcic_present(void) { return 0; } pcic_probe(void)4006010fb5SSam Ravnborgstatic inline int pcic_probe(void) { return 0; } pci_time_init(void)4106010fb5SSam Ravnborgstatic inline void pci_time_init(void) {} sun4m_pci_init_IRQ(void)4206010fb5SSam Ravnborgstatic inline void sun4m_pci_init_IRQ(void) {} 4306010fb5SSam Ravnborg #endif 44a439fe51SSam Ravnborg #endif 45a439fe51SSam Ravnborg 46a439fe51SSam Ravnborg /* Size of PCI I/O space which we relocate. */ 47a439fe51SSam Ravnborg #define PCI_SPACE_SIZE 0x1000000 /* 16 MB */ 48a439fe51SSam Ravnborg 49a439fe51SSam Ravnborg /* PCIC Register Set. */ 50a439fe51SSam Ravnborg #define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */ 51a439fe51SSam Ravnborg #define PCI_SIZE_0 0x44 /* 32 bits */ 52a439fe51SSam Ravnborg #define PCI_SIZE_1 0x48 /* 32 bits */ 53a439fe51SSam Ravnborg #define PCI_SIZE_2 0x4c /* 32 bits */ 54a439fe51SSam Ravnborg #define PCI_SIZE_3 0x50 /* 32 bits */ 55a439fe51SSam Ravnborg #define PCI_SIZE_4 0x54 /* 32 bits */ 56a439fe51SSam Ravnborg #define PCI_SIZE_5 0x58 /* 32 bits */ 57a439fe51SSam Ravnborg #define PCI_PIO_CONTROL 0x60 /* 8 bits */ 58a439fe51SSam Ravnborg #define PCI_DVMA_CONTROL 0x62 /* 8 bits */ 59a439fe51SSam Ravnborg #define PCI_DVMA_CONTROL_INACTIVITY_REQ (1<<0) 60a439fe51SSam Ravnborg #define PCI_DVMA_CONTROL_IOTLB_ENABLE (1<<0) 61a439fe51SSam Ravnborg #define PCI_DVMA_CONTROL_IOTLB_DISABLE 0 62a439fe51SSam Ravnborg #define PCI_DVMA_CONTROL_INACTIVITY_ACK (1<<4) 63a439fe51SSam Ravnborg #define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */ 64a439fe51SSam Ravnborg #define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */ 65a439fe51SSam Ravnborg #define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */ 66a439fe51SSam Ravnborg #define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */ 67a439fe51SSam Ravnborg #define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */ 68a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING 0x70 /* 32 bits */ 69a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING_PIO 0x40000000 70a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING_DMA 0x20000000 71a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING_PCI 0x10000000 72a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING_APSR 0x08000000 73a439fe51SSam Ravnborg #define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */ 74a439fe51SSam Ravnborg #define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */ 75a439fe51SSam Ravnborg #define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */ 76a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */ 77a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING_CLEAR_ALL 0x80 78a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING_CLEAR_PIO 0x40 79a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING_CLEAR_DMA 0x20 80a439fe51SSam Ravnborg #define PCI_SYS_INT_PENDING_CLEAR_PCI 0x10 81a439fe51SSam Ravnborg #define PCI_IOTLB_CONTROL 0x84 /* 8 bits */ 82a439fe51SSam Ravnborg #define PCI_INT_SELECT_LO 0x88 /* 16 bits */ 83a439fe51SSam Ravnborg #define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */ 84a439fe51SSam Ravnborg #define PCI_INT_SELECT_HI 0x8c /* 16 bits */ 85a439fe51SSam Ravnborg #define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */ 86a439fe51SSam Ravnborg #define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */ 87a439fe51SSam Ravnborg #define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */ 88a439fe51SSam Ravnborg #define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */ 89a439fe51SSam Ravnborg #define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */ 90a439fe51SSam Ravnborg #define PCI_SMBAR0 0xa0 /* 8 bits */ 91a439fe51SSam Ravnborg #define PCI_MSIZE0 0xa1 /* 8 bits */ 92a439fe51SSam Ravnborg #define PCI_PMBAR0 0xa2 /* 8 bits */ 93a439fe51SSam Ravnborg #define PCI_SMBAR1 0xa4 /* 8 bits */ 94a439fe51SSam Ravnborg #define PCI_MSIZE1 0xa5 /* 8 bits */ 95a439fe51SSam Ravnborg #define PCI_PMBAR1 0xa6 /* 8 bits */ 96a439fe51SSam Ravnborg #define PCI_SIBAR 0xa8 /* 8 bits */ 97a439fe51SSam Ravnborg #define PCI_SIBAR_ADDRESS_MASK 0xf 98a439fe51SSam Ravnborg #define PCI_ISIZE 0xa9 /* 8 bits */ 99a439fe51SSam Ravnborg #define PCI_ISIZE_16M 0xf 100a439fe51SSam Ravnborg #define PCI_ISIZE_32M 0xe 101a439fe51SSam Ravnborg #define PCI_ISIZE_64M 0xc 102a439fe51SSam Ravnborg #define PCI_ISIZE_128M 0x8 103a439fe51SSam Ravnborg #define PCI_ISIZE_256M 0x0 104a439fe51SSam Ravnborg #define PCI_PIBAR 0xaa /* 8 bits */ 105a439fe51SSam Ravnborg #define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */ 106a439fe51SSam Ravnborg #define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */ 107a439fe51SSam Ravnborg #define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */ 108a439fe51SSam Ravnborg #define PCI_SYS_LIMIT 0xb8 /* 32 bits */ 109a439fe51SSam Ravnborg #define PCI_SYS_COUNTER 0xbc /* 32 bits */ 110a439fe51SSam Ravnborg #define PCI_SYS_COUNTER_OVERFLOW (1<<31) /* Limit reached */ 111a439fe51SSam Ravnborg #define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */ 112a439fe51SSam Ravnborg #define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */ 113a439fe51SSam Ravnborg #define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */ 114a439fe51SSam Ravnborg #define PCI_COUNTER_IRQ 0xc6 /* 8 bits */ 115a439fe51SSam Ravnborg #define PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq) ((((sys_irq) & 0xf) << 4) | \ 116a439fe51SSam Ravnborg ((cpu_irq) & 0xf)) 117a439fe51SSam Ravnborg #define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf) 118a439fe51SSam Ravnborg #define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf) 119a439fe51SSam Ravnborg #define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */ 120a439fe51SSam Ravnborg #define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */ 121a439fe51SSam Ravnborg #define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */ 122a439fe51SSam Ravnborg #define PCI_SYS_STATUS 0xd0 /* 8 bits */ 123a439fe51SSam Ravnborg #define PCI_SYS_STATUS_RESET_ENABLE (1<<0) 124a439fe51SSam Ravnborg #define PCI_SYS_STATUS_RESET (1<<1) 125a439fe51SSam Ravnborg #define PCI_SYS_STATUS_WATCHDOG_RESET (1<<4) 126a439fe51SSam Ravnborg #define PCI_SYS_STATUS_PCI_RESET (1<<5) 127a439fe51SSam Ravnborg #define PCI_SYS_STATUS_PCI_RESET_ENABLE (1<<6) 128a439fe51SSam Ravnborg #define PCI_SYS_STATUS_PCI_SATTELITE_MODE (1<<7) 129a439fe51SSam Ravnborg 130a439fe51SSam Ravnborg #endif /* !(__SPARC_PCIC_H) */ 131