1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a439fe51SSam Ravnborg /*
3a439fe51SSam Ravnborg * mbus.h: Various defines for MBUS modules.
4a439fe51SSam Ravnborg *
5a439fe51SSam Ravnborg * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6a439fe51SSam Ravnborg */
7a439fe51SSam Ravnborg
8a439fe51SSam Ravnborg #ifndef _SPARC_MBUS_H
9a439fe51SSam Ravnborg #define _SPARC_MBUS_H
10a439fe51SSam Ravnborg
11a439fe51SSam Ravnborg #include <asm/ross.h> /* HyperSparc stuff */
12a439fe51SSam Ravnborg #include <asm/viking.h> /* Ugh, bug city... */
13a439fe51SSam Ravnborg
14a439fe51SSam Ravnborg enum mbus_module {
15a439fe51SSam Ravnborg HyperSparc = 0,
16a439fe51SSam Ravnborg Swift_ok = 4,
17a439fe51SSam Ravnborg Swift_bad_c = 5,
18a439fe51SSam Ravnborg Swift_lots_o_bugs = 6,
19a439fe51SSam Ravnborg Tsunami = 7,
20a439fe51SSam Ravnborg Viking_12 = 8,
21a439fe51SSam Ravnborg Viking_2x = 9,
22a439fe51SSam Ravnborg Viking_30 = 10,
23a439fe51SSam Ravnborg Viking_35 = 11,
24a439fe51SSam Ravnborg Viking_new = 12,
25a439fe51SSam Ravnborg TurboSparc = 13,
26a439fe51SSam Ravnborg SRMMU_INVAL_MOD = 14,
27a439fe51SSam Ravnborg };
28a439fe51SSam Ravnborg
29a439fe51SSam Ravnborg extern enum mbus_module srmmu_modtype;
30a439fe51SSam Ravnborg extern unsigned int viking_rev, swift_rev, cypress_rev;
31a439fe51SSam Ravnborg
32a439fe51SSam Ravnborg /* HW Mbus module bugs we have to deal with */
33a439fe51SSam Ravnborg #define HWBUG_COPYBACK_BROKEN 0x00000001
34a439fe51SSam Ravnborg #define HWBUG_ASIFLUSH_BROKEN 0x00000002
35a439fe51SSam Ravnborg #define HWBUG_VACFLUSH_BITROT 0x00000004
36a439fe51SSam Ravnborg #define HWBUG_KERN_ACCBROKEN 0x00000008
37a439fe51SSam Ravnborg #define HWBUG_KERN_CBITBROKEN 0x00000010
38a439fe51SSam Ravnborg #define HWBUG_MODIFIED_BITROT 0x00000020
39a439fe51SSam Ravnborg #define HWBUG_PC_BADFAULT_ADDR 0x00000040
40a439fe51SSam Ravnborg #define HWBUG_SUPERSCALAR_BAD 0x00000080
41a439fe51SSam Ravnborg #define HWBUG_PACINIT_BITROT 0x00000100
42a439fe51SSam Ravnborg
43a439fe51SSam Ravnborg /* First the module type values. To find out which you have, just load
44a439fe51SSam Ravnborg * the mmu control register from ASI_M_MMUREG alternate address space and
45a439fe51SSam Ravnborg * shift the value right 28 bits.
46a439fe51SSam Ravnborg */
47a439fe51SSam Ravnborg /* IMPL field means the company which produced the chip. */
48a439fe51SSam Ravnborg #define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */
49a439fe51SSam Ravnborg #define MBUS_LSI 0x3 /* LSI Logics */
50a439fe51SSam Ravnborg #define MBUS_ROSS 0x1 /* Ross is nice */
51a439fe51SSam Ravnborg #define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */
52a439fe51SSam Ravnborg
53a439fe51SSam Ravnborg /* Ross Module versions */
54a439fe51SSam Ravnborg #define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */
55a439fe51SSam Ravnborg #define ROSS_604_REV_F 0x1 /* revision f */
56a439fe51SSam Ravnborg #define ROSS_605 0xf /* revision a, a.1, and a.2 */
57a439fe51SSam Ravnborg #define ROSS_605_REV_B 0xe /* revision b */
58a439fe51SSam Ravnborg
59a439fe51SSam Ravnborg /* TI Viking Module versions */
60a439fe51SSam Ravnborg #define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */
61a439fe51SSam Ravnborg #define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */
62a439fe51SSam Ravnborg #define VIKING_REV_30 0x3 /* Version 3.0 */
63a439fe51SSam Ravnborg #define VIKING_REV_35 0x4 /* Version 3.5 */
64a439fe51SSam Ravnborg
65a439fe51SSam Ravnborg /* LSI Logics. */
66a439fe51SSam Ravnborg #define LSI_L64815 0x0
67a439fe51SSam Ravnborg
68a439fe51SSam Ravnborg /* Fujitsu */
69a439fe51SSam Ravnborg #define FMI_AURORA 0x4 /* MB8690x, a Swift module... */
70a439fe51SSam Ravnborg #define FMI_TURBO 0x5 /* MB86907, a TurboSparc module... */
71a439fe51SSam Ravnborg
72a439fe51SSam Ravnborg /* For multiprocessor support we need to be able to obtain the CPU id and
73a439fe51SSam Ravnborg * the MBUS Module id.
74a439fe51SSam Ravnborg */
75a439fe51SSam Ravnborg
76a439fe51SSam Ravnborg /* The CPU ID is encoded in the trap base register, 20 bits to the left of
77a439fe51SSam Ravnborg * bit zero, with 2 bits being significant.
78a439fe51SSam Ravnborg */
79a439fe51SSam Ravnborg #define TBR_ID_SHIFT 20
80a439fe51SSam Ravnborg
get_cpuid(void)81a439fe51SSam Ravnborg static inline int get_cpuid(void)
82a439fe51SSam Ravnborg {
83a439fe51SSam Ravnborg register int retval;
84a439fe51SSam Ravnborg __asm__ __volatile__("rd %%tbr, %0\n\t"
85a439fe51SSam Ravnborg "srl %0, %1, %0\n\t" :
86a439fe51SSam Ravnborg "=r" (retval) :
87a439fe51SSam Ravnborg "i" (TBR_ID_SHIFT));
88a439fe51SSam Ravnborg return (retval & 3);
89a439fe51SSam Ravnborg }
90a439fe51SSam Ravnborg
get_modid(void)91a439fe51SSam Ravnborg static inline int get_modid(void)
92a439fe51SSam Ravnborg {
93a439fe51SSam Ravnborg return (get_cpuid() | 0x8);
94a439fe51SSam Ravnborg }
95a439fe51SSam Ravnborg
96a439fe51SSam Ravnborg
97a439fe51SSam Ravnborg #endif /* !(_SPARC_MBUS_H) */
98