1 /* cache.h: Cache specific code for the Sparc. These include flushing 2 * and direct tag/data line access. 3 * 4 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net) 5 */ 6 7 #ifndef _SPARC_CACHE_H 8 #define _SPARC_CACHE_H 9 10 #define ARCH_SLAB_MINALIGN __alignof__(unsigned long long) 11 12 #define L1_CACHE_SHIFT 5 13 #define L1_CACHE_BYTES 32 14 #define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))) 15 16 #ifdef CONFIG_SPARC32 17 #define SMP_CACHE_BYTES_SHIFT 5 18 #else 19 #define SMP_CACHE_BYTES_SHIFT 6 20 #endif 21 22 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) 23 24 #define __read_mostly __attribute__((__section__(".data.read_mostly"))) 25 26 #ifdef CONFIG_SPARC32 27 #include <asm/asi.h> 28 29 /* Direct access to the instruction cache is provided through and 30 * alternate address space. The IDC bit must be off in the ICCR on 31 * HyperSparcs for these accesses to work. The code below does not do 32 * any checking, the caller must do so. These routines are for 33 * diagnostics only, but could end up being useful. Use with care. 34 * Also, you are asking for trouble if you execute these in one of the 35 * three instructions following a %asr/%psr access or modification. 36 */ 37 38 /* First, cache-tag access. */ 39 static inline unsigned int get_icache_tag(int setnum, int tagnum) 40 { 41 unsigned int vaddr, retval; 42 43 vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5); 44 __asm__ __volatile__("lda [%1] %2, %0\n\t" : 45 "=r" (retval) : 46 "r" (vaddr), "i" (ASI_M_TXTC_TAG)); 47 return retval; 48 } 49 50 static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry) 51 { 52 unsigned int vaddr; 53 54 vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5); 55 __asm__ __volatile__("sta %0, [%1] %2\n\t" : : 56 "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) : 57 "memory"); 58 } 59 60 /* Second cache-data access. The data is returned two-32bit quantities 61 * at a time. 62 */ 63 static inline void get_icache_data(int setnum, int tagnum, int subblock, 64 unsigned int *data) 65 { 66 unsigned int value1, value2, vaddr; 67 68 vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) | 69 ((subblock&0x3) << 3); 70 __asm__ __volatile__("ldda [%2] %3, %%g2\n\t" 71 "or %%g0, %%g2, %0\n\t" 72 "or %%g0, %%g3, %1\n\t" : 73 "=r" (value1), "=r" (value2) : 74 "r" (vaddr), "i" (ASI_M_TXTC_DATA) : 75 "g2", "g3"); 76 data[0] = value1; data[1] = value2; 77 } 78 79 static inline void put_icache_data(int setnum, int tagnum, int subblock, 80 unsigned int *data) 81 { 82 unsigned int value1, value2, vaddr; 83 84 vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) | 85 ((subblock&0x3) << 3); 86 value1 = data[0]; value2 = data[1]; 87 __asm__ __volatile__("or %%g0, %0, %%g2\n\t" 88 "or %%g0, %1, %%g3\n\t" 89 "stda %%g2, [%2] %3\n\t" : : 90 "r" (value1), "r" (value2), 91 "r" (vaddr), "i" (ASI_M_TXTC_DATA) : 92 "g2", "g3", "memory" /* no joke */); 93 } 94 95 /* Different types of flushes with the ICACHE. Some of the flushes 96 * affect both the ICACHE and the external cache. Others only clear 97 * the ICACHE entries on the cpu itself. V8's (most) allow 98 * granularity of flushes on the packet (element in line), whole line, 99 * and entire cache (ie. all lines) level. The ICACHE only flushes are 100 * ROSS HyperSparc specific and are in ross.h 101 */ 102 103 /* Flushes which clear out both the on-chip and external caches */ 104 static inline void flush_ei_page(unsigned int addr) 105 { 106 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : 107 "r" (addr), "i" (ASI_M_FLUSH_PAGE) : 108 "memory"); 109 } 110 111 static inline void flush_ei_seg(unsigned int addr) 112 { 113 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : 114 "r" (addr), "i" (ASI_M_FLUSH_SEG) : 115 "memory"); 116 } 117 118 static inline void flush_ei_region(unsigned int addr) 119 { 120 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : 121 "r" (addr), "i" (ASI_M_FLUSH_REGION) : 122 "memory"); 123 } 124 125 static inline void flush_ei_ctx(unsigned int addr) 126 { 127 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : 128 "r" (addr), "i" (ASI_M_FLUSH_CTX) : 129 "memory"); 130 } 131 132 static inline void flush_ei_user(unsigned int addr) 133 { 134 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : 135 "r" (addr), "i" (ASI_M_FLUSH_USER) : 136 "memory"); 137 } 138 #endif /* CONFIG_SPARC32 */ 139 140 #endif /* !(_SPARC_CACHE_H) */ 141