1d550bbd4SDavid Howells #ifndef __SPARC64_BARRIER_H 2d550bbd4SDavid Howells #define __SPARC64_BARRIER_H 3d550bbd4SDavid Howells 4d550bbd4SDavid Howells /* These are here in an effort to more fully work around Spitfire Errata 5d550bbd4SDavid Howells * #51. Essentially, if a memory barrier occurs soon after a mispredicted 6d550bbd4SDavid Howells * branch, the chip can stop executing instructions until a trap occurs. 7d550bbd4SDavid Howells * Therefore, if interrupts are disabled, the chip can hang forever. 8d550bbd4SDavid Howells * 9d550bbd4SDavid Howells * It used to be believed that the memory barrier had to be right in the 10d550bbd4SDavid Howells * delay slot, but a case has been traced recently wherein the memory barrier 11d550bbd4SDavid Howells * was one instruction after the branch delay slot and the chip still hung. 12d550bbd4SDavid Howells * The offending sequence was the following in sym_wakeup_done() of the 13d550bbd4SDavid Howells * sym53c8xx_2 driver: 14d550bbd4SDavid Howells * 15d550bbd4SDavid Howells * call sym_ccb_from_dsa, 0 16d550bbd4SDavid Howells * movge %icc, 0, %l0 17d550bbd4SDavid Howells * brz,pn %o0, .LL1303 18d550bbd4SDavid Howells * mov %o0, %l2 19d550bbd4SDavid Howells * membar #LoadLoad 20d550bbd4SDavid Howells * 21d550bbd4SDavid Howells * The branch has to be mispredicted for the bug to occur. Therefore, we put 22d550bbd4SDavid Howells * the memory barrier explicitly into a "branch always, predicted taken" 23d550bbd4SDavid Howells * delay slot to avoid the problem case. 24d550bbd4SDavid Howells */ 25d550bbd4SDavid Howells #define membar_safe(type) \ 26d550bbd4SDavid Howells do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ 27d550bbd4SDavid Howells " membar " type "\n" \ 28d550bbd4SDavid Howells "1:\n" \ 29d550bbd4SDavid Howells : : : "memory"); \ 30d550bbd4SDavid Howells } while (0) 31d550bbd4SDavid Howells 32d550bbd4SDavid Howells /* The kernel always executes in TSO memory model these days, 33d550bbd4SDavid Howells * and furthermore most sparc64 chips implement more stringent 34d550bbd4SDavid Howells * memory ordering than required by the specifications. 35d550bbd4SDavid Howells */ 36d550bbd4SDavid Howells #define mb() membar_safe("#StoreLoad") 37d550bbd4SDavid Howells #define rmb() __asm__ __volatile__("":::"memory") 38d550bbd4SDavid Howells #define wmb() __asm__ __volatile__("":::"memory") 39d550bbd4SDavid Howells 40d550bbd4SDavid Howells #define read_barrier_depends() do { } while(0) 41d550bbd4SDavid Howells #define set_mb(__var, __value) \ 42d550bbd4SDavid Howells do { __var = __value; membar_safe("#StoreLoad"); } while(0) 43d550bbd4SDavid Howells 44d550bbd4SDavid Howells #ifdef CONFIG_SMP 45d550bbd4SDavid Howells #define smp_mb() mb() 46d550bbd4SDavid Howells #define smp_rmb() rmb() 47d550bbd4SDavid Howells #define smp_wmb() wmb() 48d550bbd4SDavid Howells #else 49d550bbd4SDavid Howells #define smp_mb() __asm__ __volatile__("":::"memory") 50d550bbd4SDavid Howells #define smp_rmb() __asm__ __volatile__("":::"memory") 51d550bbd4SDavid Howells #define smp_wmb() __asm__ __volatile__("":::"memory") 52d550bbd4SDavid Howells #endif 53d550bbd4SDavid Howells 54d550bbd4SDavid Howells #define smp_read_barrier_depends() do { } while(0) 55d550bbd4SDavid Howells 5647933ad4SPeter Zijlstra #define smp_store_release(p, v) \ 5747933ad4SPeter Zijlstra do { \ 5847933ad4SPeter Zijlstra compiletime_assert_atomic_type(*p); \ 5947933ad4SPeter Zijlstra barrier(); \ 6047933ad4SPeter Zijlstra ACCESS_ONCE(*p) = (v); \ 6147933ad4SPeter Zijlstra } while (0) 6247933ad4SPeter Zijlstra 6347933ad4SPeter Zijlstra #define smp_load_acquire(p) \ 6447933ad4SPeter Zijlstra ({ \ 6547933ad4SPeter Zijlstra typeof(*p) ___p1 = ACCESS_ONCE(*p); \ 6647933ad4SPeter Zijlstra compiletime_assert_atomic_type(*p); \ 6747933ad4SPeter Zijlstra barrier(); \ 6847933ad4SPeter Zijlstra ___p1; \ 6947933ad4SPeter Zijlstra }) 7047933ad4SPeter Zijlstra 71*56d36489SPeter Zijlstra #define smp_mb__before_atomic() barrier() 72*56d36489SPeter Zijlstra #define smp_mb__after_atomic() barrier() 73*56d36489SPeter Zijlstra 74d550bbd4SDavid Howells #endif /* !(__SPARC64_BARRIER_H) */ 75