1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg /* 3a439fe51SSam Ravnborg * apb.h: Advanced PCI Bridge Configuration Registers and Bits 4a439fe51SSam Ravnborg * 5a439fe51SSam Ravnborg * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 6a439fe51SSam Ravnborg */ 7a439fe51SSam Ravnborg 8a439fe51SSam Ravnborg #ifndef _SPARC64_APB_H 9a439fe51SSam Ravnborg #define _SPARC64_APB_H 10a439fe51SSam Ravnborg 11a439fe51SSam Ravnborg #define APB_TICK_REGISTER 0xb0 12a439fe51SSam Ravnborg #define APB_INT_ACK 0xb8 13a439fe51SSam Ravnborg #define APB_PRIMARY_MASTER_RETRY_LIMIT 0xc0 14a439fe51SSam Ravnborg #define APB_DMA_ASFR 0xc8 15a439fe51SSam Ravnborg #define APB_DMA_AFAR 0xd0 16a439fe51SSam Ravnborg #define APB_PIO_TARGET_RETRY_LIMIT 0xd8 17a439fe51SSam Ravnborg #define APB_PIO_TARGET_LATENCY_TIMER 0xd9 18a439fe51SSam Ravnborg #define APB_DMA_TARGET_RETRY_LIMIT 0xda 19a439fe51SSam Ravnborg #define APB_DMA_TARGET_LATENCY_TIMER 0xdb 20a439fe51SSam Ravnborg #define APB_SECONDARY_MASTER_RETRY_LIMIT 0xdc 21a439fe51SSam Ravnborg #define APB_SECONDARY_CONTROL 0xdd 22a439fe51SSam Ravnborg #define APB_IO_ADDRESS_MAP 0xde 23a439fe51SSam Ravnborg #define APB_MEM_ADDRESS_MAP 0xdf 24a439fe51SSam Ravnborg 25a439fe51SSam Ravnborg #define APB_PCI_CONTROL_LOW 0xe0 26a439fe51SSam Ravnborg # define APB_PCI_CTL_LOW_ARB_PARK (1 << 21) 27a439fe51SSam Ravnborg # define APB_PCI_CTL_LOW_ERRINT_EN (1 << 8) 28a439fe51SSam Ravnborg 29a439fe51SSam Ravnborg #define APB_PCI_CONTROL_HIGH 0xe4 30a439fe51SSam Ravnborg # define APB_PCI_CTL_HIGH_SERR (1 << 2) 31a439fe51SSam Ravnborg # define APB_PCI_CTL_HIGH_ARBITER_EN (1 << 0) 32a439fe51SSam Ravnborg 33a439fe51SSam Ravnborg #define APB_PIO_ASFR 0xe8 34a439fe51SSam Ravnborg #define APB_PIO_AFAR 0xf0 35a439fe51SSam Ravnborg #define APB_DIAG_REGISTER 0xf8 36a439fe51SSam Ravnborg 37a439fe51SSam Ravnborg #endif /* !(_SPARC64_APB_H) */ 38