1 /* 2 * debugfs ops for the L1 cache 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/init.h> 11 #include <linux/module.h> 12 #include <linux/debugfs.h> 13 #include <linux/seq_file.h> 14 #include <asm/processor.h> 15 #include <asm/uaccess.h> 16 #include <asm/cache.h> 17 #include <asm/io.h> 18 19 enum cache_type { 20 CACHE_TYPE_ICACHE, 21 CACHE_TYPE_DCACHE, 22 CACHE_TYPE_UNIFIED, 23 }; 24 25 static int __uses_jump_to_uncached cache_seq_show(struct seq_file *file, 26 void *iter) 27 { 28 unsigned int cache_type = (unsigned int)file->private; 29 struct cache_info *cache; 30 unsigned int waysize, way, cache_size; 31 unsigned long ccr, base; 32 static unsigned long addrstart = 0; 33 34 /* 35 * Go uncached immediately so we don't skew the results any 36 * more than we already are.. 37 */ 38 jump_to_uncached(); 39 40 ccr = ctrl_inl(CCR); 41 if ((ccr & CCR_CACHE_ENABLE) == 0) { 42 back_to_cached(); 43 44 seq_printf(file, "disabled\n"); 45 return 0; 46 } 47 48 if (cache_type == CACHE_TYPE_DCACHE) { 49 base = CACHE_OC_ADDRESS_ARRAY; 50 cache = ¤t_cpu_data.dcache; 51 } else { 52 base = CACHE_IC_ADDRESS_ARRAY; 53 cache = ¤t_cpu_data.icache; 54 } 55 56 /* 57 * Due to the amount of data written out (depending on the cache size), 58 * we may be iterated over multiple times. In this case, keep track of 59 * the entry position in addrstart, and rewind it when we've hit the 60 * end of the cache. 61 * 62 * Likewise, the same code is used for multiple caches, so care must 63 * be taken for bouncing addrstart back and forth so the appropriate 64 * cache is hit. 65 */ 66 cache_size = cache->ways * cache->sets * cache->linesz; 67 if (((addrstart & 0xff000000) != base) || 68 (addrstart & 0x00ffffff) > cache_size) 69 addrstart = base; 70 71 waysize = cache->sets; 72 73 /* 74 * If the OC is already in RAM mode, we only have 75 * half of the entries to consider.. 76 */ 77 if ((ccr & CCR_CACHE_ORA) && cache_type == CACHE_TYPE_DCACHE) 78 waysize >>= 1; 79 80 waysize <<= cache->entry_shift; 81 82 for (way = 0; way < cache->ways; way++) { 83 unsigned long addr; 84 unsigned int line; 85 86 seq_printf(file, "-----------------------------------------\n"); 87 seq_printf(file, "Way %d\n", way); 88 seq_printf(file, "-----------------------------------------\n"); 89 90 for (addr = addrstart, line = 0; 91 addr < addrstart + waysize; 92 addr += cache->linesz, line++) { 93 unsigned long data = ctrl_inl(addr); 94 95 /* Check the V bit, ignore invalid cachelines */ 96 if ((data & 1) == 0) 97 continue; 98 99 /* U: Dirty, cache tag is 10 bits up */ 100 seq_printf(file, "%3d: %c 0x%lx\n", 101 line, data & 2 ? 'U' : ' ', 102 data & 0x1ffffc00); 103 } 104 105 addrstart += cache->way_incr; 106 } 107 108 back_to_cached(); 109 110 return 0; 111 } 112 113 static int cache_debugfs_open(struct inode *inode, struct file *file) 114 { 115 return single_open(file, cache_seq_show, inode->i_private); 116 } 117 118 static const struct file_operations cache_debugfs_fops = { 119 .owner = THIS_MODULE, 120 .open = cache_debugfs_open, 121 .read = seq_read, 122 .llseek = seq_lseek, 123 .release = single_release, 124 }; 125 126 static int __init cache_debugfs_init(void) 127 { 128 struct dentry *dcache_dentry, *icache_dentry; 129 130 dcache_dentry = debugfs_create_file("dcache", S_IRUSR, sh_debugfs_root, 131 (unsigned int *)CACHE_TYPE_DCACHE, 132 &cache_debugfs_fops); 133 if (!dcache_dentry) 134 return -ENOMEM; 135 if (IS_ERR(dcache_dentry)) 136 return PTR_ERR(dcache_dentry); 137 138 icache_dentry = debugfs_create_file("icache", S_IRUSR, sh_debugfs_root, 139 (unsigned int *)CACHE_TYPE_ICACHE, 140 &cache_debugfs_fops); 141 if (!icache_dentry) { 142 debugfs_remove(dcache_dentry); 143 return -ENOMEM; 144 } 145 if (IS_ERR(icache_dentry)) { 146 debugfs_remove(dcache_dentry); 147 return PTR_ERR(icache_dentry); 148 } 149 150 return 0; 151 } 152 module_init(cache_debugfs_init); 153 154 MODULE_LICENSE("GPL v2"); 155