xref: /linux/arch/sh/mm/Kconfig (revision f3d2229852697062d530f19742f0ab792b92873d)
1#
2# Processor families
3#
4config CPU_SH2
5	select SH_WRITETHROUGH if !CPU_SH2A
6	bool
7
8config CPU_SH2A
9	bool
10	select CPU_SH2
11
12config CPU_SH3
13	bool
14	select CPU_HAS_INTEVT
15	select CPU_HAS_SR_RB
16
17config CPU_SH4
18	bool
19	select CPU_HAS_INTEVT
20	select CPU_HAS_SR_RB
21	select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
22
23config CPU_SH4A
24	bool
25	select CPU_SH4
26
27config CPU_SH4AL_DSP
28	bool
29	select CPU_SH4A
30
31config CPU_SUBTYPE_ST40
32	bool
33	select CPU_SH4
34	select CPU_HAS_INTC2_IRQ
35
36config CPU_SHX2
37	bool
38
39choice
40	prompt "Processor sub-type selection"
41
42#
43# Processor subtypes
44#
45
46# SH-2 Processor Support
47
48config CPU_SUBTYPE_SH7604
49	bool "Support SH7604 processor"
50	select CPU_SH2
51
52config CPU_SUBTYPE_SH7619
53	bool "Support SH7619 processor"
54	select CPU_SH2
55
56# SH-2A Processor Support
57
58config CPU_SUBTYPE_SH7206
59	bool "Support SH7206 processor"
60	select CPU_SH2A
61
62# SH-3 Processor Support
63
64config CPU_SUBTYPE_SH7300
65	bool "Support SH7300 processor"
66	select CPU_SH3
67
68config CPU_SUBTYPE_SH7705
69	bool "Support SH7705 processor"
70	select CPU_SH3
71	select CPU_HAS_IPR_IRQ
72	select CPU_HAS_PINT_IRQ
73
74config CPU_SUBTYPE_SH7706
75	bool "Support SH7706 processor"
76	select CPU_SH3
77	select CPU_HAS_IPR_IRQ
78	help
79	  Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
80
81config CPU_SUBTYPE_SH7707
82	bool "Support SH7707 processor"
83	select CPU_SH3
84	select CPU_HAS_PINT_IRQ
85	help
86	  Select SH7707 if you have a  60 Mhz SH-3 HD6417707 CPU.
87
88config CPU_SUBTYPE_SH7708
89	bool "Support SH7708 processor"
90	select CPU_SH3
91	help
92	  Select SH7708 if you have a  60 Mhz SH-3 HD6417708S or
93	  if you have a 100 Mhz SH-3 HD6417708R CPU.
94
95config CPU_SUBTYPE_SH7709
96	bool "Support SH7709 processor"
97	select CPU_SH3
98	select CPU_HAS_IPR_IRQ
99	select CPU_HAS_PINT_IRQ
100	help
101	  Select SH7709 if you have a  80 Mhz SH-3 HD6417709 CPU.
102
103config CPU_SUBTYPE_SH7710
104	bool "Support SH7710 processor"
105	select CPU_SH3
106	select CPU_HAS_IPR_IRQ
107	help
108	  Select SH7710 if you have a SH3-DSP SH7710 CPU.
109
110config CPU_SUBTYPE_SH7712
111	bool "Support SH7712 processor"
112	select CPU_SH3
113	select CPU_HAS_IPR_IRQ
114	help
115	  Select SH7712 if you have a SH3-DSP SH7712 CPU.
116
117# SH-4 Processor Support
118
119config CPU_SUBTYPE_SH7750
120	bool "Support SH7750 processor"
121	select CPU_SH4
122	select CPU_HAS_IPR_IRQ
123	help
124	  Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
125
126config CPU_SUBTYPE_SH7091
127	bool "Support SH7091 processor"
128	select CPU_SH4
129	select CPU_SUBTYPE_SH7750
130	help
131	  Select SH7091 if you have an SH-4 based Sega device (such as
132	  the Dreamcast, Naomi, and Naomi 2).
133
134config CPU_SUBTYPE_SH7750R
135	bool "Support SH7750R processor"
136	select CPU_SH4
137	select CPU_SUBTYPE_SH7750
138	select CPU_HAS_IPR_IRQ
139
140config CPU_SUBTYPE_SH7750S
141	bool "Support SH7750S processor"
142	select CPU_SH4
143	select CPU_SUBTYPE_SH7750
144	select CPU_HAS_IPR_IRQ
145
146config CPU_SUBTYPE_SH7751
147	bool "Support SH7751 processor"
148	select CPU_SH4
149	select CPU_HAS_IPR_IRQ
150	help
151	  Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
152	  or if you have a HD6417751R CPU.
153
154config CPU_SUBTYPE_SH7751R
155	bool "Support SH7751R processor"
156	select CPU_SH4
157	select CPU_SUBTYPE_SH7751
158	select CPU_HAS_IPR_IRQ
159
160config CPU_SUBTYPE_SH7760
161	bool "Support SH7760 processor"
162	select CPU_SH4
163	select CPU_HAS_INTC2_IRQ
164	select CPU_HAS_IPR_IRQ
165
166config CPU_SUBTYPE_SH4_202
167	bool "Support SH4-202 processor"
168	select CPU_SH4
169
170# ST40 Processor Support
171
172config CPU_SUBTYPE_ST40STB1
173	bool "Support ST40STB1/ST40RA processors"
174	select CPU_SUBTYPE_ST40
175	help
176	  Select ST40STB1 if you have a ST40RA CPU.
177	  This was previously called the ST40STB1, hence the option name.
178
179config CPU_SUBTYPE_ST40GX1
180	bool "Support ST40GX1 processor"
181	select CPU_SUBTYPE_ST40
182	help
183	  Select ST40GX1 if you have a ST40GX1 CPU.
184
185# SH-4A Processor Support
186
187config CPU_SUBTYPE_SH7770
188	bool "Support SH7770 processor"
189	select CPU_SH4A
190
191config CPU_SUBTYPE_SH7780
192	bool "Support SH7780 processor"
193	select CPU_SH4A
194	select CPU_HAS_INTC2_IRQ
195
196config CPU_SUBTYPE_SH7785
197	bool "Support SH7785 processor"
198	select CPU_SH4A
199	select CPU_SHX2
200	select CPU_HAS_INTC2_IRQ
201
202# SH4AL-DSP Processor Support
203
204config CPU_SUBTYPE_SH73180
205	bool "Support SH73180 processor"
206	select CPU_SH4AL_DSP
207
208config CPU_SUBTYPE_SH7343
209	bool "Support SH7343 processor"
210	select CPU_SH4AL_DSP
211
212config CPU_SUBTYPE_SH7722
213	bool "Support SH7722 processor"
214	select CPU_SH4AL_DSP
215	select CPU_SHX2
216	select CPU_HAS_IPR_IRQ
217
218endchoice
219
220menu "Memory management options"
221
222config QUICKLIST
223	def_bool y
224
225config MMU
226        bool "Support for memory management hardware"
227	depends on !CPU_SH2
228	default y
229	help
230	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
231	  boot on these systems, this option must not be set.
232
233	  On other systems (such as the SH-3 and 4) where an MMU exists,
234	  turning this off will boot the kernel on these machines with the
235	  MMU implicitly switched off.
236
237config PAGE_OFFSET
238	hex
239	default "0x80000000" if MMU
240	default "0x00000000"
241
242config MEMORY_START
243	hex "Physical memory start address"
244	default "0x08000000"
245	---help---
246	  Computers built with Hitachi SuperH processors always
247	  map the ROM starting at address zero.  But the processor
248	  does not specify the range that RAM takes.
249
250	  The physical memory (RAM) start address will be automatically
251	  set to 08000000. Other platforms, such as the Solution Engine
252	  boards typically map RAM at 0C000000.
253
254	  Tweak this only when porting to a new machine which does not
255	  already have a defconfig. Changing it from the known correct
256	  value on any of the known systems will only lead to disaster.
257
258config MEMORY_SIZE
259	hex "Physical memory size"
260	default "0x00400000"
261	help
262	  This sets the default memory size assumed by your SH kernel. It can
263	  be overridden as normal by the 'mem=' argument on the kernel command
264	  line. If unsure, consult your board specifications or just leave it
265	  as 0x00400000 which was the default value before this became
266	  configurable.
267
268config 32BIT
269	bool "Support 32-bit physical addressing through PMB"
270	depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
271	default y
272	help
273	  If you say Y here, physical addressing will be extended to
274	  32-bits through the SH-4A PMB. If this is not set, legacy
275	  29-bit physical addressing will be used.
276
277config X2TLB
278	bool "Enable extended TLB mode"
279	depends on CPU_SHX2 && MMU && EXPERIMENTAL
280	help
281	  Selecting this option will enable the extended mode of the SH-X2
282	  TLB. For legacy SH-X behaviour and interoperability, say N. For
283	  all of the fun new features and a willingless to submit bug reports,
284	  say Y.
285
286config VSYSCALL
287	bool "Support vsyscall page"
288	depends on MMU
289	default y
290	help
291	  This will enable support for the kernel mapping a vDSO page
292	  in process space, and subsequently handing down the entry point
293	  to the libc through the ELF auxiliary vector.
294
295	  From the kernel side this is used for the signal trampoline.
296	  For systems with an MMU that can afford to give up a page,
297	  (the default value) say Y.
298
299config NODES_SHIFT
300	int
301	default "1"
302	depends on NEED_MULTIPLE_NODES
303
304config ARCH_FLATMEM_ENABLE
305	def_bool y
306
307config MAX_ACTIVE_REGIONS
308	int
309	default "1"
310
311config ARCH_POPULATES_NODE_MAP
312	def_bool y
313
314choice
315	prompt "Kernel page size"
316	default PAGE_SIZE_4KB
317
318config PAGE_SIZE_4KB
319	bool "4kB"
320	help
321	  This is the default page size used by all SuperH CPUs.
322
323config PAGE_SIZE_8KB
324	bool "8kB"
325	depends on EXPERIMENTAL && X2TLB
326	help
327	  This enables 8kB pages as supported by SH-X2 and later MMUs.
328
329config PAGE_SIZE_64KB
330	bool "64kB"
331	depends on EXPERIMENTAL && CPU_SH4
332	help
333	  This enables support for 64kB pages, possible on all SH-4
334	  CPUs and later. Highly experimental, not recommended.
335
336endchoice
337
338choice
339	prompt "HugeTLB page size"
340	depends on HUGETLB_PAGE && CPU_SH4 && MMU
341	default HUGETLB_PAGE_SIZE_64K
342
343config HUGETLB_PAGE_SIZE_64K
344	bool "64kB"
345
346config HUGETLB_PAGE_SIZE_256K
347	bool "256kB"
348	depends on X2TLB
349
350config HUGETLB_PAGE_SIZE_1MB
351	bool "1MB"
352
353config HUGETLB_PAGE_SIZE_4MB
354	bool "4MB"
355	depends on X2TLB
356
357config HUGETLB_PAGE_SIZE_64MB
358	bool "64MB"
359	depends on X2TLB
360
361endchoice
362
363source "mm/Kconfig"
364
365endmenu
366
367menu "Cache configuration"
368
369config SH7705_CACHE_32KB
370	bool "Enable 32KB cache size for SH7705"
371	depends on CPU_SUBTYPE_SH7705
372	default y
373
374config SH_DIRECT_MAPPED
375	bool "Use direct-mapped caching"
376	default n
377	help
378	  Selecting this option will configure the caches to be direct-mapped,
379	  even if the cache supports a 2 or 4-way mode. This is useful primarily
380	  for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
381	  SH4-202, SH4-501, etc.)
382
383	  Turn this option off for platforms that do not have a direct-mapped
384	  cache, and you have no need to run the caches in such a configuration.
385
386config SH_WRITETHROUGH
387	bool "Use write-through caching"
388	help
389	  Selecting this option will configure the caches in write-through
390	  mode, as opposed to the default write-back configuration.
391
392	  Since there's sill some aliasing issues on SH-4, this option will
393	  unfortunately still require the majority of flushing functions to
394	  be implemented to deal with aliasing.
395
396	  If unsure, say N.
397
398config SH_OCRAM
399	bool "Operand Cache RAM (OCRAM) support"
400	help
401	  Selecting this option will automatically tear down the number of
402	  sets in the dcache by half, which in turn exposes a memory range.
403
404	  The addresses for the OC RAM base will vary according to the
405	  processor version. Consult vendor documentation for specifics.
406
407	  If unsure, say N.
408
409endmenu
410