1# SPDX-License-Identifier: GPL-2.0 2menu "Memory management options" 3 4config MMU 5 bool "Support for memory management hardware" 6 depends on !CPU_SH2 7 default y 8 help 9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 10 boot on these systems, this option must not be set. 11 12 On other systems (such as the SH-3 and 4) where an MMU exists, 13 turning this off will boot the kernel on these machines with the 14 MMU implicitly switched off. 15 16config PAGE_OFFSET 17 hex 18 default "0x80000000" if MMU 19 default "0x00000000" 20 21config ARCH_FORCE_MAX_ORDER 22 int "Maximum zone order" 23 range 9 64 if PAGE_SIZE_16KB 24 default "9" if PAGE_SIZE_16KB 25 range 7 64 if PAGE_SIZE_64KB 26 default "7" if PAGE_SIZE_64KB 27 range 11 64 28 default "14" if !MMU 29 default "11" 30 help 31 The kernel memory allocator divides physically contiguous memory 32 blocks into "zones", where each zone is a power of two number of 33 pages. This option selects the largest power of two that the kernel 34 keeps in the memory allocator. If you need to allocate very large 35 blocks of physically contiguous memory, then you may need to 36 increase this value. 37 38 This config option is actually maximum order plus one. For example, 39 a value of 11 means that the largest free memory block is 2^10 pages. 40 41 The page size is not necessarily 4KB. Keep this in mind when 42 choosing a value for this option. 43 44config MEMORY_START 45 hex "Physical memory start address" 46 default "0x08000000" 47 help 48 Computers built with Hitachi SuperH processors always 49 map the ROM starting at address zero. But the processor 50 does not specify the range that RAM takes. 51 52 The physical memory (RAM) start address will be automatically 53 set to 08000000. Other platforms, such as the Solution Engine 54 boards typically map RAM at 0C000000. 55 56 Tweak this only when porting to a new machine which does not 57 already have a defconfig. Changing it from the known correct 58 value on any of the known systems will only lead to disaster. 59 60config MEMORY_SIZE 61 hex "Physical memory size" 62 default "0x04000000" 63 help 64 This sets the default memory size assumed by your SH kernel. It can 65 be overridden as normal by the 'mem=' argument on the kernel command 66 line. If unsure, consult your board specifications or just leave it 67 as 0x04000000 which was the default value before this became 68 configurable. 69 70# Physical addressing modes 71 72config 29BIT 73 def_bool !32BIT 74 select UNCACHED_MAPPING 75 76config 32BIT 77 bool 78 default !MMU 79 80config PMB 81 bool "Support 32-bit physical addressing through PMB" 82 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP 83 select 32BIT 84 select UNCACHED_MAPPING 85 help 86 If you say Y here, physical addressing will be extended to 87 32-bits through the SH-4A PMB. If this is not set, legacy 88 29-bit physical addressing will be used. 89 90config X2TLB 91 def_bool y 92 depends on (CPU_SHX2 || CPU_SHX3) && MMU 93 94config VSYSCALL 95 bool "Support vsyscall page" 96 depends on MMU && (CPU_SH3 || CPU_SH4) 97 default y 98 help 99 This will enable support for the kernel mapping a vDSO page 100 in process space, and subsequently handing down the entry point 101 to the libc through the ELF auxiliary vector. 102 103 From the kernel side this is used for the signal trampoline. 104 For systems with an MMU that can afford to give up a page, 105 (the default value) say Y. 106 107config NUMA 108 bool "Non-Uniform Memory Access (NUMA) Support" 109 depends on MMU && SYS_SUPPORTS_NUMA 110 select ARCH_WANT_NUMA_VARIABLE_LOCALITY 111 default n 112 help 113 Some SH systems have many various memories scattered around 114 the address space, each with varying latencies. This enables 115 support for these blocks by binding them to nodes and allowing 116 memory policies to be used for prioritizing and controlling 117 allocation behaviour. 118 119config NODES_SHIFT 120 int 121 default "3" if CPU_SUBTYPE_SHX3 122 default "1" 123 depends on NUMA 124 125config ARCH_FLATMEM_ENABLE 126 def_bool y 127 depends on !NUMA 128 129config ARCH_SPARSEMEM_ENABLE 130 def_bool y 131 select SPARSEMEM_STATIC 132 133config ARCH_SPARSEMEM_DEFAULT 134 def_bool y 135 136config ARCH_SELECT_MEMORY_MODEL 137 def_bool y 138 139config ARCH_MEMORY_PROBE 140 def_bool y 141 depends on MEMORY_HOTPLUG 142 143config IOREMAP_FIXED 144 def_bool y 145 depends on X2TLB 146 147config UNCACHED_MAPPING 148 bool 149 150config HAVE_SRAM_POOL 151 bool 152 select GENERIC_ALLOCATOR 153 154choice 155 prompt "Kernel page size" 156 default PAGE_SIZE_4KB 157 158config PAGE_SIZE_4KB 159 bool "4kB" 160 help 161 This is the default page size used by all SuperH CPUs. 162 163config PAGE_SIZE_8KB 164 bool "8kB" 165 depends on !MMU || X2TLB 166 help 167 This enables 8kB pages as supported by SH-X2 and later MMUs. 168 169config PAGE_SIZE_16KB 170 bool "16kB" 171 depends on !MMU 172 help 173 This enables 16kB pages on MMU-less SH systems. 174 175config PAGE_SIZE_64KB 176 bool "64kB" 177 depends on !MMU || CPU_SH4 178 help 179 This enables support for 64kB pages, possible on all SH-4 180 CPUs and later. 181 182endchoice 183 184choice 185 prompt "HugeTLB page size" 186 depends on HUGETLB_PAGE 187 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB 188 default HUGETLB_PAGE_SIZE_64K 189 190config HUGETLB_PAGE_SIZE_64K 191 bool "64kB" 192 depends on !PAGE_SIZE_64KB 193 194config HUGETLB_PAGE_SIZE_256K 195 bool "256kB" 196 depends on X2TLB 197 198config HUGETLB_PAGE_SIZE_1MB 199 bool "1MB" 200 201config HUGETLB_PAGE_SIZE_4MB 202 bool "4MB" 203 depends on X2TLB 204 205config HUGETLB_PAGE_SIZE_64MB 206 bool "64MB" 207 depends on X2TLB 208 209endchoice 210 211config SCHED_MC 212 bool "Multi-core scheduler support" 213 depends on SMP 214 default y 215 help 216 Multi-core scheduler support improves the CPU scheduler's decision 217 making when dealing with multi-core CPU chips at a cost of slightly 218 increased overhead in some places. If unsure say N here. 219 220endmenu 221 222menu "Cache configuration" 223 224config SH7705_CACHE_32KB 225 bool "Enable 32KB cache size for SH7705" 226 depends on CPU_SUBTYPE_SH7705 227 default y 228 229choice 230 prompt "Cache mode" 231 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 232 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) 233 234config CACHE_WRITEBACK 235 bool "Write-back" 236 237config CACHE_WRITETHROUGH 238 bool "Write-through" 239 help 240 Selecting this option will configure the caches in write-through 241 mode, as opposed to the default write-back configuration. 242 243 Since there's sill some aliasing issues on SH-4, this option will 244 unfortunately still require the majority of flushing functions to 245 be implemented to deal with aliasing. 246 247 If unsure, say N. 248 249config CACHE_OFF 250 bool "Off" 251 252endchoice 253 254endmenu 255