1# 2# Processor families 3# 4config CPU_SH2 5 bool 6 7config CPU_SH2A 8 bool 9 select CPU_SH2 10 11config CPU_SH3 12 bool 13 select CPU_HAS_INTEVT 14 select CPU_HAS_SR_RB 15 16config CPU_SH4 17 bool 18 select CPU_HAS_INTEVT 19 select CPU_HAS_SR_RB 20 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2 21 select CPU_HAS_FPU if !CPU_SH4AL_DSP 22 23config CPU_SH4A 24 bool 25 select CPU_SH4 26 27config CPU_SH4AL_DSP 28 bool 29 select CPU_SH4A 30 select CPU_HAS_DSP 31 32config CPU_SUBTYPE_ST40 33 bool 34 select CPU_SH4 35 36config CPU_SHX2 37 bool 38 39config CPU_SHX3 40 bool 41 42choice 43 prompt "Processor sub-type selection" 44 45# 46# Processor subtypes 47# 48 49# SH-2 Processor Support 50 51config CPU_SUBTYPE_SH7619 52 bool "Support SH7619 processor" 53 select CPU_SH2 54 55# SH-2A Processor Support 56 57config CPU_SUBTYPE_SH7206 58 bool "Support SH7206 processor" 59 select CPU_SH2A 60 61# SH-3 Processor Support 62 63config CPU_SUBTYPE_SH7705 64 bool "Support SH7705 processor" 65 select CPU_SH3 66 67config CPU_SUBTYPE_SH7706 68 bool "Support SH7706 processor" 69 select CPU_SH3 70 help 71 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. 72 73config CPU_SUBTYPE_SH7707 74 bool "Support SH7707 processor" 75 select CPU_SH3 76 help 77 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. 78 79config CPU_SUBTYPE_SH7708 80 bool "Support SH7708 processor" 81 select CPU_SH3 82 help 83 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or 84 if you have a 100 Mhz SH-3 HD6417708R CPU. 85 86config CPU_SUBTYPE_SH7709 87 bool "Support SH7709 processor" 88 select CPU_SH3 89 help 90 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. 91 92config CPU_SUBTYPE_SH7710 93 bool "Support SH7710 processor" 94 select CPU_SH3 95 select CPU_HAS_DSP 96 help 97 Select SH7710 if you have a SH3-DSP SH7710 CPU. 98 99config CPU_SUBTYPE_SH7712 100 bool "Support SH7712 processor" 101 select CPU_SH3 102 select CPU_HAS_DSP 103 help 104 Select SH7712 if you have a SH3-DSP SH7712 CPU. 105 106config CPU_SUBTYPE_SH7720 107 bool "Support SH7720 processor" 108 select CPU_SH3 109 select CPU_HAS_DSP 110 help 111 Select SH7720 if you have a SH3-DSP SH7720 CPU. 112 113# SH-4 Processor Support 114 115config CPU_SUBTYPE_SH7750 116 bool "Support SH7750 processor" 117 select CPU_SH4 118 help 119 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. 120 121config CPU_SUBTYPE_SH7091 122 bool "Support SH7091 processor" 123 select CPU_SH4 124 help 125 Select SH7091 if you have an SH-4 based Sega device (such as 126 the Dreamcast, Naomi, and Naomi 2). 127 128config CPU_SUBTYPE_SH7750R 129 bool "Support SH7750R processor" 130 select CPU_SH4 131 132config CPU_SUBTYPE_SH7750S 133 bool "Support SH7750S processor" 134 select CPU_SH4 135 136config CPU_SUBTYPE_SH7751 137 bool "Support SH7751 processor" 138 select CPU_SH4 139 help 140 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, 141 or if you have a HD6417751R CPU. 142 143config CPU_SUBTYPE_SH7751R 144 bool "Support SH7751R processor" 145 select CPU_SH4 146 147config CPU_SUBTYPE_SH7760 148 bool "Support SH7760 processor" 149 select CPU_SH4 150 151config CPU_SUBTYPE_SH4_202 152 bool "Support SH4-202 processor" 153 select CPU_SH4 154 155# ST40 Processor Support 156 157config CPU_SUBTYPE_ST40STB1 158 bool "Support ST40STB1/ST40RA processors" 159 select CPU_SUBTYPE_ST40 160 help 161 Select ST40STB1 if you have a ST40RA CPU. 162 This was previously called the ST40STB1, hence the option name. 163 164config CPU_SUBTYPE_ST40GX1 165 bool "Support ST40GX1 processor" 166 select CPU_SUBTYPE_ST40 167 help 168 Select ST40GX1 if you have a ST40GX1 CPU. 169 170# SH-4A Processor Support 171 172config CPU_SUBTYPE_SH7770 173 bool "Support SH7770 processor" 174 select CPU_SH4A 175 176config CPU_SUBTYPE_SH7780 177 bool "Support SH7780 processor" 178 select CPU_SH4A 179 180config CPU_SUBTYPE_SH7785 181 bool "Support SH7785 processor" 182 select CPU_SH4A 183 select CPU_SHX2 184 select ARCH_SPARSEMEM_ENABLE 185 select SYS_SUPPORTS_NUMA 186 187config CPU_SUBTYPE_SHX3 188 bool "Support SH-X3 processor" 189 select CPU_SH4A 190 select CPU_SHX3 191 select ARCH_SPARSEMEM_ENABLE 192 select SYS_SUPPORTS_NUMA 193 194# SH4AL-DSP Processor Support 195 196config CPU_SUBTYPE_SH7343 197 bool "Support SH7343 processor" 198 select CPU_SH4AL_DSP 199 200config CPU_SUBTYPE_SH7722 201 bool "Support SH7722 processor" 202 select CPU_SH4AL_DSP 203 select CPU_SHX2 204 select ARCH_SPARSEMEM_ENABLE 205 select SYS_SUPPORTS_NUMA 206 207endchoice 208 209menu "Memory management options" 210 211config QUICKLIST 212 def_bool y 213 214config MMU 215 bool "Support for memory management hardware" 216 depends on !CPU_SH2 217 default y 218 help 219 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 220 boot on these systems, this option must not be set. 221 222 On other systems (such as the SH-3 and 4) where an MMU exists, 223 turning this off will boot the kernel on these machines with the 224 MMU implicitly switched off. 225 226config PAGE_OFFSET 227 hex 228 default "0x80000000" if MMU 229 default "0x00000000" 230 231config MEMORY_START 232 hex "Physical memory start address" 233 default "0x08000000" 234 ---help--- 235 Computers built with Hitachi SuperH processors always 236 map the ROM starting at address zero. But the processor 237 does not specify the range that RAM takes. 238 239 The physical memory (RAM) start address will be automatically 240 set to 08000000. Other platforms, such as the Solution Engine 241 boards typically map RAM at 0C000000. 242 243 Tweak this only when porting to a new machine which does not 244 already have a defconfig. Changing it from the known correct 245 value on any of the known systems will only lead to disaster. 246 247config MEMORY_SIZE 248 hex "Physical memory size" 249 default "0x00400000" 250 help 251 This sets the default memory size assumed by your SH kernel. It can 252 be overridden as normal by the 'mem=' argument on the kernel command 253 line. If unsure, consult your board specifications or just leave it 254 as 0x00400000 which was the default value before this became 255 configurable. 256 257config 32BIT 258 bool "Support 32-bit physical addressing through PMB" 259 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) 260 default y 261 help 262 If you say Y here, physical addressing will be extended to 263 32-bits through the SH-4A PMB. If this is not set, legacy 264 29-bit physical addressing will be used. 265 266config X2TLB 267 bool "Enable extended TLB mode" 268 depends on CPU_SHX2 && MMU && EXPERIMENTAL 269 help 270 Selecting this option will enable the extended mode of the SH-X2 271 TLB. For legacy SH-X behaviour and interoperability, say N. For 272 all of the fun new features and a willingless to submit bug reports, 273 say Y. 274 275config VSYSCALL 276 bool "Support vsyscall page" 277 depends on MMU 278 default y 279 help 280 This will enable support for the kernel mapping a vDSO page 281 in process space, and subsequently handing down the entry point 282 to the libc through the ELF auxiliary vector. 283 284 From the kernel side this is used for the signal trampoline. 285 For systems with an MMU that can afford to give up a page, 286 (the default value) say Y. 287 288config NUMA 289 bool "Non Uniform Memory Access (NUMA) Support" 290 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL 291 default n 292 help 293 Some SH systems have many various memories scattered around 294 the address space, each with varying latencies. This enables 295 support for these blocks by binding them to nodes and allowing 296 memory policies to be used for prioritizing and controlling 297 allocation behaviour. 298 299config NODES_SHIFT 300 int 301 default "3" if CPU_SUBTYPE_SHX3 302 default "1" 303 depends on NEED_MULTIPLE_NODES 304 305config ARCH_FLATMEM_ENABLE 306 def_bool y 307 depends on !NUMA 308 309config ARCH_SPARSEMEM_ENABLE 310 def_bool y 311 select SPARSEMEM_STATIC 312 313config ARCH_SPARSEMEM_DEFAULT 314 def_bool y 315 316config MAX_ACTIVE_REGIONS 317 int 318 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM) 319 default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM) 320 default "1" 321 322config ARCH_POPULATES_NODE_MAP 323 def_bool y 324 325config ARCH_SELECT_MEMORY_MODEL 326 def_bool y 327 328config ARCH_ENABLE_MEMORY_HOTPLUG 329 def_bool y 330 depends on SPARSEMEM 331 332config ARCH_MEMORY_PROBE 333 def_bool y 334 depends on MEMORY_HOTPLUG 335 336choice 337 prompt "Kernel page size" 338 default PAGE_SIZE_4KB 339 340config PAGE_SIZE_4KB 341 bool "4kB" 342 help 343 This is the default page size used by all SuperH CPUs. 344 345config PAGE_SIZE_8KB 346 bool "8kB" 347 depends on EXPERIMENTAL && X2TLB 348 help 349 This enables 8kB pages as supported by SH-X2 and later MMUs. 350 351config PAGE_SIZE_64KB 352 bool "64kB" 353 depends on EXPERIMENTAL && CPU_SH4 354 help 355 This enables support for 64kB pages, possible on all SH-4 356 CPUs and later. Highly experimental, not recommended. 357 358endchoice 359 360choice 361 prompt "HugeTLB page size" 362 depends on HUGETLB_PAGE && CPU_SH4 && MMU 363 default HUGETLB_PAGE_SIZE_64K 364 365config HUGETLB_PAGE_SIZE_64K 366 bool "64kB" 367 368config HUGETLB_PAGE_SIZE_256K 369 bool "256kB" 370 depends on X2TLB 371 372config HUGETLB_PAGE_SIZE_1MB 373 bool "1MB" 374 375config HUGETLB_PAGE_SIZE_4MB 376 bool "4MB" 377 depends on X2TLB 378 379config HUGETLB_PAGE_SIZE_64MB 380 bool "64MB" 381 depends on X2TLB 382 383endchoice 384 385source "mm/Kconfig" 386 387endmenu 388 389menu "Cache configuration" 390 391config SH7705_CACHE_32KB 392 bool "Enable 32KB cache size for SH7705" 393 depends on CPU_SUBTYPE_SH7705 394 default y 395 396config SH_DIRECT_MAPPED 397 bool "Use direct-mapped caching" 398 default n 399 help 400 Selecting this option will configure the caches to be direct-mapped, 401 even if the cache supports a 2 or 4-way mode. This is useful primarily 402 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R, 403 SH4-202, SH4-501, etc.) 404 405 Turn this option off for platforms that do not have a direct-mapped 406 cache, and you have no need to run the caches in such a configuration. 407 408choice 409 prompt "Cache mode" 410 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 411 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) 412 413config CACHE_WRITEBACK 414 bool "Write-back" 415 depends on CPU_SH2A || CPU_SH3 || CPU_SH4 416 417config CACHE_WRITETHROUGH 418 bool "Write-through" 419 help 420 Selecting this option will configure the caches in write-through 421 mode, as opposed to the default write-back configuration. 422 423 Since there's sill some aliasing issues on SH-4, this option will 424 unfortunately still require the majority of flushing functions to 425 be implemented to deal with aliasing. 426 427 If unsure, say N. 428 429config CACHE_OFF 430 bool "Off" 431 432endchoice 433 434endmenu 435