1menu "Processor selection" 2 3# 4# Processor families 5# 6config CPU_SH2 7 select SH_WRITETHROUGH if !CPU_SH2A 8 bool 9 10config CPU_SH2A 11 bool 12 select CPU_SH2 13 14config CPU_SH3 15 bool 16 select CPU_HAS_INTEVT 17 select CPU_HAS_SR_RB 18 19config CPU_SH4 20 bool 21 select CPU_HAS_INTEVT 22 select CPU_HAS_SR_RB 23 select CPU_HAS_PTEA if !CPU_SUBTYPE_ST40 24 25config CPU_SH4A 26 bool 27 select CPU_SH4 28 29config CPU_SH4AL_DSP 30 bool 31 select CPU_SH4A 32 33config CPU_SUBTYPE_ST40 34 bool 35 select CPU_SH4 36 select CPU_HAS_INTC2_IRQ 37 38# 39# Processor subtypes 40# 41 42comment "SH-2 Processor Support" 43 44config CPU_SUBTYPE_SH7604 45 bool "Support SH7604 processor" 46 select CPU_SH2 47 48config CPU_SUBTYPE_SH7619 49 bool "Support SH7619 processor" 50 select CPU_SH2 51 52comment "SH-2A Processor Support" 53 54config CPU_SUBTYPE_SH7206 55 bool "Support SH7206 processor" 56 select CPU_SH2A 57 58comment "SH-3 Processor Support" 59 60config CPU_SUBTYPE_SH7300 61 bool "Support SH7300 processor" 62 select CPU_SH3 63 64config CPU_SUBTYPE_SH7705 65 bool "Support SH7705 processor" 66 select CPU_SH3 67 select CPU_HAS_PINT_IRQ 68 69config CPU_SUBTYPE_SH7706 70 bool "Support SH7706 processor" 71 select CPU_SH3 72 help 73 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. 74 75config CPU_SUBTYPE_SH7707 76 bool "Support SH7707 processor" 77 select CPU_SH3 78 select CPU_HAS_PINT_IRQ 79 help 80 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. 81 82config CPU_SUBTYPE_SH7708 83 bool "Support SH7708 processor" 84 select CPU_SH3 85 help 86 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or 87 if you have a 100 Mhz SH-3 HD6417708R CPU. 88 89config CPU_SUBTYPE_SH7709 90 bool "Support SH7709 processor" 91 select CPU_SH3 92 select CPU_HAS_PINT_IRQ 93 help 94 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. 95 96config CPU_SUBTYPE_SH7710 97 bool "Support SH7710 processor" 98 select CPU_SH3 99 help 100 Select SH7710 if you have a SH3-DSP SH7710 CPU. 101 102comment "SH-4 Processor Support" 103 104config CPU_SUBTYPE_SH7750 105 bool "Support SH7750 processor" 106 select CPU_SH4 107 select CPU_HAS_IPR_IRQ 108 help 109 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. 110 111config CPU_SUBTYPE_SH7091 112 bool "Support SH7091 processor" 113 select CPU_SH4 114 select CPU_SUBTYPE_SH7750 115 help 116 Select SH7091 if you have an SH-4 based Sega device (such as 117 the Dreamcast, Naomi, and Naomi 2). 118 119config CPU_SUBTYPE_SH7750R 120 bool "Support SH7750R processor" 121 select CPU_SH4 122 select CPU_SUBTYPE_SH7750 123 select CPU_HAS_IPR_IRQ 124 125config CPU_SUBTYPE_SH7750S 126 bool "Support SH7750S processor" 127 select CPU_SH4 128 select CPU_SUBTYPE_SH7750 129 select CPU_HAS_IPR_IRQ 130 131config CPU_SUBTYPE_SH7751 132 bool "Support SH7751 processor" 133 select CPU_SH4 134 select CPU_HAS_IPR_IRQ 135 help 136 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, 137 or if you have a HD6417751R CPU. 138 139config CPU_SUBTYPE_SH7751R 140 bool "Support SH7751R processor" 141 select CPU_SH4 142 select CPU_SUBTYPE_SH7751 143 select CPU_HAS_IPR_IRQ 144 145config CPU_SUBTYPE_SH7760 146 bool "Support SH7760 processor" 147 select CPU_SH4 148 select CPU_HAS_INTC2_IRQ 149 150config CPU_SUBTYPE_SH4_202 151 bool "Support SH4-202 processor" 152 select CPU_SH4 153 154comment "ST40 Processor Support" 155 156config CPU_SUBTYPE_ST40STB1 157 bool "Support ST40STB1/ST40RA processors" 158 select CPU_SUBTYPE_ST40 159 help 160 Select ST40STB1 if you have a ST40RA CPU. 161 This was previously called the ST40STB1, hence the option name. 162 163config CPU_SUBTYPE_ST40GX1 164 bool "Support ST40GX1 processor" 165 select CPU_SUBTYPE_ST40 166 help 167 Select ST40GX1 if you have a ST40GX1 CPU. 168 169comment "SH-4A Processor Support" 170 171config CPU_SUBTYPE_SH7770 172 bool "Support SH7770 processor" 173 select CPU_SH4A 174 175config CPU_SUBTYPE_SH7780 176 bool "Support SH7780 processor" 177 select CPU_SH4A 178 select CPU_HAS_INTC2_IRQ 179 180config CPU_SUBTYPE_SH7785 181 bool "Support SH7785 processor" 182 select CPU_SH4A 183 select CPU_HAS_INTC2_IRQ 184 185comment "SH4AL-DSP Processor Support" 186 187config CPU_SUBTYPE_SH73180 188 bool "Support SH73180 processor" 189 select CPU_SH4AL_DSP 190 191config CPU_SUBTYPE_SH7343 192 bool "Support SH7343 processor" 193 select CPU_SH4AL_DSP 194 195endmenu 196 197menu "Memory management options" 198 199config MMU 200 bool "Support for memory management hardware" 201 depends on !CPU_SH2 202 default y 203 help 204 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 205 boot on these systems, this option must not be set. 206 207 On other systems (such as the SH-3 and 4) where an MMU exists, 208 turning this off will boot the kernel on these machines with the 209 MMU implicitly switched off. 210 211config PAGE_OFFSET 212 hex 213 default "0x80000000" if MMU 214 default "0x00000000" 215 216config MEMORY_START 217 hex "Physical memory start address" 218 default "0x08000000" 219 ---help--- 220 Computers built with Hitachi SuperH processors always 221 map the ROM starting at address zero. But the processor 222 does not specify the range that RAM takes. 223 224 The physical memory (RAM) start address will be automatically 225 set to 08000000. Other platforms, such as the Solution Engine 226 boards typically map RAM at 0C000000. 227 228 Tweak this only when porting to a new machine which does not 229 already have a defconfig. Changing it from the known correct 230 value on any of the known systems will only lead to disaster. 231 232config MEMORY_SIZE 233 hex "Physical memory size" 234 default "0x00400000" 235 help 236 This sets the default memory size assumed by your SH kernel. It can 237 be overridden as normal by the 'mem=' argument on the kernel command 238 line. If unsure, consult your board specifications or just leave it 239 as 0x00400000 which was the default value before this became 240 configurable. 241 242config 32BIT 243 bool "Support 32-bit physical addressing through PMB" 244 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN) 245 default y 246 help 247 If you say Y here, physical addressing will be extended to 248 32-bits through the SH-4A PMB. If this is not set, legacy 249 29-bit physical addressing will be used. 250 251config X2TLB 252 bool "Enable extended TLB mode" 253 depends on CPU_SUBTYPE_SH7785 && MMU && EXPERIMENTAL 254 help 255 Selecting this option will enable the extended mode of the SH-X2 256 TLB. For legacy SH-X behaviour and interoperability, say N. For 257 all of the fun new features and a willingless to submit bug reports, 258 say Y. 259 260config VSYSCALL 261 bool "Support vsyscall page" 262 depends on MMU 263 default y 264 help 265 This will enable support for the kernel mapping a vDSO page 266 in process space, and subsequently handing down the entry point 267 to the libc through the ELF auxiliary vector. 268 269 From the kernel side this is used for the signal trampoline. 270 For systems with an MMU that can afford to give up a page, 271 (the default value) say Y. 272 273choice 274 prompt "Kernel page size" 275 default PAGE_SIZE_4KB 276 277config PAGE_SIZE_4KB 278 bool "4kB" 279 help 280 This is the default page size used by all SuperH CPUs. 281 282config PAGE_SIZE_8KB 283 bool "8kB" 284 depends on EXPERIMENTAL && X2TLB 285 help 286 This enables 8kB pages as supported by SH-X2 and later MMUs. 287 288config PAGE_SIZE_64KB 289 bool "64kB" 290 depends on EXPERIMENTAL && CPU_SH4 291 help 292 This enables support for 64kB pages, possible on all SH-4 293 CPUs and later. Highly experimental, not recommended. 294 295endchoice 296 297choice 298 prompt "HugeTLB page size" 299 depends on HUGETLB_PAGE && CPU_SH4 && MMU 300 default HUGETLB_PAGE_SIZE_64K 301 302config HUGETLB_PAGE_SIZE_64K 303 bool "64kB" 304 305config HUGETLB_PAGE_SIZE_256K 306 bool "256kB" 307 depends on X2TLB 308 309config HUGETLB_PAGE_SIZE_1MB 310 bool "1MB" 311 312config HUGETLB_PAGE_SIZE_4MB 313 bool "4MB" 314 depends on X2TLB 315 316config HUGETLB_PAGE_SIZE_64MB 317 bool "64MB" 318 depends on X2TLB 319 320endchoice 321 322source "mm/Kconfig" 323 324endmenu 325 326menu "Cache configuration" 327 328config SH7705_CACHE_32KB 329 bool "Enable 32KB cache size for SH7705" 330 depends on CPU_SUBTYPE_SH7705 331 default y 332 333config SH_DIRECT_MAPPED 334 bool "Use direct-mapped caching" 335 default n 336 help 337 Selecting this option will configure the caches to be direct-mapped, 338 even if the cache supports a 2 or 4-way mode. This is useful primarily 339 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R, 340 SH4-202, SH4-501, etc.) 341 342 Turn this option off for platforms that do not have a direct-mapped 343 cache, and you have no need to run the caches in such a configuration. 344 345config SH_WRITETHROUGH 346 bool "Use write-through caching" 347 help 348 Selecting this option will configure the caches in write-through 349 mode, as opposed to the default write-back configuration. 350 351 Since there's sill some aliasing issues on SH-4, this option will 352 unfortunately still require the majority of flushing functions to 353 be implemented to deal with aliasing. 354 355 If unsure, say N. 356 357config SH_OCRAM 358 bool "Operand Cache RAM (OCRAM) support" 359 help 360 Selecting this option will automatically tear down the number of 361 sets in the dcache by half, which in turn exposes a memory range. 362 363 The addresses for the OC RAM base will vary according to the 364 processor version. Consult vendor documentation for specifics. 365 366 If unsure, say N. 367 368endmenu 369