1# SPDX-License-Identifier: GPL-2.0 2menu "Memory management options" 3 4config QUICKLIST 5 def_bool y 6 7config MMU 8 bool "Support for memory management hardware" 9 depends on !CPU_SH2 10 default y 11 help 12 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 13 boot on these systems, this option must not be set. 14 15 On other systems (such as the SH-3 and 4) where an MMU exists, 16 turning this off will boot the kernel on these machines with the 17 MMU implicitly switched off. 18 19config PAGE_OFFSET 20 hex 21 default "0x80000000" if MMU && SUPERH32 22 default "0x20000000" if MMU && SUPERH64 23 default "0x00000000" 24 25config FORCE_MAX_ZONEORDER 26 int "Maximum zone order" 27 range 9 64 if PAGE_SIZE_16KB 28 default "9" if PAGE_SIZE_16KB 29 range 7 64 if PAGE_SIZE_64KB 30 default "7" if PAGE_SIZE_64KB 31 range 11 64 32 default "14" if !MMU 33 default "11" 34 help 35 The kernel memory allocator divides physically contiguous memory 36 blocks into "zones", where each zone is a power of two number of 37 pages. This option selects the largest power of two that the kernel 38 keeps in the memory allocator. If you need to allocate very large 39 blocks of physically contiguous memory, then you may need to 40 increase this value. 41 42 This config option is actually maximum order plus one. For example, 43 a value of 11 means that the largest free memory block is 2^10 pages. 44 45 The page size is not necessarily 4KB. Keep this in mind when 46 choosing a value for this option. 47 48config MEMORY_START 49 hex "Physical memory start address" 50 default "0x08000000" 51 ---help--- 52 Computers built with Hitachi SuperH processors always 53 map the ROM starting at address zero. But the processor 54 does not specify the range that RAM takes. 55 56 The physical memory (RAM) start address will be automatically 57 set to 08000000. Other platforms, such as the Solution Engine 58 boards typically map RAM at 0C000000. 59 60 Tweak this only when porting to a new machine which does not 61 already have a defconfig. Changing it from the known correct 62 value on any of the known systems will only lead to disaster. 63 64config MEMORY_SIZE 65 hex "Physical memory size" 66 default "0x04000000" 67 help 68 This sets the default memory size assumed by your SH kernel. It can 69 be overridden as normal by the 'mem=' argument on the kernel command 70 line. If unsure, consult your board specifications or just leave it 71 as 0x04000000 which was the default value before this became 72 configurable. 73 74# Physical addressing modes 75 76config 29BIT 77 def_bool !32BIT 78 depends on SUPERH32 79 select UNCACHED_MAPPING 80 81config 32BIT 82 bool 83 default y if CPU_SH5 || !MMU 84 85config PMB 86 bool "Support 32-bit physical addressing through PMB" 87 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP 88 select 32BIT 89 select UNCACHED_MAPPING 90 help 91 If you say Y here, physical addressing will be extended to 92 32-bits through the SH-4A PMB. If this is not set, legacy 93 29-bit physical addressing will be used. 94 95config X2TLB 96 def_bool y 97 depends on (CPU_SHX2 || CPU_SHX3) && MMU 98 99config VSYSCALL 100 bool "Support vsyscall page" 101 depends on MMU && (CPU_SH3 || CPU_SH4) 102 default y 103 help 104 This will enable support for the kernel mapping a vDSO page 105 in process space, and subsequently handing down the entry point 106 to the libc through the ELF auxiliary vector. 107 108 From the kernel side this is used for the signal trampoline. 109 For systems with an MMU that can afford to give up a page, 110 (the default value) say Y. 111 112config NUMA 113 bool "Non Uniform Memory Access (NUMA) Support" 114 depends on MMU && SYS_SUPPORTS_NUMA 115 select ARCH_WANT_NUMA_VARIABLE_LOCALITY 116 default n 117 help 118 Some SH systems have many various memories scattered around 119 the address space, each with varying latencies. This enables 120 support for these blocks by binding them to nodes and allowing 121 memory policies to be used for prioritizing and controlling 122 allocation behaviour. 123 124config NODES_SHIFT 125 int 126 default "3" if CPU_SUBTYPE_SHX3 127 default "1" 128 depends on NEED_MULTIPLE_NODES 129 130config ARCH_FLATMEM_ENABLE 131 def_bool y 132 depends on !NUMA 133 134config ARCH_SPARSEMEM_ENABLE 135 def_bool y 136 select SPARSEMEM_STATIC 137 138config ARCH_SPARSEMEM_DEFAULT 139 def_bool y 140 141config ARCH_SELECT_MEMORY_MODEL 142 def_bool y 143 144config ARCH_ENABLE_MEMORY_HOTPLUG 145 def_bool y 146 depends on SPARSEMEM && MMU 147 148config ARCH_ENABLE_MEMORY_HOTREMOVE 149 def_bool y 150 depends on SPARSEMEM && MMU 151 152config ARCH_MEMORY_PROBE 153 def_bool y 154 depends on MEMORY_HOTPLUG 155 156config IOREMAP_FIXED 157 def_bool y 158 depends on X2TLB || SUPERH64 159 160config UNCACHED_MAPPING 161 bool 162 163config HAVE_SRAM_POOL 164 bool 165 select GENERIC_ALLOCATOR 166 167choice 168 prompt "Kernel page size" 169 default PAGE_SIZE_4KB 170 171config PAGE_SIZE_4KB 172 bool "4kB" 173 help 174 This is the default page size used by all SuperH CPUs. 175 176config PAGE_SIZE_8KB 177 bool "8kB" 178 depends on !MMU || X2TLB 179 help 180 This enables 8kB pages as supported by SH-X2 and later MMUs. 181 182config PAGE_SIZE_16KB 183 bool "16kB" 184 depends on !MMU 185 help 186 This enables 16kB pages on MMU-less SH systems. 187 188config PAGE_SIZE_64KB 189 bool "64kB" 190 depends on !MMU || CPU_SH4 || CPU_SH5 191 help 192 This enables support for 64kB pages, possible on all SH-4 193 CPUs and later. 194 195endchoice 196 197choice 198 prompt "HugeTLB page size" 199 depends on HUGETLB_PAGE 200 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB 201 default HUGETLB_PAGE_SIZE_64K 202 203config HUGETLB_PAGE_SIZE_64K 204 bool "64kB" 205 depends on !PAGE_SIZE_64KB 206 207config HUGETLB_PAGE_SIZE_256K 208 bool "256kB" 209 depends on X2TLB 210 211config HUGETLB_PAGE_SIZE_1MB 212 bool "1MB" 213 214config HUGETLB_PAGE_SIZE_4MB 215 bool "4MB" 216 depends on X2TLB 217 218config HUGETLB_PAGE_SIZE_64MB 219 bool "64MB" 220 depends on X2TLB 221 222config HUGETLB_PAGE_SIZE_512MB 223 bool "512MB" 224 depends on CPU_SH5 225 226endchoice 227 228config SCHED_MC 229 bool "Multi-core scheduler support" 230 depends on SMP 231 default y 232 help 233 Multi-core scheduler support improves the CPU scheduler's decision 234 making when dealing with multi-core CPU chips at a cost of slightly 235 increased overhead in some places. If unsure say N here. 236 237endmenu 238 239menu "Cache configuration" 240 241config SH7705_CACHE_32KB 242 bool "Enable 32KB cache size for SH7705" 243 depends on CPU_SUBTYPE_SH7705 244 default y 245 246choice 247 prompt "Cache mode" 248 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 249 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) 250 251config CACHE_WRITEBACK 252 bool "Write-back" 253 254config CACHE_WRITETHROUGH 255 bool "Write-through" 256 help 257 Selecting this option will configure the caches in write-through 258 mode, as opposed to the default write-back configuration. 259 260 Since there's sill some aliasing issues on SH-4, this option will 261 unfortunately still require the majority of flushing functions to 262 be implemented to deal with aliasing. 263 264 If unsure, say N. 265 266config CACHE_OFF 267 bool "Off" 268 269endchoice 270 271endmenu 272