1# SPDX-License-Identifier: GPL-2.0 2menu "Memory management options" 3 4config MMU 5 bool "Support for memory management hardware" 6 depends on !CPU_SH2 7 select HAVE_PAGE_SIZE_4KB 8 select HAVE_PAGE_SIZE_8KB if X2TLB 9 select HAVE_PAGE_SIZE_64KB if CPU_SH4 10 default y 11 help 12 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 13 boot on these systems, this option must not be set. 14 15 On other systems (such as the SH-3 and 4) where an MMU exists, 16 turning this off will boot the kernel on these machines with the 17 MMU implicitly switched off. 18 19config NOMMU 20 def_bool !MMU 21 select HAVE_PAGE_SIZE_4KB 22 select HAVE_PAGE_SIZE_8KB 23 select HAVE_PAGE_SIZE_16KB 24 select HAVE_PAGE_SIZE_64KB 25 help 26 On MMU-less systems, any of these page sizes can be selected 27 28config PAGE_OFFSET 29 hex 30 default "0x80000000" if MMU 31 default "0x00000000" 32 33config ARCH_FORCE_MAX_ORDER 34 int "Order of maximal physically contiguous allocations" 35 default "8" if PAGE_SIZE_16KB 36 default "6" if PAGE_SIZE_64KB 37 default "13" if !MMU 38 default "10" 39 help 40 The kernel page allocator limits the size of maximal physically 41 contiguous allocations. The limit is called MAX_PAGE:_ORDER and it 42 defines the maximal power of two of number of pages that can be 43 allocated as a single contiguous block. This option allows 44 overriding the default setting when ability to allocate very 45 large blocks of physically contiguous memory is required. 46 47 The page size is not necessarily 4KB. Keep this in mind when 48 choosing a value for this option. 49 50 Don't change if unsure. 51 52config MEMORY_START 53 hex "Physical memory start address" 54 default "0x08000000" 55 help 56 Computers built with Hitachi SuperH processors always 57 map the ROM starting at address zero. But the processor 58 does not specify the range that RAM takes. 59 60 The physical memory (RAM) start address will be automatically 61 set to 08000000. Other platforms, such as the Solution Engine 62 boards typically map RAM at 0C000000. 63 64 Tweak this only when porting to a new machine which does not 65 already have a defconfig. Changing it from the known correct 66 value on any of the known systems will only lead to disaster. 67 68config MEMORY_SIZE 69 hex "Physical memory size" 70 default "0x04000000" 71 help 72 This sets the default memory size assumed by your SH kernel. It can 73 be overridden as normal by the 'mem=' argument on the kernel command 74 line. If unsure, consult your board specifications or just leave it 75 as 0x04000000 which was the default value before this became 76 configurable. 77 78# Physical addressing modes 79 80config 29BIT 81 def_bool !32BIT 82 select UNCACHED_MAPPING 83 84config 32BIT 85 bool 86 default !MMU 87 88config PMB 89 bool "Support 32-bit physical addressing through PMB" 90 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP 91 select 32BIT 92 select UNCACHED_MAPPING 93 help 94 If you say Y here, physical addressing will be extended to 95 32-bits through the SH-4A PMB. If this is not set, legacy 96 29-bit physical addressing will be used. 97 98config X2TLB 99 def_bool y 100 depends on (CPU_SHX2 || CPU_SHX3) && MMU 101 102config VSYSCALL 103 bool "Support vsyscall page" 104 depends on MMU && (CPU_SH3 || CPU_SH4) 105 default y 106 help 107 This will enable support for the kernel mapping a vDSO page 108 in process space, and subsequently handing down the entry point 109 to the libc through the ELF auxiliary vector. 110 111 From the kernel side this is used for the signal trampoline. 112 For systems with an MMU that can afford to give up a page, 113 (the default value) say Y. 114 115config NUMA 116 bool "Non-Uniform Memory Access (NUMA) Support" 117 depends on MMU && SYS_SUPPORTS_NUMA 118 select ARCH_WANT_NUMA_VARIABLE_LOCALITY 119 default n 120 help 121 Some SH systems have many various memories scattered around 122 the address space, each with varying latencies. This enables 123 support for these blocks by binding them to nodes and allowing 124 memory policies to be used for prioritizing and controlling 125 allocation behaviour. 126 127config NODES_SHIFT 128 int 129 default "3" if CPU_SUBTYPE_SHX3 130 default "1" 131 depends on NUMA 132 133config ARCH_FLATMEM_ENABLE 134 def_bool y 135 depends on !NUMA 136 137config ARCH_SPARSEMEM_ENABLE 138 def_bool y 139 select SPARSEMEM_STATIC 140 141config ARCH_SPARSEMEM_DEFAULT 142 def_bool y 143 144config ARCH_SELECT_MEMORY_MODEL 145 def_bool y 146 147config IOREMAP_FIXED 148 def_bool y 149 depends on X2TLB 150 151config UNCACHED_MAPPING 152 bool 153 154config HAVE_SRAM_POOL 155 bool 156 select GENERIC_ALLOCATOR 157 158choice 159 prompt "HugeTLB page size" 160 depends on HUGETLB_PAGE 161 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB 162 default HUGETLB_PAGE_SIZE_64K 163 164config HUGETLB_PAGE_SIZE_64K 165 bool "64kB" 166 depends on !PAGE_SIZE_64KB 167 168config HUGETLB_PAGE_SIZE_256K 169 bool "256kB" 170 depends on X2TLB 171 172config HUGETLB_PAGE_SIZE_1MB 173 bool "1MB" 174 175config HUGETLB_PAGE_SIZE_4MB 176 bool "4MB" 177 depends on X2TLB 178 179config HUGETLB_PAGE_SIZE_64MB 180 bool "64MB" 181 depends on X2TLB 182 183endchoice 184 185config SCHED_MC 186 bool "Multi-core scheduler support" 187 depends on SMP 188 default y 189 help 190 Multi-core scheduler support improves the CPU scheduler's decision 191 making when dealing with multi-core CPU chips at a cost of slightly 192 increased overhead in some places. If unsure say N here. 193 194endmenu 195 196menu "Cache configuration" 197 198config SH7705_CACHE_32KB 199 bool "Enable 32KB cache size for SH7705" 200 depends on CPU_SUBTYPE_SH7705 201 default y 202 203choice 204 prompt "Cache mode" 205 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 206 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) 207 208config CACHE_WRITEBACK 209 bool "Write-back" 210 211config CACHE_WRITETHROUGH 212 bool "Write-through" 213 help 214 Selecting this option will configure the caches in write-through 215 mode, as opposed to the default write-back configuration. 216 217 Since there's sill some aliasing issues on SH-4, this option will 218 unfortunately still require the majority of flushing functions to 219 be implemented to deal with aliasing. 220 221 If unsure, say N. 222 223config CACHE_OFF 224 bool "Off" 225 226endchoice 227 228endmenu 229