xref: /linux/arch/sh/mm/Kconfig (revision 1a442fe02d205d6980202b07f799ab9336e72ad7)
1#
2# Processor families
3#
4config CPU_SH2
5	bool
6
7config CPU_SH2A
8	bool
9	select CPU_SH2
10
11config CPU_SH3
12	bool
13	select CPU_HAS_INTEVT
14	select CPU_HAS_SR_RB
15
16config CPU_SH4
17	bool
18	select CPU_HAS_INTEVT
19	select CPU_HAS_SR_RB
20	select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
21	select CPU_HAS_FPU if !CPU_SH4AL_DSP
22
23config CPU_SH4A
24	bool
25	select CPU_SH4
26
27config CPU_SH4AL_DSP
28	bool
29	select CPU_SH4A
30	select CPU_HAS_DSP
31
32config CPU_SUBTYPE_ST40
33	bool
34	select CPU_SH4
35
36config CPU_SHX2
37	bool
38
39config CPU_SHX3
40	bool
41
42choice
43	prompt "Processor sub-type selection"
44
45#
46# Processor subtypes
47#
48
49# SH-2 Processor Support
50
51config CPU_SUBTYPE_SH7619
52	bool "Support SH7619 processor"
53	select CPU_SH2
54
55# SH-2A Processor Support
56
57config CPU_SUBTYPE_SH7206
58	bool "Support SH7206 processor"
59	select CPU_SH2A
60
61# SH-3 Processor Support
62
63config CPU_SUBTYPE_SH7705
64	bool "Support SH7705 processor"
65	select CPU_SH3
66
67config CPU_SUBTYPE_SH7706
68	bool "Support SH7706 processor"
69	select CPU_SH3
70	help
71	  Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
72
73config CPU_SUBTYPE_SH7707
74	bool "Support SH7707 processor"
75	select CPU_SH3
76	help
77	  Select SH7707 if you have a  60 Mhz SH-3 HD6417707 CPU.
78
79config CPU_SUBTYPE_SH7708
80	bool "Support SH7708 processor"
81	select CPU_SH3
82	help
83	  Select SH7708 if you have a  60 Mhz SH-3 HD6417708S or
84	  if you have a 100 Mhz SH-3 HD6417708R CPU.
85
86config CPU_SUBTYPE_SH7709
87	bool "Support SH7709 processor"
88	select CPU_SH3
89	help
90	  Select SH7709 if you have a  80 Mhz SH-3 HD6417709 CPU.
91
92config CPU_SUBTYPE_SH7710
93	bool "Support SH7710 processor"
94	select CPU_SH3
95	select CPU_HAS_DSP
96	help
97	  Select SH7710 if you have a SH3-DSP SH7710 CPU.
98
99config CPU_SUBTYPE_SH7712
100	bool "Support SH7712 processor"
101	select CPU_SH3
102	select CPU_HAS_DSP
103	help
104	  Select SH7712 if you have a SH3-DSP SH7712 CPU.
105
106config CPU_SUBTYPE_SH7720
107	bool "Support SH7720 processor"
108	select CPU_SH3
109	select CPU_HAS_DSP
110	help
111	  Select SH7720 if you have a SH3-DSP SH7720 CPU.
112
113# SH-4 Processor Support
114
115config CPU_SUBTYPE_SH7750
116	bool "Support SH7750 processor"
117	select CPU_SH4
118	help
119	  Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
120
121config CPU_SUBTYPE_SH7091
122	bool "Support SH7091 processor"
123	select CPU_SH4
124	help
125	  Select SH7091 if you have an SH-4 based Sega device (such as
126	  the Dreamcast, Naomi, and Naomi 2).
127
128config CPU_SUBTYPE_SH7750R
129	bool "Support SH7750R processor"
130	select CPU_SH4
131
132config CPU_SUBTYPE_SH7750S
133	bool "Support SH7750S processor"
134	select CPU_SH4
135
136config CPU_SUBTYPE_SH7751
137	bool "Support SH7751 processor"
138	select CPU_SH4
139	help
140	  Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
141	  or if you have a HD6417751R CPU.
142
143config CPU_SUBTYPE_SH7751R
144	bool "Support SH7751R processor"
145	select CPU_SH4
146
147config CPU_SUBTYPE_SH7760
148	bool "Support SH7760 processor"
149	select CPU_SH4
150
151config CPU_SUBTYPE_SH4_202
152	bool "Support SH4-202 processor"
153	select CPU_SH4
154
155# ST40 Processor Support
156
157config CPU_SUBTYPE_ST40STB1
158	bool "Support ST40STB1/ST40RA processors"
159	select CPU_SUBTYPE_ST40
160	help
161	  Select ST40STB1 if you have a ST40RA CPU.
162	  This was previously called the ST40STB1, hence the option name.
163
164config CPU_SUBTYPE_ST40GX1
165	bool "Support ST40GX1 processor"
166	select CPU_SUBTYPE_ST40
167	help
168	  Select ST40GX1 if you have a ST40GX1 CPU.
169
170# SH-4A Processor Support
171
172config CPU_SUBTYPE_SH7770
173	bool "Support SH7770 processor"
174	select CPU_SH4A
175
176config CPU_SUBTYPE_SH7780
177	bool "Support SH7780 processor"
178	select CPU_SH4A
179
180config CPU_SUBTYPE_SH7785
181	bool "Support SH7785 processor"
182	select CPU_SH4A
183	select CPU_SHX2
184	select ARCH_SPARSEMEM_ENABLE
185	select SYS_SUPPORTS_NUMA
186
187config CPU_SUBTYPE_SHX3
188	bool "Support SH-X3 processor"
189	select CPU_SH4A
190	select CPU_SHX3
191	select ARCH_SPARSEMEM_ENABLE
192	select SYS_SUPPORTS_NUMA
193	select SYS_SUPPORTS_SMP
194
195# SH4AL-DSP Processor Support
196
197config CPU_SUBTYPE_SH7343
198	bool "Support SH7343 processor"
199	select CPU_SH4AL_DSP
200
201config CPU_SUBTYPE_SH7722
202	bool "Support SH7722 processor"
203	select CPU_SH4AL_DSP
204	select CPU_SHX2
205	select ARCH_SPARSEMEM_ENABLE
206	select SYS_SUPPORTS_NUMA
207
208endchoice
209
210menu "Memory management options"
211
212config QUICKLIST
213	def_bool y
214
215config MMU
216        bool "Support for memory management hardware"
217	depends on !CPU_SH2
218	default y
219	help
220	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
221	  boot on these systems, this option must not be set.
222
223	  On other systems (such as the SH-3 and 4) where an MMU exists,
224	  turning this off will boot the kernel on these machines with the
225	  MMU implicitly switched off.
226
227config PAGE_OFFSET
228	hex
229	default "0x80000000" if MMU
230	default "0x00000000"
231
232config MEMORY_START
233	hex "Physical memory start address"
234	default "0x08000000"
235	---help---
236	  Computers built with Hitachi SuperH processors always
237	  map the ROM starting at address zero.  But the processor
238	  does not specify the range that RAM takes.
239
240	  The physical memory (RAM) start address will be automatically
241	  set to 08000000. Other platforms, such as the Solution Engine
242	  boards typically map RAM at 0C000000.
243
244	  Tweak this only when porting to a new machine which does not
245	  already have a defconfig. Changing it from the known correct
246	  value on any of the known systems will only lead to disaster.
247
248config MEMORY_SIZE
249	hex "Physical memory size"
250	default "0x00400000"
251	help
252	  This sets the default memory size assumed by your SH kernel. It can
253	  be overridden as normal by the 'mem=' argument on the kernel command
254	  line. If unsure, consult your board specifications or just leave it
255	  as 0x00400000 which was the default value before this became
256	  configurable.
257
258config 32BIT
259	bool "Support 32-bit physical addressing through PMB"
260	depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
261	default y
262	help
263	  If you say Y here, physical addressing will be extended to
264	  32-bits through the SH-4A PMB. If this is not set, legacy
265	  29-bit physical addressing will be used.
266
267config X2TLB
268	bool "Enable extended TLB mode"
269	depends on CPU_SHX2 && MMU && EXPERIMENTAL
270	help
271	  Selecting this option will enable the extended mode of the SH-X2
272	  TLB. For legacy SH-X behaviour and interoperability, say N. For
273	  all of the fun new features and a willingless to submit bug reports,
274	  say Y.
275
276config VSYSCALL
277	bool "Support vsyscall page"
278	depends on MMU
279	default y
280	help
281	  This will enable support for the kernel mapping a vDSO page
282	  in process space, and subsequently handing down the entry point
283	  to the libc through the ELF auxiliary vector.
284
285	  From the kernel side this is used for the signal trampoline.
286	  For systems with an MMU that can afford to give up a page,
287	  (the default value) say Y.
288
289config NUMA
290	bool "Non Uniform Memory Access (NUMA) Support"
291	depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
292	default n
293	help
294	  Some SH systems have many various memories scattered around
295	  the address space, each with varying latencies. This enables
296	  support for these blocks by binding them to nodes and allowing
297	  memory policies to be used for prioritizing and controlling
298	  allocation behaviour.
299
300config NODES_SHIFT
301	int
302	default "3" if CPU_SUBTYPE_SHX3
303	default "1"
304	depends on NEED_MULTIPLE_NODES
305
306config ARCH_FLATMEM_ENABLE
307	def_bool y
308	depends on !NUMA
309
310config ARCH_SPARSEMEM_ENABLE
311	def_bool y
312	select SPARSEMEM_STATIC
313
314config ARCH_SPARSEMEM_DEFAULT
315	def_bool y
316
317config MAX_ACTIVE_REGIONS
318	int
319	default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
320	default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
321	default "1"
322
323config ARCH_POPULATES_NODE_MAP
324	def_bool y
325
326config ARCH_SELECT_MEMORY_MODEL
327	def_bool y
328
329config ARCH_ENABLE_MEMORY_HOTPLUG
330	def_bool y
331	depends on SPARSEMEM
332
333config ARCH_MEMORY_PROBE
334	def_bool y
335	depends on MEMORY_HOTPLUG
336
337choice
338	prompt "Kernel page size"
339	default PAGE_SIZE_4KB
340
341config PAGE_SIZE_4KB
342	bool "4kB"
343	help
344	  This is the default page size used by all SuperH CPUs.
345
346config PAGE_SIZE_8KB
347	bool "8kB"
348	depends on EXPERIMENTAL && X2TLB
349	help
350	  This enables 8kB pages as supported by SH-X2 and later MMUs.
351
352config PAGE_SIZE_64KB
353	bool "64kB"
354	depends on EXPERIMENTAL && CPU_SH4
355	help
356	  This enables support for 64kB pages, possible on all SH-4
357	  CPUs and later. Highly experimental, not recommended.
358
359endchoice
360
361choice
362	prompt "HugeTLB page size"
363	depends on HUGETLB_PAGE && CPU_SH4 && MMU
364	default HUGETLB_PAGE_SIZE_64K
365
366config HUGETLB_PAGE_SIZE_64K
367	bool "64kB"
368
369config HUGETLB_PAGE_SIZE_256K
370	bool "256kB"
371	depends on X2TLB
372
373config HUGETLB_PAGE_SIZE_1MB
374	bool "1MB"
375
376config HUGETLB_PAGE_SIZE_4MB
377	bool "4MB"
378	depends on X2TLB
379
380config HUGETLB_PAGE_SIZE_64MB
381	bool "64MB"
382	depends on X2TLB
383
384endchoice
385
386source "mm/Kconfig"
387
388endmenu
389
390menu "Cache configuration"
391
392config SH7705_CACHE_32KB
393	bool "Enable 32KB cache size for SH7705"
394	depends on CPU_SUBTYPE_SH7705
395	default y
396
397config SH_DIRECT_MAPPED
398	bool "Use direct-mapped caching"
399	default n
400	help
401	  Selecting this option will configure the caches to be direct-mapped,
402	  even if the cache supports a 2 or 4-way mode. This is useful primarily
403	  for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
404	  SH4-202, SH4-501, etc.)
405
406	  Turn this option off for platforms that do not have a direct-mapped
407	  cache, and you have no need to run the caches in such a configuration.
408
409choice
410	prompt "Cache mode"
411	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
412	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
413
414config CACHE_WRITEBACK
415	bool "Write-back"
416	depends on CPU_SH2A || CPU_SH3 || CPU_SH4
417
418config CACHE_WRITETHROUGH
419	bool "Write-through"
420	help
421	  Selecting this option will configure the caches in write-through
422	  mode, as opposed to the default write-back configuration.
423
424	  Since there's sill some aliasing issues on SH-4, this option will
425	  unfortunately still require the majority of flushing functions to
426	  be implemented to deal with aliasing.
427
428	  If unsure, say N.
429
430config CACHE_OFF
431	bool "Off"
432
433endchoice
434
435endmenu
436