1menu "Memory management options" 2 3config QUICKLIST 4 def_bool y 5 6config MMU 7 bool "Support for memory management hardware" 8 depends on !CPU_SH2 9 default y 10 help 11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 12 boot on these systems, this option must not be set. 13 14 On other systems (such as the SH-3 and 4) where an MMU exists, 15 turning this off will boot the kernel on these machines with the 16 MMU implicitly switched off. 17 18config PAGE_OFFSET 19 hex 20 default "0x80000000" if MMU && SUPERH32 21 default "0x20000000" if MMU && SUPERH64 22 default "0x00000000" 23 24config FORCE_MAX_ZONEORDER 25 int "Maximum zone order" 26 range 9 64 if PAGE_SIZE_16KB 27 default "9" if PAGE_SIZE_16KB 28 range 7 64 if PAGE_SIZE_64KB 29 default "7" if PAGE_SIZE_64KB 30 range 11 64 31 default "14" if !MMU 32 default "11" 33 help 34 The kernel memory allocator divides physically contiguous memory 35 blocks into "zones", where each zone is a power of two number of 36 pages. This option selects the largest power of two that the kernel 37 keeps in the memory allocator. If you need to allocate very large 38 blocks of physically contiguous memory, then you may need to 39 increase this value. 40 41 This config option is actually maximum order plus one. For example, 42 a value of 11 means that the largest free memory block is 2^10 pages. 43 44 The page size is not necessarily 4KB. Keep this in mind when 45 choosing a value for this option. 46 47config MEMORY_START 48 hex "Physical memory start address" 49 default "0x08000000" 50 ---help--- 51 Computers built with Hitachi SuperH processors always 52 map the ROM starting at address zero. But the processor 53 does not specify the range that RAM takes. 54 55 The physical memory (RAM) start address will be automatically 56 set to 08000000. Other platforms, such as the Solution Engine 57 boards typically map RAM at 0C000000. 58 59 Tweak this only when porting to a new machine which does not 60 already have a defconfig. Changing it from the known correct 61 value on any of the known systems will only lead to disaster. 62 63config MEMORY_SIZE 64 hex "Physical memory size" 65 default "0x04000000" 66 help 67 This sets the default memory size assumed by your SH kernel. It can 68 be overridden as normal by the 'mem=' argument on the kernel command 69 line. If unsure, consult your board specifications or just leave it 70 as 0x04000000 which was the default value before this became 71 configurable. 72 73# Physical addressing modes 74 75config 29BIT 76 def_bool !32BIT 77 depends on SUPERH32 78 select UNCACHED_MAPPING 79 80config 32BIT 81 bool 82 default y if CPU_SH5 || !MMU 83 84config PMB 85 bool "Support 32-bit physical addressing through PMB" 86 depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP 87 select 32BIT 88 select UNCACHED_MAPPING 89 help 90 If you say Y here, physical addressing will be extended to 91 32-bits through the SH-4A PMB. If this is not set, legacy 92 29-bit physical addressing will be used. 93 94config X2TLB 95 def_bool y 96 depends on (CPU_SHX2 || CPU_SHX3) && MMU 97 98config VSYSCALL 99 bool "Support vsyscall page" 100 depends on MMU && (CPU_SH3 || CPU_SH4) 101 default y 102 help 103 This will enable support for the kernel mapping a vDSO page 104 in process space, and subsequently handing down the entry point 105 to the libc through the ELF auxiliary vector. 106 107 From the kernel side this is used for the signal trampoline. 108 For systems with an MMU that can afford to give up a page, 109 (the default value) say Y. 110 111config NUMA 112 bool "Non Uniform Memory Access (NUMA) Support" 113 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL 114 select ARCH_WANT_NUMA_VARIABLE_LOCALITY 115 default n 116 help 117 Some SH systems have many various memories scattered around 118 the address space, each with varying latencies. This enables 119 support for these blocks by binding them to nodes and allowing 120 memory policies to be used for prioritizing and controlling 121 allocation behaviour. 122 123config NODES_SHIFT 124 int 125 default "3" if CPU_SUBTYPE_SHX3 126 default "1" 127 depends on NEED_MULTIPLE_NODES 128 129config ARCH_FLATMEM_ENABLE 130 def_bool y 131 depends on !NUMA 132 133config ARCH_SPARSEMEM_ENABLE 134 def_bool y 135 select SPARSEMEM_STATIC 136 137config ARCH_SPARSEMEM_DEFAULT 138 def_bool y 139 140config MAX_ACTIVE_REGIONS 141 int 142 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM) 143 default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \ 144 CPU_SUBTYPE_SH7785) 145 default "1" 146 147config ARCH_SELECT_MEMORY_MODEL 148 def_bool y 149 150config ARCH_ENABLE_MEMORY_HOTPLUG 151 def_bool y 152 depends on SPARSEMEM && MMU 153 154config ARCH_ENABLE_MEMORY_HOTREMOVE 155 def_bool y 156 depends on SPARSEMEM && MMU 157 158config ARCH_MEMORY_PROBE 159 def_bool y 160 depends on MEMORY_HOTPLUG 161 162config IOREMAP_FIXED 163 def_bool y 164 depends on X2TLB || SUPERH64 165 166config UNCACHED_MAPPING 167 bool 168 169config HAVE_SRAM_POOL 170 bool 171 select GENERIC_ALLOCATOR 172 173choice 174 prompt "Kernel page size" 175 default PAGE_SIZE_4KB 176 177config PAGE_SIZE_4KB 178 bool "4kB" 179 help 180 This is the default page size used by all SuperH CPUs. 181 182config PAGE_SIZE_8KB 183 bool "8kB" 184 depends on !MMU || X2TLB 185 help 186 This enables 8kB pages as supported by SH-X2 and later MMUs. 187 188config PAGE_SIZE_16KB 189 bool "16kB" 190 depends on !MMU 191 help 192 This enables 16kB pages on MMU-less SH systems. 193 194config PAGE_SIZE_64KB 195 bool "64kB" 196 depends on !MMU || CPU_SH4 || CPU_SH5 197 help 198 This enables support for 64kB pages, possible on all SH-4 199 CPUs and later. 200 201endchoice 202 203choice 204 prompt "HugeTLB page size" 205 depends on HUGETLB_PAGE 206 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB 207 default HUGETLB_PAGE_SIZE_64K 208 209config HUGETLB_PAGE_SIZE_64K 210 bool "64kB" 211 depends on !PAGE_SIZE_64KB 212 213config HUGETLB_PAGE_SIZE_256K 214 bool "256kB" 215 depends on X2TLB 216 217config HUGETLB_PAGE_SIZE_1MB 218 bool "1MB" 219 220config HUGETLB_PAGE_SIZE_4MB 221 bool "4MB" 222 depends on X2TLB 223 224config HUGETLB_PAGE_SIZE_64MB 225 bool "64MB" 226 depends on X2TLB 227 228config HUGETLB_PAGE_SIZE_512MB 229 bool "512MB" 230 depends on CPU_SH5 231 232endchoice 233 234source "mm/Kconfig" 235 236config SCHED_MC 237 bool "Multi-core scheduler support" 238 depends on SMP 239 default y 240 help 241 Multi-core scheduler support improves the CPU scheduler's decision 242 making when dealing with multi-core CPU chips at a cost of slightly 243 increased overhead in some places. If unsure say N here. 244 245endmenu 246 247menu "Cache configuration" 248 249config SH7705_CACHE_32KB 250 bool "Enable 32KB cache size for SH7705" 251 depends on CPU_SUBTYPE_SH7705 252 default y 253 254choice 255 prompt "Cache mode" 256 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 257 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) 258 259config CACHE_WRITEBACK 260 bool "Write-back" 261 262config CACHE_WRITETHROUGH 263 bool "Write-through" 264 help 265 Selecting this option will configure the caches in write-through 266 mode, as opposed to the default write-back configuration. 267 268 Since there's sill some aliasing issues on SH-4, this option will 269 unfortunately still require the majority of flushing functions to 270 be implemented to deal with aliasing. 271 272 If unsure, say N. 273 274config CACHE_OFF 275 bool "Off" 276 277endchoice 278 279endmenu 280