1# 2# Processor families 3# 4config CPU_SH2 5 select SH_WRITETHROUGH if !CPU_SH2A 6 bool 7 8config CPU_SH2A 9 bool 10 select CPU_SH2 11 12config CPU_SH3 13 bool 14 select CPU_HAS_INTEVT 15 select CPU_HAS_SR_RB 16 17config CPU_SH4 18 bool 19 select CPU_HAS_INTEVT 20 select CPU_HAS_SR_RB 21 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2 22 23config CPU_SH4A 24 bool 25 select CPU_SH4 26 27config CPU_SH4AL_DSP 28 bool 29 select CPU_SH4A 30 31config CPU_SUBTYPE_ST40 32 bool 33 select CPU_SH4 34 select CPU_HAS_INTC2_IRQ 35 36config CPU_SHX2 37 bool 38 39choice 40 prompt "Processor sub-type selection" 41 42# 43# Processor subtypes 44# 45 46# SH-2 Processor Support 47 48config CPU_SUBTYPE_SH7604 49 bool "Support SH7604 processor" 50 select CPU_SH2 51 52config CPU_SUBTYPE_SH7619 53 bool "Support SH7619 processor" 54 select CPU_SH2 55 56# SH-2A Processor Support 57 58config CPU_SUBTYPE_SH7206 59 bool "Support SH7206 processor" 60 select CPU_SH2A 61 62# SH-3 Processor Support 63 64config CPU_SUBTYPE_SH7300 65 bool "Support SH7300 processor" 66 select CPU_SH3 67 68config CPU_SUBTYPE_SH7705 69 bool "Support SH7705 processor" 70 select CPU_SH3 71 select CPU_HAS_IPR_IRQ 72 select CPU_HAS_PINT_IRQ 73 74config CPU_SUBTYPE_SH7706 75 bool "Support SH7706 processor" 76 select CPU_SH3 77 select CPU_HAS_IPR_IRQ 78 help 79 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. 80 81config CPU_SUBTYPE_SH7707 82 bool "Support SH7707 processor" 83 select CPU_SH3 84 select CPU_HAS_PINT_IRQ 85 help 86 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. 87 88config CPU_SUBTYPE_SH7708 89 bool "Support SH7708 processor" 90 select CPU_SH3 91 help 92 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or 93 if you have a 100 Mhz SH-3 HD6417708R CPU. 94 95config CPU_SUBTYPE_SH7709 96 bool "Support SH7709 processor" 97 select CPU_SH3 98 select CPU_HAS_IPR_IRQ 99 select CPU_HAS_PINT_IRQ 100 help 101 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. 102 103config CPU_SUBTYPE_SH7710 104 bool "Support SH7710 processor" 105 select CPU_SH3 106 select CPU_HAS_IPR_IRQ 107 help 108 Select SH7710 if you have a SH3-DSP SH7710 CPU. 109 110config CPU_SUBTYPE_SH7712 111 bool "Support SH7712 processor" 112 select CPU_SH3 113 select CPU_HAS_IPR_IRQ 114 help 115 Select SH7712 if you have a SH3-DSP SH7712 CPU. 116 117# SH-4 Processor Support 118 119config CPU_SUBTYPE_SH7750 120 bool "Support SH7750 processor" 121 select CPU_SH4 122 select CPU_HAS_IPR_IRQ 123 help 124 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. 125 126config CPU_SUBTYPE_SH7091 127 bool "Support SH7091 processor" 128 select CPU_SH4 129 help 130 Select SH7091 if you have an SH-4 based Sega device (such as 131 the Dreamcast, Naomi, and Naomi 2). 132 133config CPU_SUBTYPE_SH7750R 134 bool "Support SH7750R processor" 135 select CPU_SH4 136 select CPU_HAS_IPR_IRQ 137 138config CPU_SUBTYPE_SH7750S 139 bool "Support SH7750S processor" 140 select CPU_SH4 141 select CPU_HAS_IPR_IRQ 142 143config CPU_SUBTYPE_SH7751 144 bool "Support SH7751 processor" 145 select CPU_SH4 146 select CPU_HAS_IPR_IRQ 147 help 148 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, 149 or if you have a HD6417751R CPU. 150 151config CPU_SUBTYPE_SH7751R 152 bool "Support SH7751R processor" 153 select CPU_SH4 154 select CPU_HAS_IPR_IRQ 155 156config CPU_SUBTYPE_SH7760 157 bool "Support SH7760 processor" 158 select CPU_SH4 159 select CPU_HAS_INTC2_IRQ 160 select CPU_HAS_IPR_IRQ 161 162config CPU_SUBTYPE_SH4_202 163 bool "Support SH4-202 processor" 164 select CPU_SH4 165 166# ST40 Processor Support 167 168config CPU_SUBTYPE_ST40STB1 169 bool "Support ST40STB1/ST40RA processors" 170 select CPU_SUBTYPE_ST40 171 help 172 Select ST40STB1 if you have a ST40RA CPU. 173 This was previously called the ST40STB1, hence the option name. 174 175config CPU_SUBTYPE_ST40GX1 176 bool "Support ST40GX1 processor" 177 select CPU_SUBTYPE_ST40 178 help 179 Select ST40GX1 if you have a ST40GX1 CPU. 180 181# SH-4A Processor Support 182 183config CPU_SUBTYPE_SH7770 184 bool "Support SH7770 processor" 185 select CPU_SH4A 186 187config CPU_SUBTYPE_SH7780 188 bool "Support SH7780 processor" 189 select CPU_SH4A 190 select CPU_HAS_INTC2_IRQ 191 192config CPU_SUBTYPE_SH7785 193 bool "Support SH7785 processor" 194 select CPU_SH4A 195 select CPU_SHX2 196 select CPU_HAS_INTC2_IRQ 197 198# SH4AL-DSP Processor Support 199 200config CPU_SUBTYPE_SH73180 201 bool "Support SH73180 processor" 202 select CPU_SH4AL_DSP 203 204config CPU_SUBTYPE_SH7343 205 bool "Support SH7343 processor" 206 select CPU_SH4AL_DSP 207 208config CPU_SUBTYPE_SH7722 209 bool "Support SH7722 processor" 210 select CPU_SH4AL_DSP 211 select CPU_SHX2 212 select CPU_HAS_IPR_IRQ 213 214endchoice 215 216menu "Memory management options" 217 218config QUICKLIST 219 def_bool y 220 221config MMU 222 bool "Support for memory management hardware" 223 depends on !CPU_SH2 224 default y 225 help 226 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 227 boot on these systems, this option must not be set. 228 229 On other systems (such as the SH-3 and 4) where an MMU exists, 230 turning this off will boot the kernel on these machines with the 231 MMU implicitly switched off. 232 233config PAGE_OFFSET 234 hex 235 default "0x80000000" if MMU 236 default "0x00000000" 237 238config MEMORY_START 239 hex "Physical memory start address" 240 default "0x08000000" 241 ---help--- 242 Computers built with Hitachi SuperH processors always 243 map the ROM starting at address zero. But the processor 244 does not specify the range that RAM takes. 245 246 The physical memory (RAM) start address will be automatically 247 set to 08000000. Other platforms, such as the Solution Engine 248 boards typically map RAM at 0C000000. 249 250 Tweak this only when porting to a new machine which does not 251 already have a defconfig. Changing it from the known correct 252 value on any of the known systems will only lead to disaster. 253 254config MEMORY_SIZE 255 hex "Physical memory size" 256 default "0x00400000" 257 help 258 This sets the default memory size assumed by your SH kernel. It can 259 be overridden as normal by the 'mem=' argument on the kernel command 260 line. If unsure, consult your board specifications or just leave it 261 as 0x00400000 which was the default value before this became 262 configurable. 263 264config 32BIT 265 bool "Support 32-bit physical addressing through PMB" 266 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN) 267 default y 268 help 269 If you say Y here, physical addressing will be extended to 270 32-bits through the SH-4A PMB. If this is not set, legacy 271 29-bit physical addressing will be used. 272 273config X2TLB 274 bool "Enable extended TLB mode" 275 depends on CPU_SHX2 && MMU && EXPERIMENTAL 276 help 277 Selecting this option will enable the extended mode of the SH-X2 278 TLB. For legacy SH-X behaviour and interoperability, say N. For 279 all of the fun new features and a willingless to submit bug reports, 280 say Y. 281 282config VSYSCALL 283 bool "Support vsyscall page" 284 depends on MMU 285 default y 286 help 287 This will enable support for the kernel mapping a vDSO page 288 in process space, and subsequently handing down the entry point 289 to the libc through the ELF auxiliary vector. 290 291 From the kernel side this is used for the signal trampoline. 292 For systems with an MMU that can afford to give up a page, 293 (the default value) say Y. 294 295config NODES_SHIFT 296 int 297 default "1" 298 depends on NEED_MULTIPLE_NODES 299 300config ARCH_FLATMEM_ENABLE 301 def_bool y 302 303config MAX_ACTIVE_REGIONS 304 int 305 default "1" 306 307config ARCH_POPULATES_NODE_MAP 308 def_bool y 309 310choice 311 prompt "Kernel page size" 312 default PAGE_SIZE_4KB 313 314config PAGE_SIZE_4KB 315 bool "4kB" 316 help 317 This is the default page size used by all SuperH CPUs. 318 319config PAGE_SIZE_8KB 320 bool "8kB" 321 depends on EXPERIMENTAL && X2TLB 322 help 323 This enables 8kB pages as supported by SH-X2 and later MMUs. 324 325config PAGE_SIZE_64KB 326 bool "64kB" 327 depends on EXPERIMENTAL && CPU_SH4 328 help 329 This enables support for 64kB pages, possible on all SH-4 330 CPUs and later. Highly experimental, not recommended. 331 332endchoice 333 334choice 335 prompt "HugeTLB page size" 336 depends on HUGETLB_PAGE && CPU_SH4 && MMU 337 default HUGETLB_PAGE_SIZE_64K 338 339config HUGETLB_PAGE_SIZE_64K 340 bool "64kB" 341 342config HUGETLB_PAGE_SIZE_256K 343 bool "256kB" 344 depends on X2TLB 345 346config HUGETLB_PAGE_SIZE_1MB 347 bool "1MB" 348 349config HUGETLB_PAGE_SIZE_4MB 350 bool "4MB" 351 depends on X2TLB 352 353config HUGETLB_PAGE_SIZE_64MB 354 bool "64MB" 355 depends on X2TLB 356 357endchoice 358 359source "mm/Kconfig" 360 361endmenu 362 363menu "Cache configuration" 364 365config SH7705_CACHE_32KB 366 bool "Enable 32KB cache size for SH7705" 367 depends on CPU_SUBTYPE_SH7705 368 default y 369 370config SH_DIRECT_MAPPED 371 bool "Use direct-mapped caching" 372 default n 373 help 374 Selecting this option will configure the caches to be direct-mapped, 375 even if the cache supports a 2 or 4-way mode. This is useful primarily 376 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R, 377 SH4-202, SH4-501, etc.) 378 379 Turn this option off for platforms that do not have a direct-mapped 380 cache, and you have no need to run the caches in such a configuration. 381 382config SH_WRITETHROUGH 383 bool "Use write-through caching" 384 help 385 Selecting this option will configure the caches in write-through 386 mode, as opposed to the default write-back configuration. 387 388 Since there's sill some aliasing issues on SH-4, this option will 389 unfortunately still require the majority of flushing functions to 390 be implemented to deal with aliasing. 391 392 If unsure, say N. 393 394config SH_OCRAM 395 bool "Operand Cache RAM (OCRAM) support" 396 help 397 Selecting this option will automatically tear down the number of 398 sets in the dcache by half, which in turn exposes a memory range. 399 400 The addresses for the OC RAM base will vary according to the 401 processor version. Consult vendor documentation for specifics. 402 403 If unsure, say N. 404 405endmenu 406