1 /* 2 * 'traps.c' handles hardware traps and faults after we have saved some 3 * state in 'entry.S'. 4 * 5 * SuperH version: Copyright (C) 1999 Niibe Yutaka 6 * Copyright (C) 2000 Philipp Rumpf 7 * Copyright (C) 2000 David Howells 8 * Copyright (C) 2002 - 2007 Paul Mundt 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/ptrace.h> 16 #include <linux/hardirq.h> 17 #include <linux/init.h> 18 #include <linux/spinlock.h> 19 #include <linux/module.h> 20 #include <linux/kallsyms.h> 21 #include <linux/io.h> 22 #include <linux/bug.h> 23 #include <linux/debug_locks.h> 24 #include <linux/kdebug.h> 25 #include <linux/kexec.h> 26 #include <linux/limits.h> 27 #include <linux/proc_fs.h> 28 #include <asm/system.h> 29 #include <asm/uaccess.h> 30 #include <asm/fpu.h> 31 #include <asm/kprobes.h> 32 33 #ifdef CONFIG_CPU_SH2 34 # define TRAP_RESERVED_INST 4 35 # define TRAP_ILLEGAL_SLOT_INST 6 36 # define TRAP_ADDRESS_ERROR 9 37 # ifdef CONFIG_CPU_SH2A 38 # define TRAP_UBC 12 39 # define TRAP_FPU_ERROR 13 40 # define TRAP_DIVZERO_ERROR 17 41 # define TRAP_DIVOVF_ERROR 18 42 # endif 43 #else 44 #define TRAP_RESERVED_INST 12 45 #define TRAP_ILLEGAL_SLOT_INST 13 46 #endif 47 48 static unsigned long se_user; 49 static unsigned long se_sys; 50 static unsigned long se_skipped; 51 static unsigned long se_half; 52 static unsigned long se_word; 53 static unsigned long se_dword; 54 static unsigned long se_multi; 55 /* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not 56 valid! */ 57 static int se_usermode = 3; 58 /* 0: no warning 1: print a warning message */ 59 static int se_kernmode_warn = 1; 60 61 #ifdef CONFIG_PROC_FS 62 static const char *se_usermode_action[] = { 63 "ignored", 64 "warn", 65 "fixup", 66 "fixup+warn", 67 "signal", 68 "signal+warn" 69 }; 70 71 static int 72 proc_alignment_read(char *page, char **start, off_t off, int count, int *eof, 73 void *data) 74 { 75 char *p = page; 76 int len; 77 78 p += sprintf(p, "User:\t\t%lu\n", se_user); 79 p += sprintf(p, "System:\t\t%lu\n", se_sys); 80 p += sprintf(p, "Skipped:\t%lu\n", se_skipped); 81 p += sprintf(p, "Half:\t\t%lu\n", se_half); 82 p += sprintf(p, "Word:\t\t%lu\n", se_word); 83 p += sprintf(p, "DWord:\t\t%lu\n", se_dword); 84 p += sprintf(p, "Multi:\t\t%lu\n", se_multi); 85 p += sprintf(p, "User faults:\t%i (%s)\n", se_usermode, 86 se_usermode_action[se_usermode]); 87 p += sprintf(p, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn, 88 se_kernmode_warn ? "+warn" : ""); 89 90 len = (p - page) - off; 91 if (len < 0) 92 len = 0; 93 94 *eof = (len <= count) ? 1 : 0; 95 *start = page + off; 96 97 return len; 98 } 99 100 static int proc_alignment_write(struct file *file, const char __user *buffer, 101 unsigned long count, void *data) 102 { 103 char mode; 104 105 if (count > 0) { 106 if (get_user(mode, buffer)) 107 return -EFAULT; 108 if (mode >= '0' && mode <= '5') 109 se_usermode = mode - '0'; 110 } 111 return count; 112 } 113 114 static int proc_alignment_kern_write(struct file *file, const char __user *buffer, 115 unsigned long count, void *data) 116 { 117 char mode; 118 119 if (count > 0) { 120 if (get_user(mode, buffer)) 121 return -EFAULT; 122 if (mode >= '0' && mode <= '1') 123 se_kernmode_warn = mode - '0'; 124 } 125 return count; 126 } 127 #endif 128 129 static void dump_mem(const char *str, unsigned long bottom, unsigned long top) 130 { 131 unsigned long p; 132 int i; 133 134 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); 135 136 for (p = bottom & ~31; p < top; ) { 137 printk("%04lx: ", p & 0xffff); 138 139 for (i = 0; i < 8; i++, p += 4) { 140 unsigned int val; 141 142 if (p < bottom || p >= top) 143 printk(" "); 144 else { 145 if (__get_user(val, (unsigned int __user *)p)) { 146 printk("\n"); 147 return; 148 } 149 printk("%08x ", val); 150 } 151 } 152 printk("\n"); 153 } 154 } 155 156 static DEFINE_SPINLOCK(die_lock); 157 158 void die(const char * str, struct pt_regs * regs, long err) 159 { 160 static int die_counter; 161 162 oops_enter(); 163 164 console_verbose(); 165 spin_lock_irq(&die_lock); 166 bust_spinlocks(1); 167 168 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); 169 170 print_modules(); 171 show_regs(regs); 172 173 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm, 174 task_pid_nr(current), task_stack_page(current) + 1); 175 176 if (!user_mode(regs) || in_interrupt()) 177 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE + 178 (unsigned long)task_stack_page(current)); 179 180 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV); 181 182 bust_spinlocks(0); 183 add_taint(TAINT_DIE); 184 spin_unlock_irq(&die_lock); 185 186 if (kexec_should_crash(current)) 187 crash_kexec(regs); 188 189 if (in_interrupt()) 190 panic("Fatal exception in interrupt"); 191 192 if (panic_on_oops) 193 panic("Fatal exception"); 194 195 oops_exit(); 196 do_exit(SIGSEGV); 197 } 198 199 static inline void die_if_kernel(const char *str, struct pt_regs *regs, 200 long err) 201 { 202 if (!user_mode(regs)) 203 die(str, regs, err); 204 } 205 206 /* 207 * try and fix up kernelspace address errors 208 * - userspace errors just cause EFAULT to be returned, resulting in SEGV 209 * - kernel/userspace interfaces cause a jump to an appropriate handler 210 * - other kernel errors are bad 211 */ 212 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err) 213 { 214 if (!user_mode(regs)) { 215 const struct exception_table_entry *fixup; 216 fixup = search_exception_tables(regs->pc); 217 if (fixup) { 218 regs->pc = fixup->fixup; 219 return; 220 } 221 222 die(str, regs, err); 223 } 224 } 225 226 static inline void sign_extend(unsigned int count, unsigned char *dst) 227 { 228 #ifdef __LITTLE_ENDIAN__ 229 if ((count == 1) && dst[0] & 0x80) { 230 dst[1] = 0xff; 231 dst[2] = 0xff; 232 dst[3] = 0xff; 233 } 234 if ((count == 2) && dst[1] & 0x80) { 235 dst[2] = 0xff; 236 dst[3] = 0xff; 237 } 238 #else 239 if ((count == 1) && dst[3] & 0x80) { 240 dst[2] = 0xff; 241 dst[1] = 0xff; 242 dst[0] = 0xff; 243 } 244 if ((count == 2) && dst[2] & 0x80) { 245 dst[1] = 0xff; 246 dst[0] = 0xff; 247 } 248 #endif 249 } 250 251 static struct mem_access user_mem_access = { 252 copy_from_user, 253 copy_to_user, 254 }; 255 256 /* 257 * handle an instruction that does an unaligned memory access by emulating the 258 * desired behaviour 259 * - note that PC _may not_ point to the faulting instruction 260 * (if that instruction is in a branch delay slot) 261 * - return 0 if emulation okay, -EFAULT on existential error 262 */ 263 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, 264 struct mem_access *ma) 265 { 266 int ret, index, count; 267 unsigned long *rm, *rn; 268 unsigned char *src, *dst; 269 unsigned char __user *srcu, *dstu; 270 271 index = (instruction>>8)&15; /* 0x0F00 */ 272 rn = ®s->regs[index]; 273 274 index = (instruction>>4)&15; /* 0x00F0 */ 275 rm = ®s->regs[index]; 276 277 count = 1<<(instruction&3); 278 279 switch (count) { 280 case 1: se_half += 1; break; 281 case 2: se_word += 1; break; 282 case 4: se_dword += 1; break; 283 case 8: se_multi += 1; break; /* ??? */ 284 } 285 286 ret = -EFAULT; 287 switch (instruction>>12) { 288 case 0: /* mov.[bwl] to/from memory via r0+rn */ 289 if (instruction & 8) { 290 /* from memory */ 291 srcu = (unsigned char __user *)*rm; 292 srcu += regs->regs[0]; 293 dst = (unsigned char *)rn; 294 *(unsigned long *)dst = 0; 295 296 #if !defined(__LITTLE_ENDIAN__) 297 dst += 4-count; 298 #endif 299 if (ma->from(dst, srcu, count)) 300 goto fetch_fault; 301 302 sign_extend(count, dst); 303 } else { 304 /* to memory */ 305 src = (unsigned char *)rm; 306 #if !defined(__LITTLE_ENDIAN__) 307 src += 4-count; 308 #endif 309 dstu = (unsigned char __user *)*rn; 310 dstu += regs->regs[0]; 311 312 if (ma->to(dstu, src, count)) 313 goto fetch_fault; 314 } 315 ret = 0; 316 break; 317 318 case 1: /* mov.l Rm,@(disp,Rn) */ 319 src = (unsigned char*) rm; 320 dstu = (unsigned char __user *)*rn; 321 dstu += (instruction&0x000F)<<2; 322 323 if (ma->to(dstu, src, 4)) 324 goto fetch_fault; 325 ret = 0; 326 break; 327 328 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ 329 if (instruction & 4) 330 *rn -= count; 331 src = (unsigned char*) rm; 332 dstu = (unsigned char __user *)*rn; 333 #if !defined(__LITTLE_ENDIAN__) 334 src += 4-count; 335 #endif 336 if (ma->to(dstu, src, count)) 337 goto fetch_fault; 338 ret = 0; 339 break; 340 341 case 5: /* mov.l @(disp,Rm),Rn */ 342 srcu = (unsigned char __user *)*rm; 343 srcu += (instruction & 0x000F) << 2; 344 dst = (unsigned char *)rn; 345 *(unsigned long *)dst = 0; 346 347 if (ma->from(dst, srcu, 4)) 348 goto fetch_fault; 349 ret = 0; 350 break; 351 352 case 6: /* mov.[bwl] from memory, possibly with post-increment */ 353 srcu = (unsigned char __user *)*rm; 354 if (instruction & 4) 355 *rm += count; 356 dst = (unsigned char*) rn; 357 *(unsigned long*)dst = 0; 358 359 #if !defined(__LITTLE_ENDIAN__) 360 dst += 4-count; 361 #endif 362 if (ma->from(dst, srcu, count)) 363 goto fetch_fault; 364 sign_extend(count, dst); 365 ret = 0; 366 break; 367 368 case 8: 369 switch ((instruction&0xFF00)>>8) { 370 case 0x81: /* mov.w R0,@(disp,Rn) */ 371 src = (unsigned char *) ®s->regs[0]; 372 #if !defined(__LITTLE_ENDIAN__) 373 src += 2; 374 #endif 375 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */ 376 dstu += (instruction & 0x000F) << 1; 377 378 if (ma->to(dstu, src, 2)) 379 goto fetch_fault; 380 ret = 0; 381 break; 382 383 case 0x85: /* mov.w @(disp,Rm),R0 */ 384 srcu = (unsigned char __user *)*rm; 385 srcu += (instruction & 0x000F) << 1; 386 dst = (unsigned char *) ®s->regs[0]; 387 *(unsigned long *)dst = 0; 388 389 #if !defined(__LITTLE_ENDIAN__) 390 dst += 2; 391 #endif 392 if (ma->from(dst, srcu, 2)) 393 goto fetch_fault; 394 sign_extend(2, dst); 395 ret = 0; 396 break; 397 } 398 break; 399 } 400 return ret; 401 402 fetch_fault: 403 /* Argh. Address not only misaligned but also non-existent. 404 * Raise an EFAULT and see if it's trapped 405 */ 406 die_if_no_fixup("Fault in unaligned fixup", regs, 0); 407 return -EFAULT; 408 } 409 410 /* 411 * emulate the instruction in the delay slot 412 * - fetches the instruction from PC+2 413 */ 414 static inline int handle_delayslot(struct pt_regs *regs, 415 insn_size_t old_instruction, 416 struct mem_access *ma) 417 { 418 insn_size_t instruction; 419 void __user *addr = (void __user *)(regs->pc + 420 instruction_size(old_instruction)); 421 422 if (copy_from_user(&instruction, addr, sizeof(instruction))) { 423 /* the instruction-fetch faulted */ 424 if (user_mode(regs)) 425 return -EFAULT; 426 427 /* kernel */ 428 die("delay-slot-insn faulting in handle_unaligned_delayslot", 429 regs, 0); 430 } 431 432 return handle_unaligned_ins(instruction, regs, ma); 433 } 434 435 /* 436 * handle an instruction that does an unaligned memory access 437 * - have to be careful of branch delay-slot instructions that fault 438 * SH3: 439 * - if the branch would be taken PC points to the branch 440 * - if the branch would not be taken, PC points to delay-slot 441 * SH4: 442 * - PC always points to delayed branch 443 * - return 0 if handled, -EFAULT if failed (may not return if in kernel) 444 */ 445 446 /* Macros to determine offset from current PC for branch instructions */ 447 /* Explicit type coercion is used to force sign extension where needed */ 448 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) 449 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 450 451 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 452 struct mem_access *ma, int expected) 453 { 454 u_int rm; 455 int ret, index; 456 457 index = (instruction>>8)&15; /* 0x0F00 */ 458 rm = regs->regs[index]; 459 460 /* shout about fixups */ 461 if (!expected && printk_ratelimit()) 462 printk(KERN_NOTICE "Fixing up unaligned %s access " 463 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 464 user_mode(regs) ? "userspace" : "kernel", 465 current->comm, task_pid_nr(current), 466 (void *)regs->pc, instruction); 467 468 ret = -EFAULT; 469 switch (instruction&0xF000) { 470 case 0x0000: 471 if (instruction==0x000B) { 472 /* rts */ 473 ret = handle_delayslot(regs, instruction, ma); 474 if (ret==0) 475 regs->pc = regs->pr; 476 } 477 else if ((instruction&0x00FF)==0x0023) { 478 /* braf @Rm */ 479 ret = handle_delayslot(regs, instruction, ma); 480 if (ret==0) 481 regs->pc += rm + 4; 482 } 483 else if ((instruction&0x00FF)==0x0003) { 484 /* bsrf @Rm */ 485 ret = handle_delayslot(regs, instruction, ma); 486 if (ret==0) { 487 regs->pr = regs->pc + 4; 488 regs->pc += rm + 4; 489 } 490 } 491 else { 492 /* mov.[bwl] to/from memory via r0+rn */ 493 goto simple; 494 } 495 break; 496 497 case 0x1000: /* mov.l Rm,@(disp,Rn) */ 498 goto simple; 499 500 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ 501 goto simple; 502 503 case 0x4000: 504 if ((instruction&0x00FF)==0x002B) { 505 /* jmp @Rm */ 506 ret = handle_delayslot(regs, instruction, ma); 507 if (ret==0) 508 regs->pc = rm; 509 } 510 else if ((instruction&0x00FF)==0x000B) { 511 /* jsr @Rm */ 512 ret = handle_delayslot(regs, instruction, ma); 513 if (ret==0) { 514 regs->pr = regs->pc + 4; 515 regs->pc = rm; 516 } 517 } 518 else { 519 /* mov.[bwl] to/from memory via r0+rn */ 520 goto simple; 521 } 522 break; 523 524 case 0x5000: /* mov.l @(disp,Rm),Rn */ 525 goto simple; 526 527 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ 528 goto simple; 529 530 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ 531 switch (instruction&0x0F00) { 532 case 0x0100: /* mov.w R0,@(disp,Rm) */ 533 goto simple; 534 case 0x0500: /* mov.w @(disp,Rm),R0 */ 535 goto simple; 536 case 0x0B00: /* bf lab - no delayslot*/ 537 break; 538 case 0x0F00: /* bf/s lab */ 539 ret = handle_delayslot(regs, instruction, ma); 540 if (ret==0) { 541 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 542 if ((regs->sr & 0x00000001) != 0) 543 regs->pc += 4; /* next after slot */ 544 else 545 #endif 546 regs->pc += SH_PC_8BIT_OFFSET(instruction); 547 } 548 break; 549 case 0x0900: /* bt lab - no delayslot */ 550 break; 551 case 0x0D00: /* bt/s lab */ 552 ret = handle_delayslot(regs, instruction, ma); 553 if (ret==0) { 554 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 555 if ((regs->sr & 0x00000001) == 0) 556 regs->pc += 4; /* next after slot */ 557 else 558 #endif 559 regs->pc += SH_PC_8BIT_OFFSET(instruction); 560 } 561 break; 562 } 563 break; 564 565 case 0xA000: /* bra label */ 566 ret = handle_delayslot(regs, instruction, ma); 567 if (ret==0) 568 regs->pc += SH_PC_12BIT_OFFSET(instruction); 569 break; 570 571 case 0xB000: /* bsr label */ 572 ret = handle_delayslot(regs, instruction, ma); 573 if (ret==0) { 574 regs->pr = regs->pc + 4; 575 regs->pc += SH_PC_12BIT_OFFSET(instruction); 576 } 577 break; 578 } 579 return ret; 580 581 /* handle non-delay-slot instruction */ 582 simple: 583 ret = handle_unaligned_ins(instruction, regs, ma); 584 if (ret==0) 585 regs->pc += instruction_size(instruction); 586 return ret; 587 } 588 589 /* 590 * Handle various address error exceptions: 591 * - instruction address error: 592 * misaligned PC 593 * PC >= 0x80000000 in user mode 594 * - data address error (read and write) 595 * misaligned data access 596 * access to >= 0x80000000 is user mode 597 * Unfortuntaly we can't distinguish between instruction address error 598 * and data address errors caused by read accesses. 599 */ 600 asmlinkage void do_address_error(struct pt_regs *regs, 601 unsigned long writeaccess, 602 unsigned long address) 603 { 604 unsigned long error_code = 0; 605 mm_segment_t oldfs; 606 siginfo_t info; 607 insn_size_t instruction; 608 int tmp; 609 610 /* Intentional ifdef */ 611 #ifdef CONFIG_CPU_HAS_SR_RB 612 error_code = lookup_exception_vector(); 613 #endif 614 615 oldfs = get_fs(); 616 617 if (user_mode(regs)) { 618 int si_code = BUS_ADRERR; 619 620 local_irq_enable(); 621 622 se_user += 1; 623 624 #ifndef CONFIG_CPU_SH2A 625 set_fs(USER_DS); 626 if (copy_from_user(&instruction, (u16 *)(regs->pc & ~1), 2)) { 627 set_fs(oldfs); 628 goto uspace_segv; 629 } 630 set_fs(oldfs); 631 632 /* shout about userspace fixups */ 633 if (se_usermode & 1) 634 printk(KERN_NOTICE "Unaligned userspace access " 635 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 636 current->comm, current->pid, (void *)regs->pc, 637 instruction); 638 #endif 639 640 if (se_usermode & 2) 641 goto fixup; 642 643 if (se_usermode & 4) 644 goto uspace_segv; 645 else { 646 /* ignore */ 647 regs->pc += instruction_size(instruction); 648 return; 649 } 650 651 fixup: 652 /* bad PC is not something we can fix */ 653 if (regs->pc & 1) { 654 si_code = BUS_ADRALN; 655 goto uspace_segv; 656 } 657 658 set_fs(USER_DS); 659 tmp = handle_unaligned_access(instruction, regs, 660 &user_mem_access, 0); 661 set_fs(oldfs); 662 663 if (tmp==0) 664 return; /* sorted */ 665 uspace_segv: 666 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned " 667 "access (PC %lx PR %lx)\n", current->comm, regs->pc, 668 regs->pr); 669 670 info.si_signo = SIGBUS; 671 info.si_errno = 0; 672 info.si_code = si_code; 673 info.si_addr = (void __user *)address; 674 force_sig_info(SIGBUS, &info, current); 675 } else { 676 se_sys += 1; 677 678 if (se_kernmode_warn) 679 printk(KERN_NOTICE "Unaligned kernel access " 680 "on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 681 current->comm, current->pid, (void *)regs->pc, 682 instruction); 683 684 if (regs->pc & 1) 685 die("unaligned program counter", regs, error_code); 686 687 set_fs(KERNEL_DS); 688 if (copy_from_user(&instruction, (void __user *)(regs->pc), 689 sizeof(instruction))) { 690 /* Argh. Fault on the instruction itself. 691 This should never happen non-SMP 692 */ 693 set_fs(oldfs); 694 die("insn faulting in do_address_error", regs, 0); 695 } 696 697 handle_unaligned_access(instruction, regs, 698 &user_mem_access, 0); 699 set_fs(oldfs); 700 } 701 } 702 703 #ifdef CONFIG_SH_DSP 704 /* 705 * SH-DSP support gerg@snapgear.com. 706 */ 707 int is_dsp_inst(struct pt_regs *regs) 708 { 709 unsigned short inst = 0; 710 711 /* 712 * Safe guard if DSP mode is already enabled or we're lacking 713 * the DSP altogether. 714 */ 715 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) 716 return 0; 717 718 get_user(inst, ((unsigned short *) regs->pc)); 719 720 inst &= 0xf000; 721 722 /* Check for any type of DSP or support instruction */ 723 if ((inst == 0xf000) || (inst == 0x4000)) 724 return 1; 725 726 return 0; 727 } 728 #else 729 #define is_dsp_inst(regs) (0) 730 #endif /* CONFIG_SH_DSP */ 731 732 #ifdef CONFIG_CPU_SH2A 733 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5, 734 unsigned long r6, unsigned long r7, 735 struct pt_regs __regs) 736 { 737 siginfo_t info; 738 739 switch (r4) { 740 case TRAP_DIVZERO_ERROR: 741 info.si_code = FPE_INTDIV; 742 break; 743 case TRAP_DIVOVF_ERROR: 744 info.si_code = FPE_INTOVF; 745 break; 746 } 747 748 force_sig_info(SIGFPE, &info, current); 749 } 750 #endif 751 752 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, 753 unsigned long r6, unsigned long r7, 754 struct pt_regs __regs) 755 { 756 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 757 unsigned long error_code; 758 struct task_struct *tsk = current; 759 760 #ifdef CONFIG_SH_FPU_EMU 761 unsigned short inst = 0; 762 int err; 763 764 get_user(inst, (unsigned short*)regs->pc); 765 766 err = do_fpu_inst(inst, regs); 767 if (!err) { 768 regs->pc += instruction_size(inst); 769 return; 770 } 771 /* not a FPU inst. */ 772 #endif 773 774 #ifdef CONFIG_SH_DSP 775 /* Check if it's a DSP instruction */ 776 if (is_dsp_inst(regs)) { 777 /* Enable DSP mode, and restart instruction. */ 778 regs->sr |= SR_DSP; 779 /* Save DSP mode */ 780 tsk->thread.dsp_status.status |= SR_DSP; 781 return; 782 } 783 #endif 784 785 error_code = lookup_exception_vector(); 786 787 local_irq_enable(); 788 force_sig(SIGILL, tsk); 789 die_if_no_fixup("reserved instruction", regs, error_code); 790 } 791 792 #ifdef CONFIG_SH_FPU_EMU 793 static int emulate_branch(unsigned short inst, struct pt_regs *regs) 794 { 795 /* 796 * bfs: 8fxx: PC+=d*2+4; 797 * bts: 8dxx: PC+=d*2+4; 798 * bra: axxx: PC+=D*2+4; 799 * bsr: bxxx: PC+=D*2+4 after PR=PC+4; 800 * braf:0x23: PC+=Rn*2+4; 801 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4; 802 * jmp: 4x2b: PC=Rn; 803 * jsr: 4x0b: PC=Rn after PR=PC+4; 804 * rts: 000b: PC=PR; 805 */ 806 if (((inst & 0xf000) == 0xb000) || /* bsr */ 807 ((inst & 0xf0ff) == 0x0003) || /* bsrf */ 808 ((inst & 0xf0ff) == 0x400b)) /* jsr */ 809 regs->pr = regs->pc + 4; 810 811 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */ 812 regs->pc += SH_PC_8BIT_OFFSET(inst); 813 return 0; 814 } 815 816 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */ 817 regs->pc += SH_PC_12BIT_OFFSET(inst); 818 return 0; 819 } 820 821 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */ 822 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; 823 return 0; 824 } 825 826 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */ 827 regs->pc = regs->regs[(inst & 0x0f00) >> 8]; 828 return 0; 829 } 830 831 if ((inst & 0xffff) == 0x000b) { /* rts */ 832 regs->pc = regs->pr; 833 return 0; 834 } 835 836 return 1; 837 } 838 #endif 839 840 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5, 841 unsigned long r6, unsigned long r7, 842 struct pt_regs __regs) 843 { 844 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 845 unsigned long inst; 846 struct task_struct *tsk = current; 847 848 if (kprobe_handle_illslot(regs->pc) == 0) 849 return; 850 851 #ifdef CONFIG_SH_FPU_EMU 852 get_user(inst, (unsigned short *)regs->pc + 1); 853 if (!do_fpu_inst(inst, regs)) { 854 get_user(inst, (unsigned short *)regs->pc); 855 if (!emulate_branch(inst, regs)) 856 return; 857 /* fault in branch.*/ 858 } 859 /* not a FPU inst. */ 860 #endif 861 862 inst = lookup_exception_vector(); 863 864 local_irq_enable(); 865 force_sig(SIGILL, tsk); 866 die_if_no_fixup("illegal slot instruction", regs, inst); 867 } 868 869 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, 870 unsigned long r6, unsigned long r7, 871 struct pt_regs __regs) 872 { 873 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 874 long ex; 875 876 ex = lookup_exception_vector(); 877 die_if_kernel("exception", regs, ex); 878 } 879 880 #if defined(CONFIG_SH_STANDARD_BIOS) 881 void *gdb_vbr_vector; 882 883 static inline void __init gdb_vbr_init(void) 884 { 885 register unsigned long vbr; 886 887 /* 888 * Read the old value of the VBR register to initialise 889 * the vector through which debug and BIOS traps are 890 * delegated by the Linux trap handler. 891 */ 892 asm volatile("stc vbr, %0" : "=r" (vbr)); 893 894 gdb_vbr_vector = (void *)(vbr + 0x100); 895 printk("Setting GDB trap vector to 0x%08lx\n", 896 (unsigned long)gdb_vbr_vector); 897 } 898 #endif 899 900 void __cpuinit per_cpu_trap_init(void) 901 { 902 extern void *vbr_base; 903 904 #ifdef CONFIG_SH_STANDARD_BIOS 905 if (raw_smp_processor_id() == 0) 906 gdb_vbr_init(); 907 #endif 908 909 /* NOTE: The VBR value should be at P1 910 (or P2, virtural "fixed" address space). 911 It's definitely should not in physical address. */ 912 913 asm volatile("ldc %0, vbr" 914 : /* no output */ 915 : "r" (&vbr_base) 916 : "memory"); 917 } 918 919 void *set_exception_table_vec(unsigned int vec, void *handler) 920 { 921 extern void *exception_handling_table[]; 922 void *old_handler; 923 924 old_handler = exception_handling_table[vec]; 925 exception_handling_table[vec] = handler; 926 return old_handler; 927 } 928 929 void __init trap_init(void) 930 { 931 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst); 932 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst); 933 934 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ 935 defined(CONFIG_SH_FPU_EMU) 936 /* 937 * For SH-4 lacking an FPU, treat floating point instructions as 938 * reserved. They'll be handled in the math-emu case, or faulted on 939 * otherwise. 940 */ 941 set_exception_table_evt(0x800, do_reserved_inst); 942 set_exception_table_evt(0x820, do_illegal_slot_inst); 943 #elif defined(CONFIG_SH_FPU) 944 #ifdef CONFIG_CPU_SUBTYPE_SHX3 945 set_exception_table_evt(0xd80, fpu_state_restore_trap_handler); 946 set_exception_table_evt(0xda0, fpu_state_restore_trap_handler); 947 #else 948 set_exception_table_evt(0x800, fpu_state_restore_trap_handler); 949 set_exception_table_evt(0x820, fpu_state_restore_trap_handler); 950 #endif 951 #endif 952 953 #ifdef CONFIG_CPU_SH2 954 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler); 955 #endif 956 #ifdef CONFIG_CPU_SH2A 957 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error); 958 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error); 959 #ifdef CONFIG_SH_FPU 960 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler); 961 #endif 962 #endif 963 964 #ifdef TRAP_UBC 965 set_exception_table_vec(TRAP_UBC, break_point_trap); 966 #endif 967 968 /* Setup VBR for boot cpu */ 969 per_cpu_trap_init(); 970 } 971 972 void show_stack(struct task_struct *tsk, unsigned long *sp) 973 { 974 unsigned long stack; 975 976 if (!tsk) 977 tsk = current; 978 if (tsk == current) 979 sp = (unsigned long *)current_stack_pointer; 980 else 981 sp = (unsigned long *)tsk->thread.sp; 982 983 stack = (unsigned long)sp; 984 dump_mem("Stack: ", stack, THREAD_SIZE + 985 (unsigned long)task_stack_page(tsk)); 986 show_trace(tsk, sp, NULL); 987 } 988 989 void dump_stack(void) 990 { 991 show_stack(NULL, NULL); 992 } 993 EXPORT_SYMBOL(dump_stack); 994 995 #ifdef CONFIG_PROC_FS 996 /* 997 * This needs to be done after sysctl_init, otherwise sys/ will be 998 * overwritten. Actually, this shouldn't be in sys/ at all since 999 * it isn't a sysctl, and it doesn't contain sysctl information. 1000 * We now locate it in /proc/cpu/alignment instead. 1001 */ 1002 static int __init alignment_init(void) 1003 { 1004 struct proc_dir_entry *dir, *res; 1005 1006 dir = proc_mkdir("cpu", NULL); 1007 if (!dir) 1008 return -ENOMEM; 1009 1010 res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, dir); 1011 if (!res) 1012 return -ENOMEM; 1013 1014 res->read_proc = proc_alignment_read; 1015 res->write_proc = proc_alignment_write; 1016 1017 res = create_proc_entry("kernel_alignment", S_IWUSR | S_IRUGO, dir); 1018 if (!res) 1019 return -ENOMEM; 1020 1021 res->read_proc = proc_alignment_read; 1022 res->write_proc = proc_alignment_kern_write; 1023 1024 return 0; 1025 } 1026 1027 fs_initcall(alignment_init); 1028 #endif 1029