1 /* 2 * 'traps.c' handles hardware traps and faults after we have saved some 3 * state in 'entry.S'. 4 * 5 * SuperH version: Copyright (C) 1999 Niibe Yutaka 6 * Copyright (C) 2000 Philipp Rumpf 7 * Copyright (C) 2000 David Howells 8 * Copyright (C) 2002 - 2007 Paul Mundt 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/ptrace.h> 16 #include <linux/init.h> 17 #include <linux/spinlock.h> 18 #include <linux/module.h> 19 #include <linux/kallsyms.h> 20 #include <linux/io.h> 21 #include <linux/bug.h> 22 #include <linux/debug_locks.h> 23 #include <linux/kdebug.h> 24 #include <linux/kexec.h> 25 #include <linux/limits.h> 26 #include <asm/system.h> 27 #include <asm/uaccess.h> 28 29 #ifdef CONFIG_SH_KGDB 30 #include <asm/kgdb.h> 31 #define CHK_REMOTE_DEBUG(regs) \ 32 { \ 33 if (kgdb_debug_hook && !user_mode(regs))\ 34 (*kgdb_debug_hook)(regs); \ 35 } 36 #else 37 #define CHK_REMOTE_DEBUG(regs) 38 #endif 39 40 #ifdef CONFIG_CPU_SH2 41 # define TRAP_RESERVED_INST 4 42 # define TRAP_ILLEGAL_SLOT_INST 6 43 # define TRAP_ADDRESS_ERROR 9 44 # ifdef CONFIG_CPU_SH2A 45 # define TRAP_DIVZERO_ERROR 17 46 # define TRAP_DIVOVF_ERROR 18 47 # endif 48 #else 49 #define TRAP_RESERVED_INST 12 50 #define TRAP_ILLEGAL_SLOT_INST 13 51 #endif 52 53 static void dump_mem(const char *str, unsigned long bottom, unsigned long top) 54 { 55 unsigned long p; 56 int i; 57 58 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); 59 60 for (p = bottom & ~31; p < top; ) { 61 printk("%04lx: ", p & 0xffff); 62 63 for (i = 0; i < 8; i++, p += 4) { 64 unsigned int val; 65 66 if (p < bottom || p >= top) 67 printk(" "); 68 else { 69 if (__get_user(val, (unsigned int __user *)p)) { 70 printk("\n"); 71 return; 72 } 73 printk("%08x ", val); 74 } 75 } 76 printk("\n"); 77 } 78 } 79 80 static DEFINE_SPINLOCK(die_lock); 81 82 void die(const char * str, struct pt_regs * regs, long err) 83 { 84 static int die_counter; 85 86 console_verbose(); 87 spin_lock_irq(&die_lock); 88 bust_spinlocks(1); 89 90 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); 91 92 CHK_REMOTE_DEBUG(regs); 93 print_modules(); 94 show_regs(regs); 95 96 printk("Process: %s (pid: %d, stack limit = %p)\n", 97 current->comm, current->pid, task_stack_page(current) + 1); 98 99 if (!user_mode(regs) || in_interrupt()) 100 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE + 101 (unsigned long)task_stack_page(current)); 102 103 bust_spinlocks(0); 104 spin_unlock_irq(&die_lock); 105 106 if (kexec_should_crash(current)) 107 crash_kexec(regs); 108 109 if (in_interrupt()) 110 panic("Fatal exception in interrupt"); 111 112 if (panic_on_oops) 113 panic("Fatal exception"); 114 115 do_exit(SIGSEGV); 116 } 117 118 static inline void die_if_kernel(const char *str, struct pt_regs *regs, 119 long err) 120 { 121 if (!user_mode(regs)) 122 die(str, regs, err); 123 } 124 125 /* 126 * try and fix up kernelspace address errors 127 * - userspace errors just cause EFAULT to be returned, resulting in SEGV 128 * - kernel/userspace interfaces cause a jump to an appropriate handler 129 * - other kernel errors are bad 130 * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault 131 */ 132 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err) 133 { 134 if (!user_mode(regs)) { 135 const struct exception_table_entry *fixup; 136 fixup = search_exception_tables(regs->pc); 137 if (fixup) { 138 regs->pc = fixup->fixup; 139 return 0; 140 } 141 die(str, regs, err); 142 } 143 return -EFAULT; 144 } 145 146 /* 147 * handle an instruction that does an unaligned memory access by emulating the 148 * desired behaviour 149 * - note that PC _may not_ point to the faulting instruction 150 * (if that instruction is in a branch delay slot) 151 * - return 0 if emulation okay, -EFAULT on existential error 152 */ 153 static int handle_unaligned_ins(u16 instruction, struct pt_regs *regs) 154 { 155 int ret, index, count; 156 unsigned long *rm, *rn; 157 unsigned char *src, *dst; 158 159 index = (instruction>>8)&15; /* 0x0F00 */ 160 rn = ®s->regs[index]; 161 162 index = (instruction>>4)&15; /* 0x00F0 */ 163 rm = ®s->regs[index]; 164 165 count = 1<<(instruction&3); 166 167 ret = -EFAULT; 168 switch (instruction>>12) { 169 case 0: /* mov.[bwl] to/from memory via r0+rn */ 170 if (instruction & 8) { 171 /* from memory */ 172 src = (unsigned char*) *rm; 173 src += regs->regs[0]; 174 dst = (unsigned char*) rn; 175 *(unsigned long*)dst = 0; 176 177 #ifdef __LITTLE_ENDIAN__ 178 if (copy_from_user(dst, src, count)) 179 goto fetch_fault; 180 181 if ((count == 2) && dst[1] & 0x80) { 182 dst[2] = 0xff; 183 dst[3] = 0xff; 184 } 185 #else 186 dst += 4-count; 187 188 if (__copy_user(dst, src, count)) 189 goto fetch_fault; 190 191 if ((count == 2) && dst[2] & 0x80) { 192 dst[0] = 0xff; 193 dst[1] = 0xff; 194 } 195 #endif 196 } else { 197 /* to memory */ 198 src = (unsigned char*) rm; 199 #if !defined(__LITTLE_ENDIAN__) 200 src += 4-count; 201 #endif 202 dst = (unsigned char*) *rn; 203 dst += regs->regs[0]; 204 205 if (copy_to_user(dst, src, count)) 206 goto fetch_fault; 207 } 208 ret = 0; 209 break; 210 211 case 1: /* mov.l Rm,@(disp,Rn) */ 212 src = (unsigned char*) rm; 213 dst = (unsigned char*) *rn; 214 dst += (instruction&0x000F)<<2; 215 216 if (copy_to_user(dst,src,4)) 217 goto fetch_fault; 218 ret = 0; 219 break; 220 221 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ 222 if (instruction & 4) 223 *rn -= count; 224 src = (unsigned char*) rm; 225 dst = (unsigned char*) *rn; 226 #if !defined(__LITTLE_ENDIAN__) 227 src += 4-count; 228 #endif 229 if (copy_to_user(dst, src, count)) 230 goto fetch_fault; 231 ret = 0; 232 break; 233 234 case 5: /* mov.l @(disp,Rm),Rn */ 235 src = (unsigned char*) *rm; 236 src += (instruction&0x000F)<<2; 237 dst = (unsigned char*) rn; 238 *(unsigned long*)dst = 0; 239 240 if (copy_from_user(dst,src,4)) 241 goto fetch_fault; 242 ret = 0; 243 break; 244 245 case 6: /* mov.[bwl] from memory, possibly with post-increment */ 246 src = (unsigned char*) *rm; 247 if (instruction & 4) 248 *rm += count; 249 dst = (unsigned char*) rn; 250 *(unsigned long*)dst = 0; 251 252 #ifdef __LITTLE_ENDIAN__ 253 if (copy_from_user(dst, src, count)) 254 goto fetch_fault; 255 256 if ((count == 2) && dst[1] & 0x80) { 257 dst[2] = 0xff; 258 dst[3] = 0xff; 259 } 260 #else 261 dst += 4-count; 262 263 if (copy_from_user(dst, src, count)) 264 goto fetch_fault; 265 266 if ((count == 2) && dst[2] & 0x80) { 267 dst[0] = 0xff; 268 dst[1] = 0xff; 269 } 270 #endif 271 ret = 0; 272 break; 273 274 case 8: 275 switch ((instruction&0xFF00)>>8) { 276 case 0x81: /* mov.w R0,@(disp,Rn) */ 277 src = (unsigned char*) ®s->regs[0]; 278 #if !defined(__LITTLE_ENDIAN__) 279 src += 2; 280 #endif 281 dst = (unsigned char*) *rm; /* called Rn in the spec */ 282 dst += (instruction&0x000F)<<1; 283 284 if (copy_to_user(dst, src, 2)) 285 goto fetch_fault; 286 ret = 0; 287 break; 288 289 case 0x85: /* mov.w @(disp,Rm),R0 */ 290 src = (unsigned char*) *rm; 291 src += (instruction&0x000F)<<1; 292 dst = (unsigned char*) ®s->regs[0]; 293 *(unsigned long*)dst = 0; 294 295 #if !defined(__LITTLE_ENDIAN__) 296 dst += 2; 297 #endif 298 299 if (copy_from_user(dst, src, 2)) 300 goto fetch_fault; 301 302 #ifdef __LITTLE_ENDIAN__ 303 if (dst[1] & 0x80) { 304 dst[2] = 0xff; 305 dst[3] = 0xff; 306 } 307 #else 308 if (dst[2] & 0x80) { 309 dst[0] = 0xff; 310 dst[1] = 0xff; 311 } 312 #endif 313 ret = 0; 314 break; 315 } 316 break; 317 } 318 return ret; 319 320 fetch_fault: 321 /* Argh. Address not only misaligned but also non-existent. 322 * Raise an EFAULT and see if it's trapped 323 */ 324 return die_if_no_fixup("Fault in unaligned fixup", regs, 0); 325 } 326 327 /* 328 * emulate the instruction in the delay slot 329 * - fetches the instruction from PC+2 330 */ 331 static inline int handle_unaligned_delayslot(struct pt_regs *regs) 332 { 333 u16 instruction; 334 335 if (copy_from_user(&instruction, (u16 *)(regs->pc+2), 2)) { 336 /* the instruction-fetch faulted */ 337 if (user_mode(regs)) 338 return -EFAULT; 339 340 /* kernel */ 341 die("delay-slot-insn faulting in handle_unaligned_delayslot", 342 regs, 0); 343 } 344 345 return handle_unaligned_ins(instruction,regs); 346 } 347 348 /* 349 * handle an instruction that does an unaligned memory access 350 * - have to be careful of branch delay-slot instructions that fault 351 * SH3: 352 * - if the branch would be taken PC points to the branch 353 * - if the branch would not be taken, PC points to delay-slot 354 * SH4: 355 * - PC always points to delayed branch 356 * - return 0 if handled, -EFAULT if failed (may not return if in kernel) 357 */ 358 359 /* Macros to determine offset from current PC for branch instructions */ 360 /* Explicit type coercion is used to force sign extension where needed */ 361 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) 362 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 363 364 /* 365 * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit 366 * opcodes.. 367 */ 368 #ifndef CONFIG_CPU_SH2A 369 static int handle_unaligned_notify_count = 10; 370 371 static int handle_unaligned_access(u16 instruction, struct pt_regs *regs) 372 { 373 u_int rm; 374 int ret, index; 375 376 index = (instruction>>8)&15; /* 0x0F00 */ 377 rm = regs->regs[index]; 378 379 /* shout about the first ten userspace fixups */ 380 if (user_mode(regs) && handle_unaligned_notify_count>0) { 381 handle_unaligned_notify_count--; 382 383 printk(KERN_NOTICE "Fixing up unaligned userspace access " 384 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 385 current->comm,current->pid,(u16*)regs->pc,instruction); 386 } 387 388 ret = -EFAULT; 389 switch (instruction&0xF000) { 390 case 0x0000: 391 if (instruction==0x000B) { 392 /* rts */ 393 ret = handle_unaligned_delayslot(regs); 394 if (ret==0) 395 regs->pc = regs->pr; 396 } 397 else if ((instruction&0x00FF)==0x0023) { 398 /* braf @Rm */ 399 ret = handle_unaligned_delayslot(regs); 400 if (ret==0) 401 regs->pc += rm + 4; 402 } 403 else if ((instruction&0x00FF)==0x0003) { 404 /* bsrf @Rm */ 405 ret = handle_unaligned_delayslot(regs); 406 if (ret==0) { 407 regs->pr = regs->pc + 4; 408 regs->pc += rm + 4; 409 } 410 } 411 else { 412 /* mov.[bwl] to/from memory via r0+rn */ 413 goto simple; 414 } 415 break; 416 417 case 0x1000: /* mov.l Rm,@(disp,Rn) */ 418 goto simple; 419 420 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ 421 goto simple; 422 423 case 0x4000: 424 if ((instruction&0x00FF)==0x002B) { 425 /* jmp @Rm */ 426 ret = handle_unaligned_delayslot(regs); 427 if (ret==0) 428 regs->pc = rm; 429 } 430 else if ((instruction&0x00FF)==0x000B) { 431 /* jsr @Rm */ 432 ret = handle_unaligned_delayslot(regs); 433 if (ret==0) { 434 regs->pr = regs->pc + 4; 435 regs->pc = rm; 436 } 437 } 438 else { 439 /* mov.[bwl] to/from memory via r0+rn */ 440 goto simple; 441 } 442 break; 443 444 case 0x5000: /* mov.l @(disp,Rm),Rn */ 445 goto simple; 446 447 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ 448 goto simple; 449 450 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ 451 switch (instruction&0x0F00) { 452 case 0x0100: /* mov.w R0,@(disp,Rm) */ 453 goto simple; 454 case 0x0500: /* mov.w @(disp,Rm),R0 */ 455 goto simple; 456 case 0x0B00: /* bf lab - no delayslot*/ 457 break; 458 case 0x0F00: /* bf/s lab */ 459 ret = handle_unaligned_delayslot(regs); 460 if (ret==0) { 461 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 462 if ((regs->sr & 0x00000001) != 0) 463 regs->pc += 4; /* next after slot */ 464 else 465 #endif 466 regs->pc += SH_PC_8BIT_OFFSET(instruction); 467 } 468 break; 469 case 0x0900: /* bt lab - no delayslot */ 470 break; 471 case 0x0D00: /* bt/s lab */ 472 ret = handle_unaligned_delayslot(regs); 473 if (ret==0) { 474 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 475 if ((regs->sr & 0x00000001) == 0) 476 regs->pc += 4; /* next after slot */ 477 else 478 #endif 479 regs->pc += SH_PC_8BIT_OFFSET(instruction); 480 } 481 break; 482 } 483 break; 484 485 case 0xA000: /* bra label */ 486 ret = handle_unaligned_delayslot(regs); 487 if (ret==0) 488 regs->pc += SH_PC_12BIT_OFFSET(instruction); 489 break; 490 491 case 0xB000: /* bsr label */ 492 ret = handle_unaligned_delayslot(regs); 493 if (ret==0) { 494 regs->pr = regs->pc + 4; 495 regs->pc += SH_PC_12BIT_OFFSET(instruction); 496 } 497 break; 498 } 499 return ret; 500 501 /* handle non-delay-slot instruction */ 502 simple: 503 ret = handle_unaligned_ins(instruction,regs); 504 if (ret==0) 505 regs->pc += instruction_size(instruction); 506 return ret; 507 } 508 #endif /* CONFIG_CPU_SH2A */ 509 510 #ifdef CONFIG_CPU_HAS_SR_RB 511 #define lookup_exception_vector(x) \ 512 __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x))) 513 #else 514 #define lookup_exception_vector(x) \ 515 __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x))) 516 #endif 517 518 /* 519 * Handle various address error exceptions: 520 * - instruction address error: 521 * misaligned PC 522 * PC >= 0x80000000 in user mode 523 * - data address error (read and write) 524 * misaligned data access 525 * access to >= 0x80000000 is user mode 526 * Unfortuntaly we can't distinguish between instruction address error 527 * and data address errors caused by read accesses. 528 */ 529 asmlinkage void do_address_error(struct pt_regs *regs, 530 unsigned long writeaccess, 531 unsigned long address) 532 { 533 unsigned long error_code = 0; 534 mm_segment_t oldfs; 535 siginfo_t info; 536 #ifndef CONFIG_CPU_SH2A 537 u16 instruction; 538 int tmp; 539 #endif 540 541 /* Intentional ifdef */ 542 #ifdef CONFIG_CPU_HAS_SR_RB 543 lookup_exception_vector(error_code); 544 #endif 545 546 oldfs = get_fs(); 547 548 if (user_mode(regs)) { 549 int si_code = BUS_ADRERR; 550 551 local_irq_enable(); 552 553 /* bad PC is not something we can fix */ 554 if (regs->pc & 1) { 555 si_code = BUS_ADRALN; 556 goto uspace_segv; 557 } 558 559 #ifndef CONFIG_CPU_SH2A 560 set_fs(USER_DS); 561 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) { 562 /* Argh. Fault on the instruction itself. 563 This should never happen non-SMP 564 */ 565 set_fs(oldfs); 566 goto uspace_segv; 567 } 568 569 tmp = handle_unaligned_access(instruction, regs); 570 set_fs(oldfs); 571 572 if (tmp==0) 573 return; /* sorted */ 574 #endif 575 576 uspace_segv: 577 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned " 578 "access (PC %lx PR %lx)\n", current->comm, regs->pc, 579 regs->pr); 580 581 info.si_signo = SIGBUS; 582 info.si_errno = 0; 583 info.si_code = si_code; 584 info.si_addr = (void *) address; 585 force_sig_info(SIGBUS, &info, current); 586 } else { 587 if (regs->pc & 1) 588 die("unaligned program counter", regs, error_code); 589 590 #ifndef CONFIG_CPU_SH2A 591 set_fs(KERNEL_DS); 592 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) { 593 /* Argh. Fault on the instruction itself. 594 This should never happen non-SMP 595 */ 596 set_fs(oldfs); 597 die("insn faulting in do_address_error", regs, 0); 598 } 599 600 handle_unaligned_access(instruction, regs); 601 set_fs(oldfs); 602 #else 603 printk(KERN_NOTICE "Killing process \"%s\" due to unaligned " 604 "access\n", current->comm); 605 606 force_sig(SIGSEGV, current); 607 #endif 608 } 609 } 610 611 #ifdef CONFIG_SH_DSP 612 /* 613 * SH-DSP support gerg@snapgear.com. 614 */ 615 int is_dsp_inst(struct pt_regs *regs) 616 { 617 unsigned short inst; 618 619 /* 620 * Safe guard if DSP mode is already enabled or we're lacking 621 * the DSP altogether. 622 */ 623 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) 624 return 0; 625 626 get_user(inst, ((unsigned short *) regs->pc)); 627 628 inst &= 0xf000; 629 630 /* Check for any type of DSP or support instruction */ 631 if ((inst == 0xf000) || (inst == 0x4000)) 632 return 1; 633 634 return 0; 635 } 636 #else 637 #define is_dsp_inst(regs) (0) 638 #endif /* CONFIG_SH_DSP */ 639 640 #ifdef CONFIG_CPU_SH2A 641 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5, 642 unsigned long r6, unsigned long r7, 643 struct pt_regs __regs) 644 { 645 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 646 siginfo_t info; 647 648 switch (r4) { 649 case TRAP_DIVZERO_ERROR: 650 info.si_code = FPE_INTDIV; 651 break; 652 case TRAP_DIVOVF_ERROR: 653 info.si_code = FPE_INTOVF; 654 break; 655 } 656 657 force_sig_info(SIGFPE, &info, current); 658 } 659 #endif 660 661 /* arch/sh/kernel/cpu/sh4/fpu.c */ 662 extern int do_fpu_inst(unsigned short, struct pt_regs *); 663 extern asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5, 664 unsigned long r6, unsigned long r7, struct pt_regs __regs); 665 666 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, 667 unsigned long r6, unsigned long r7, 668 struct pt_regs __regs) 669 { 670 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 671 unsigned long error_code; 672 struct task_struct *tsk = current; 673 674 #ifdef CONFIG_SH_FPU_EMU 675 unsigned short inst = 0; 676 int err; 677 678 get_user(inst, (unsigned short*)regs->pc); 679 680 err = do_fpu_inst(inst, regs); 681 if (!err) { 682 regs->pc += instruction_size(inst); 683 return; 684 } 685 /* not a FPU inst. */ 686 #endif 687 688 #ifdef CONFIG_SH_DSP 689 /* Check if it's a DSP instruction */ 690 if (is_dsp_inst(regs)) { 691 /* Enable DSP mode, and restart instruction. */ 692 regs->sr |= SR_DSP; 693 return; 694 } 695 #endif 696 697 lookup_exception_vector(error_code); 698 699 local_irq_enable(); 700 CHK_REMOTE_DEBUG(regs); 701 force_sig(SIGILL, tsk); 702 die_if_no_fixup("reserved instruction", regs, error_code); 703 } 704 705 #ifdef CONFIG_SH_FPU_EMU 706 static int emulate_branch(unsigned short inst, struct pt_regs* regs) 707 { 708 /* 709 * bfs: 8fxx: PC+=d*2+4; 710 * bts: 8dxx: PC+=d*2+4; 711 * bra: axxx: PC+=D*2+4; 712 * bsr: bxxx: PC+=D*2+4 after PR=PC+4; 713 * braf:0x23: PC+=Rn*2+4; 714 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4; 715 * jmp: 4x2b: PC=Rn; 716 * jsr: 4x0b: PC=Rn after PR=PC+4; 717 * rts: 000b: PC=PR; 718 */ 719 if ((inst & 0xfd00) == 0x8d00) { 720 regs->pc += SH_PC_8BIT_OFFSET(inst); 721 return 0; 722 } 723 724 if ((inst & 0xe000) == 0xa000) { 725 regs->pc += SH_PC_12BIT_OFFSET(inst); 726 return 0; 727 } 728 729 if ((inst & 0xf0df) == 0x0003) { 730 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; 731 return 0; 732 } 733 734 if ((inst & 0xf0df) == 0x400b) { 735 regs->pc = regs->regs[(inst & 0x0f00) >> 8]; 736 return 0; 737 } 738 739 if ((inst & 0xffff) == 0x000b) { 740 regs->pc = regs->pr; 741 return 0; 742 } 743 744 return 1; 745 } 746 #endif 747 748 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5, 749 unsigned long r6, unsigned long r7, 750 struct pt_regs __regs) 751 { 752 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 753 unsigned long error_code; 754 struct task_struct *tsk = current; 755 #ifdef CONFIG_SH_FPU_EMU 756 unsigned short inst = 0; 757 758 get_user(inst, (unsigned short *)regs->pc + 1); 759 if (!do_fpu_inst(inst, regs)) { 760 get_user(inst, (unsigned short *)regs->pc); 761 if (!emulate_branch(inst, regs)) 762 return; 763 /* fault in branch.*/ 764 } 765 /* not a FPU inst. */ 766 #endif 767 768 lookup_exception_vector(error_code); 769 770 local_irq_enable(); 771 CHK_REMOTE_DEBUG(regs); 772 force_sig(SIGILL, tsk); 773 die_if_no_fixup("illegal slot instruction", regs, error_code); 774 } 775 776 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, 777 unsigned long r6, unsigned long r7, 778 struct pt_regs __regs) 779 { 780 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 781 long ex; 782 783 lookup_exception_vector(ex); 784 die_if_kernel("exception", regs, ex); 785 } 786 787 #if defined(CONFIG_SH_STANDARD_BIOS) 788 void *gdb_vbr_vector; 789 790 static inline void __init gdb_vbr_init(void) 791 { 792 register unsigned long vbr; 793 794 /* 795 * Read the old value of the VBR register to initialise 796 * the vector through which debug and BIOS traps are 797 * delegated by the Linux trap handler. 798 */ 799 asm volatile("stc vbr, %0" : "=r" (vbr)); 800 801 gdb_vbr_vector = (void *)(vbr + 0x100); 802 printk("Setting GDB trap vector to 0x%08lx\n", 803 (unsigned long)gdb_vbr_vector); 804 } 805 #endif 806 807 void __init per_cpu_trap_init(void) 808 { 809 extern void *vbr_base; 810 811 #ifdef CONFIG_SH_STANDARD_BIOS 812 gdb_vbr_init(); 813 #endif 814 815 /* NOTE: The VBR value should be at P1 816 (or P2, virtural "fixed" address space). 817 It's definitely should not in physical address. */ 818 819 asm volatile("ldc %0, vbr" 820 : /* no output */ 821 : "r" (&vbr_base) 822 : "memory"); 823 } 824 825 void *set_exception_table_vec(unsigned int vec, void *handler) 826 { 827 extern void *exception_handling_table[]; 828 void *old_handler; 829 830 old_handler = exception_handling_table[vec]; 831 exception_handling_table[vec] = handler; 832 return old_handler; 833 } 834 835 extern asmlinkage void address_error_handler(unsigned long r4, unsigned long r5, 836 unsigned long r6, unsigned long r7, 837 struct pt_regs __regs); 838 839 void __init trap_init(void) 840 { 841 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst); 842 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst); 843 844 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ 845 defined(CONFIG_SH_FPU_EMU) 846 /* 847 * For SH-4 lacking an FPU, treat floating point instructions as 848 * reserved. They'll be handled in the math-emu case, or faulted on 849 * otherwise. 850 */ 851 set_exception_table_evt(0x800, do_reserved_inst); 852 set_exception_table_evt(0x820, do_illegal_slot_inst); 853 #elif defined(CONFIG_SH_FPU) 854 set_exception_table_evt(0x800, do_fpu_state_restore); 855 set_exception_table_evt(0x820, do_fpu_state_restore); 856 #endif 857 858 #ifdef CONFIG_CPU_SH2 859 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_handler); 860 #endif 861 #ifdef CONFIG_CPU_SH2A 862 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error); 863 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error); 864 #endif 865 866 /* Setup VBR for boot cpu */ 867 per_cpu_trap_init(); 868 } 869 870 #ifdef CONFIG_BUG 871 void handle_BUG(struct pt_regs *regs) 872 { 873 enum bug_trap_type tt; 874 tt = report_bug(regs->pc); 875 if (tt == BUG_TRAP_TYPE_WARN) { 876 regs->pc += 2; 877 return; 878 } 879 880 die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff); 881 } 882 883 int is_valid_bugaddr(unsigned long addr) 884 { 885 return addr >= PAGE_OFFSET; 886 } 887 #endif 888 889 void show_trace(struct task_struct *tsk, unsigned long *sp, 890 struct pt_regs *regs) 891 { 892 unsigned long addr; 893 894 if (regs && user_mode(regs)) 895 return; 896 897 printk("\nCall trace: "); 898 #ifdef CONFIG_KALLSYMS 899 printk("\n"); 900 #endif 901 902 while (!kstack_end(sp)) { 903 addr = *sp++; 904 if (kernel_text_address(addr)) 905 print_ip_sym(addr); 906 } 907 908 printk("\n"); 909 910 if (!tsk) 911 tsk = current; 912 913 debug_show_held_locks(tsk); 914 } 915 916 void show_stack(struct task_struct *tsk, unsigned long *sp) 917 { 918 unsigned long stack; 919 920 if (!tsk) 921 tsk = current; 922 if (tsk == current) 923 sp = (unsigned long *)current_stack_pointer; 924 else 925 sp = (unsigned long *)tsk->thread.sp; 926 927 stack = (unsigned long)sp; 928 dump_mem("Stack: ", stack, THREAD_SIZE + 929 (unsigned long)task_stack_page(tsk)); 930 show_trace(tsk, sp, NULL); 931 } 932 933 void dump_stack(void) 934 { 935 show_stack(NULL, NULL); 936 } 937 EXPORT_SYMBOL(dump_stack); 938