1 /* $Id: traps.c,v 1.17 2004/05/02 01:46:30 sugioka Exp $ 2 * 3 * linux/arch/sh/traps.c 4 * 5 * SuperH version: Copyright (C) 1999 Niibe Yutaka 6 * Copyright (C) 2000 Philipp Rumpf 7 * Copyright (C) 2000 David Howells 8 * Copyright (C) 2002, 2003 Paul Mundt 9 */ 10 11 /* 12 * 'Traps.c' handles hardware traps and faults after we have saved some 13 * state in 'entry.S'. 14 */ 15 #include <linux/sched.h> 16 #include <linux/kernel.h> 17 #include <linux/string.h> 18 #include <linux/errno.h> 19 #include <linux/ptrace.h> 20 #include <linux/timer.h> 21 #include <linux/mm.h> 22 #include <linux/smp.h> 23 #include <linux/smp_lock.h> 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/spinlock.h> 27 #include <linux/module.h> 28 #include <linux/kallsyms.h> 29 30 #include <asm/system.h> 31 #include <asm/uaccess.h> 32 #include <asm/io.h> 33 #include <asm/atomic.h> 34 #include <asm/processor.h> 35 #include <asm/sections.h> 36 37 #ifdef CONFIG_SH_KGDB 38 #include <asm/kgdb.h> 39 #define CHK_REMOTE_DEBUG(regs) \ 40 { \ 41 if ((kgdb_debug_hook != (kgdb_debug_hook_t *) NULL) && (!user_mode(regs))) \ 42 { \ 43 (*kgdb_debug_hook)(regs); \ 44 } \ 45 } 46 #else 47 #define CHK_REMOTE_DEBUG(regs) 48 #endif 49 50 #define DO_ERROR(trapnr, signr, str, name, tsk) \ 51 asmlinkage void do_##name(unsigned long r4, unsigned long r5, \ 52 unsigned long r6, unsigned long r7, \ 53 struct pt_regs regs) \ 54 { \ 55 unsigned long error_code; \ 56 \ 57 /* Check if it's a DSP instruction */ \ 58 if (is_dsp_inst(®s)) { \ 59 /* Enable DSP mode, and restart instruction. */ \ 60 regs.sr |= SR_DSP; \ 61 return; \ 62 } \ 63 \ 64 asm volatile("stc r2_bank, %0": "=r" (error_code)); \ 65 local_irq_enable(); \ 66 tsk->thread.error_code = error_code; \ 67 tsk->thread.trap_no = trapnr; \ 68 CHK_REMOTE_DEBUG(®s); \ 69 force_sig(signr, tsk); \ 70 die_if_no_fixup(str,®s,error_code); \ 71 } 72 73 #ifdef CONFIG_CPU_SH2 74 #define TRAP_RESERVED_INST 4 75 #define TRAP_ILLEGAL_SLOT_INST 6 76 #else 77 #define TRAP_RESERVED_INST 12 78 #define TRAP_ILLEGAL_SLOT_INST 13 79 #endif 80 81 /* 82 * These constants are for searching for possible module text 83 * segments. VMALLOC_OFFSET comes from mm/vmalloc.c; MODULE_RANGE is 84 * a guess of how much space is likely to be vmalloced. 85 */ 86 #define VMALLOC_OFFSET (8*1024*1024) 87 #define MODULE_RANGE (8*1024*1024) 88 89 spinlock_t die_lock; 90 91 void die(const char * str, struct pt_regs * regs, long err) 92 { 93 static int die_counter; 94 95 console_verbose(); 96 spin_lock_irq(&die_lock); 97 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); 98 CHK_REMOTE_DEBUG(regs); 99 show_regs(regs); 100 spin_unlock_irq(&die_lock); 101 do_exit(SIGSEGV); 102 } 103 104 static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err) 105 { 106 if (!user_mode(regs)) 107 die(str, regs, err); 108 } 109 110 static int handle_unaligned_notify_count = 10; 111 112 /* 113 * try and fix up kernelspace address errors 114 * - userspace errors just cause EFAULT to be returned, resulting in SEGV 115 * - kernel/userspace interfaces cause a jump to an appropriate handler 116 * - other kernel errors are bad 117 * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault 118 */ 119 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err) 120 { 121 if (!user_mode(regs)) 122 { 123 const struct exception_table_entry *fixup; 124 fixup = search_exception_tables(regs->pc); 125 if (fixup) { 126 regs->pc = fixup->fixup; 127 return 0; 128 } 129 die(str, regs, err); 130 } 131 return -EFAULT; 132 } 133 134 /* 135 * handle an instruction that does an unaligned memory access by emulating the 136 * desired behaviour 137 * - note that PC _may not_ point to the faulting instruction 138 * (if that instruction is in a branch delay slot) 139 * - return 0 if emulation okay, -EFAULT on existential error 140 */ 141 static int handle_unaligned_ins(u16 instruction, struct pt_regs *regs) 142 { 143 int ret, index, count; 144 unsigned long *rm, *rn; 145 unsigned char *src, *dst; 146 147 index = (instruction>>8)&15; /* 0x0F00 */ 148 rn = ®s->regs[index]; 149 150 index = (instruction>>4)&15; /* 0x00F0 */ 151 rm = ®s->regs[index]; 152 153 count = 1<<(instruction&3); 154 155 ret = -EFAULT; 156 switch (instruction>>12) { 157 case 0: /* mov.[bwl] to/from memory via r0+rn */ 158 if (instruction & 8) { 159 /* from memory */ 160 src = (unsigned char*) *rm; 161 src += regs->regs[0]; 162 dst = (unsigned char*) rn; 163 *(unsigned long*)dst = 0; 164 165 #ifdef __LITTLE_ENDIAN__ 166 if (copy_from_user(dst, src, count)) 167 goto fetch_fault; 168 169 if ((count == 2) && dst[1] & 0x80) { 170 dst[2] = 0xff; 171 dst[3] = 0xff; 172 } 173 #else 174 dst += 4-count; 175 176 if (__copy_user(dst, src, count)) 177 goto fetch_fault; 178 179 if ((count == 2) && dst[2] & 0x80) { 180 dst[0] = 0xff; 181 dst[1] = 0xff; 182 } 183 #endif 184 } else { 185 /* to memory */ 186 src = (unsigned char*) rm; 187 #if !defined(__LITTLE_ENDIAN__) 188 src += 4-count; 189 #endif 190 dst = (unsigned char*) *rn; 191 dst += regs->regs[0]; 192 193 if (copy_to_user(dst, src, count)) 194 goto fetch_fault; 195 } 196 ret = 0; 197 break; 198 199 case 1: /* mov.l Rm,@(disp,Rn) */ 200 src = (unsigned char*) rm; 201 dst = (unsigned char*) *rn; 202 dst += (instruction&0x000F)<<2; 203 204 if (copy_to_user(dst,src,4)) 205 goto fetch_fault; 206 ret = 0; 207 break; 208 209 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ 210 if (instruction & 4) 211 *rn -= count; 212 src = (unsigned char*) rm; 213 dst = (unsigned char*) *rn; 214 #if !defined(__LITTLE_ENDIAN__) 215 src += 4-count; 216 #endif 217 if (copy_to_user(dst, src, count)) 218 goto fetch_fault; 219 ret = 0; 220 break; 221 222 case 5: /* mov.l @(disp,Rm),Rn */ 223 src = (unsigned char*) *rm; 224 src += (instruction&0x000F)<<2; 225 dst = (unsigned char*) rn; 226 *(unsigned long*)dst = 0; 227 228 if (copy_from_user(dst,src,4)) 229 goto fetch_fault; 230 ret = 0; 231 break; 232 233 case 6: /* mov.[bwl] from memory, possibly with post-increment */ 234 src = (unsigned char*) *rm; 235 if (instruction & 4) 236 *rm += count; 237 dst = (unsigned char*) rn; 238 *(unsigned long*)dst = 0; 239 240 #ifdef __LITTLE_ENDIAN__ 241 if (copy_from_user(dst, src, count)) 242 goto fetch_fault; 243 244 if ((count == 2) && dst[1] & 0x80) { 245 dst[2] = 0xff; 246 dst[3] = 0xff; 247 } 248 #else 249 dst += 4-count; 250 251 if (copy_from_user(dst, src, count)) 252 goto fetch_fault; 253 254 if ((count == 2) && dst[2] & 0x80) { 255 dst[0] = 0xff; 256 dst[1] = 0xff; 257 } 258 #endif 259 ret = 0; 260 break; 261 262 case 8: 263 switch ((instruction&0xFF00)>>8) { 264 case 0x81: /* mov.w R0,@(disp,Rn) */ 265 src = (unsigned char*) ®s->regs[0]; 266 #if !defined(__LITTLE_ENDIAN__) 267 src += 2; 268 #endif 269 dst = (unsigned char*) *rm; /* called Rn in the spec */ 270 dst += (instruction&0x000F)<<1; 271 272 if (copy_to_user(dst, src, 2)) 273 goto fetch_fault; 274 ret = 0; 275 break; 276 277 case 0x85: /* mov.w @(disp,Rm),R0 */ 278 src = (unsigned char*) *rm; 279 src += (instruction&0x000F)<<1; 280 dst = (unsigned char*) ®s->regs[0]; 281 *(unsigned long*)dst = 0; 282 283 #if !defined(__LITTLE_ENDIAN__) 284 dst += 2; 285 #endif 286 287 if (copy_from_user(dst, src, 2)) 288 goto fetch_fault; 289 290 #ifdef __LITTLE_ENDIAN__ 291 if (dst[1] & 0x80) { 292 dst[2] = 0xff; 293 dst[3] = 0xff; 294 } 295 #else 296 if (dst[2] & 0x80) { 297 dst[0] = 0xff; 298 dst[1] = 0xff; 299 } 300 #endif 301 ret = 0; 302 break; 303 } 304 break; 305 } 306 return ret; 307 308 fetch_fault: 309 /* Argh. Address not only misaligned but also non-existent. 310 * Raise an EFAULT and see if it's trapped 311 */ 312 return die_if_no_fixup("Fault in unaligned fixup", regs, 0); 313 } 314 315 /* 316 * emulate the instruction in the delay slot 317 * - fetches the instruction from PC+2 318 */ 319 static inline int handle_unaligned_delayslot(struct pt_regs *regs) 320 { 321 u16 instruction; 322 323 if (copy_from_user(&instruction, (u16 *)(regs->pc+2), 2)) { 324 /* the instruction-fetch faulted */ 325 if (user_mode(regs)) 326 return -EFAULT; 327 328 /* kernel */ 329 die("delay-slot-insn faulting in handle_unaligned_delayslot", regs, 0); 330 } 331 332 return handle_unaligned_ins(instruction,regs); 333 } 334 335 /* 336 * handle an instruction that does an unaligned memory access 337 * - have to be careful of branch delay-slot instructions that fault 338 * SH3: 339 * - if the branch would be taken PC points to the branch 340 * - if the branch would not be taken, PC points to delay-slot 341 * SH4: 342 * - PC always points to delayed branch 343 * - return 0 if handled, -EFAULT if failed (may not return if in kernel) 344 */ 345 346 /* Macros to determine offset from current PC for branch instructions */ 347 /* Explicit type coercion is used to force sign extension where needed */ 348 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) 349 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 350 351 static int handle_unaligned_access(u16 instruction, struct pt_regs *regs) 352 { 353 u_int rm; 354 int ret, index; 355 356 index = (instruction>>8)&15; /* 0x0F00 */ 357 rm = regs->regs[index]; 358 359 /* shout about the first ten userspace fixups */ 360 if (user_mode(regs) && handle_unaligned_notify_count>0) { 361 handle_unaligned_notify_count--; 362 363 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 364 current->comm,current->pid,(u16*)regs->pc,instruction); 365 } 366 367 ret = -EFAULT; 368 switch (instruction&0xF000) { 369 case 0x0000: 370 if (instruction==0x000B) { 371 /* rts */ 372 ret = handle_unaligned_delayslot(regs); 373 if (ret==0) 374 regs->pc = regs->pr; 375 } 376 else if ((instruction&0x00FF)==0x0023) { 377 /* braf @Rm */ 378 ret = handle_unaligned_delayslot(regs); 379 if (ret==0) 380 regs->pc += rm + 4; 381 } 382 else if ((instruction&0x00FF)==0x0003) { 383 /* bsrf @Rm */ 384 ret = handle_unaligned_delayslot(regs); 385 if (ret==0) { 386 regs->pr = regs->pc + 4; 387 regs->pc += rm + 4; 388 } 389 } 390 else { 391 /* mov.[bwl] to/from memory via r0+rn */ 392 goto simple; 393 } 394 break; 395 396 case 0x1000: /* mov.l Rm,@(disp,Rn) */ 397 goto simple; 398 399 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ 400 goto simple; 401 402 case 0x4000: 403 if ((instruction&0x00FF)==0x002B) { 404 /* jmp @Rm */ 405 ret = handle_unaligned_delayslot(regs); 406 if (ret==0) 407 regs->pc = rm; 408 } 409 else if ((instruction&0x00FF)==0x000B) { 410 /* jsr @Rm */ 411 ret = handle_unaligned_delayslot(regs); 412 if (ret==0) { 413 regs->pr = regs->pc + 4; 414 regs->pc = rm; 415 } 416 } 417 else { 418 /* mov.[bwl] to/from memory via r0+rn */ 419 goto simple; 420 } 421 break; 422 423 case 0x5000: /* mov.l @(disp,Rm),Rn */ 424 goto simple; 425 426 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ 427 goto simple; 428 429 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ 430 switch (instruction&0x0F00) { 431 case 0x0100: /* mov.w R0,@(disp,Rm) */ 432 goto simple; 433 case 0x0500: /* mov.w @(disp,Rm),R0 */ 434 goto simple; 435 case 0x0B00: /* bf lab - no delayslot*/ 436 break; 437 case 0x0F00: /* bf/s lab */ 438 ret = handle_unaligned_delayslot(regs); 439 if (ret==0) { 440 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 441 if ((regs->sr & 0x00000001) != 0) 442 regs->pc += 4; /* next after slot */ 443 else 444 #endif 445 regs->pc += SH_PC_8BIT_OFFSET(instruction); 446 } 447 break; 448 case 0x0900: /* bt lab - no delayslot */ 449 break; 450 case 0x0D00: /* bt/s lab */ 451 ret = handle_unaligned_delayslot(regs); 452 if (ret==0) { 453 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 454 if ((regs->sr & 0x00000001) == 0) 455 regs->pc += 4; /* next after slot */ 456 else 457 #endif 458 regs->pc += SH_PC_8BIT_OFFSET(instruction); 459 } 460 break; 461 } 462 break; 463 464 case 0xA000: /* bra label */ 465 ret = handle_unaligned_delayslot(regs); 466 if (ret==0) 467 regs->pc += SH_PC_12BIT_OFFSET(instruction); 468 break; 469 470 case 0xB000: /* bsr label */ 471 ret = handle_unaligned_delayslot(regs); 472 if (ret==0) { 473 regs->pr = regs->pc + 4; 474 regs->pc += SH_PC_12BIT_OFFSET(instruction); 475 } 476 break; 477 } 478 return ret; 479 480 /* handle non-delay-slot instruction */ 481 simple: 482 ret = handle_unaligned_ins(instruction,regs); 483 if (ret==0) 484 regs->pc += 2; 485 return ret; 486 } 487 488 /* 489 * Handle various address error exceptions 490 */ 491 asmlinkage void do_address_error(struct pt_regs *regs, 492 unsigned long writeaccess, 493 unsigned long address) 494 { 495 unsigned long error_code; 496 mm_segment_t oldfs; 497 u16 instruction; 498 int tmp; 499 500 asm volatile("stc r2_bank,%0": "=r" (error_code)); 501 502 oldfs = get_fs(); 503 504 if (user_mode(regs)) { 505 local_irq_enable(); 506 current->thread.error_code = error_code; 507 current->thread.trap_no = (writeaccess) ? 8 : 7; 508 509 /* bad PC is not something we can fix */ 510 if (regs->pc & 1) 511 goto uspace_segv; 512 513 set_fs(USER_DS); 514 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) { 515 /* Argh. Fault on the instruction itself. 516 This should never happen non-SMP 517 */ 518 set_fs(oldfs); 519 goto uspace_segv; 520 } 521 522 tmp = handle_unaligned_access(instruction, regs); 523 set_fs(oldfs); 524 525 if (tmp==0) 526 return; /* sorted */ 527 528 uspace_segv: 529 printk(KERN_NOTICE "Killing process \"%s\" due to unaligned access\n", current->comm); 530 force_sig(SIGSEGV, current); 531 } else { 532 if (regs->pc & 1) 533 die("unaligned program counter", regs, error_code); 534 535 set_fs(KERNEL_DS); 536 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) { 537 /* Argh. Fault on the instruction itself. 538 This should never happen non-SMP 539 */ 540 set_fs(oldfs); 541 die("insn faulting in do_address_error", regs, 0); 542 } 543 544 handle_unaligned_access(instruction, regs); 545 set_fs(oldfs); 546 } 547 } 548 549 #ifdef CONFIG_SH_DSP 550 /* 551 * SH-DSP support gerg@snapgear.com. 552 */ 553 int is_dsp_inst(struct pt_regs *regs) 554 { 555 unsigned short inst; 556 557 /* 558 * Safe guard if DSP mode is already enabled or we're lacking 559 * the DSP altogether. 560 */ 561 if (!(cpu_data->flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) 562 return 0; 563 564 get_user(inst, ((unsigned short *) regs->pc)); 565 566 inst &= 0xf000; 567 568 /* Check for any type of DSP or support instruction */ 569 if ((inst == 0xf000) || (inst == 0x4000)) 570 return 1; 571 572 return 0; 573 } 574 #else 575 #define is_dsp_inst(regs) (0) 576 #endif /* CONFIG_SH_DSP */ 577 578 DO_ERROR(TRAP_RESERVED_INST, SIGILL, "reserved instruction", reserved_inst, current) 579 DO_ERROR(TRAP_ILLEGAL_SLOT_INST, SIGILL, "illegal slot instruction", illegal_slot_inst, current) 580 581 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, 582 unsigned long r6, unsigned long r7, 583 struct pt_regs regs) 584 { 585 long ex; 586 asm volatile("stc r2_bank, %0" : "=r" (ex)); 587 die_if_kernel("exception", ®s, ex); 588 } 589 590 #if defined(CONFIG_SH_STANDARD_BIOS) 591 void *gdb_vbr_vector; 592 593 static inline void __init gdb_vbr_init(void) 594 { 595 register unsigned long vbr; 596 597 /* 598 * Read the old value of the VBR register to initialise 599 * the vector through which debug and BIOS traps are 600 * delegated by the Linux trap handler. 601 */ 602 asm volatile("stc vbr, %0" : "=r" (vbr)); 603 604 gdb_vbr_vector = (void *)(vbr + 0x100); 605 printk("Setting GDB trap vector to 0x%08lx\n", 606 (unsigned long)gdb_vbr_vector); 607 } 608 #endif 609 610 void __init per_cpu_trap_init(void) 611 { 612 extern void *vbr_base; 613 614 #ifdef CONFIG_SH_STANDARD_BIOS 615 gdb_vbr_init(); 616 #endif 617 618 /* NOTE: The VBR value should be at P1 619 (or P2, virtural "fixed" address space). 620 It's definitely should not in physical address. */ 621 622 asm volatile("ldc %0, vbr" 623 : /* no output */ 624 : "r" (&vbr_base) 625 : "memory"); 626 } 627 628 void __init trap_init(void) 629 { 630 extern void *exception_handling_table[]; 631 632 exception_handling_table[TRAP_RESERVED_INST] 633 = (void *)do_reserved_inst; 634 exception_handling_table[TRAP_ILLEGAL_SLOT_INST] 635 = (void *)do_illegal_slot_inst; 636 637 #ifdef CONFIG_CPU_SH4 638 if (!(cpu_data->flags & CPU_HAS_FPU)) { 639 /* For SH-4 lacking an FPU, treat floating point instructions 640 as reserved. */ 641 /* entry 64 corresponds to EXPEVT=0x800 */ 642 exception_handling_table[64] = (void *)do_reserved_inst; 643 exception_handling_table[65] = (void *)do_illegal_slot_inst; 644 } 645 #endif 646 647 /* Setup VBR for boot cpu */ 648 per_cpu_trap_init(); 649 } 650 651 void show_stack(struct task_struct *tsk, unsigned long *sp) 652 { 653 unsigned long *stack, addr; 654 unsigned long module_start = VMALLOC_START; 655 unsigned long module_end = VMALLOC_END; 656 int i = 1; 657 658 if (tsk && !sp) { 659 sp = (unsigned long *)tsk->thread.sp; 660 } 661 662 if (!sp) { 663 __asm__ __volatile__ ( 664 "mov r15, %0\n\t" 665 "stc r7_bank, %1\n\t" 666 : "=r" (module_start), 667 "=r" (module_end) 668 ); 669 670 sp = (unsigned long *)module_start; 671 } 672 673 stack = sp; 674 675 printk("\nCall trace: "); 676 #ifdef CONFIG_KALLSYMS 677 printk("\n"); 678 #endif 679 680 while (!kstack_end(stack)) { 681 addr = *stack++; 682 if (((addr >= (unsigned long)_text) && 683 (addr <= (unsigned long)_etext)) || 684 ((addr >= module_start) && (addr <= module_end))) { 685 /* 686 * For 80-columns display, 6 entry is maximum. 687 * NOTE: '[<8c00abcd>] ' consumes 13 columns . 688 */ 689 #ifndef CONFIG_KALLSYMS 690 if (i && ((i % 6) == 0)) 691 printk("\n "); 692 #endif 693 printk("[<%08lx>] ", addr); 694 print_symbol("%s\n", addr); 695 i++; 696 } 697 } 698 699 printk("\n"); 700 } 701 702 void show_task(unsigned long *sp) 703 { 704 show_stack(NULL, sp); 705 } 706 707 void dump_stack(void) 708 { 709 show_stack(NULL, NULL); 710 } 711 EXPORT_SYMBOL(dump_stack); 712