1/* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $ 2 * 3 * arch/sh/kernel/head.S 4 * 5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 * 11 * Head.S contains the SH exception handlers and startup code. 12 */ 13#include <linux/init.h> 14#include <linux/linkage.h> 15#include <asm/thread_info.h> 16 17#ifdef CONFIG_CPU_SH4A 18#define SYNCO() synco 19 20#define PREFI(label, reg) \ 21 mov.l label, reg; \ 22 prefi @reg 23#else 24#define SYNCO() 25#define PREFI(label, reg) 26#endif 27 28 .section .empty_zero_page, "aw" 29ENTRY(empty_zero_page) 30 .long 1 /* MOUNT_ROOT_RDONLY */ 31 .long 0 /* RAMDISK_FLAGS */ 32 .long 0x0200 /* ORIG_ROOT_DEV */ 33 .long 1 /* LOADER_TYPE */ 34 .long 0x00000000 /* INITRD_START */ 35 .long 0x00000000 /* INITRD_SIZE */ 36#ifdef CONFIG_32BIT 37 .long 0x53453f00 + 32 /* "SE?" = 32 bit */ 38#else 39 .long 0x53453f00 + 29 /* "SE?" = 29 bit */ 40#endif 411: 42 .skip PAGE_SIZE - empty_zero_page - 1b 43 44 __HEAD 45 46/* 47 * Condition at the entry of _stext: 48 * 49 * BSC has already been initialized. 50 * INTC may or may not be initialized. 51 * VBR may or may not be initialized. 52 * MMU may or may not be initialized. 53 * Cache may or may not be initialized. 54 * Hardware (including on-chip modules) may or may not be initialized. 55 * 56 */ 57ENTRY(_stext) 58 ! Initialize Status Register 59 mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF 60 ldc r0, sr 61 ! Initialize global interrupt mask 62#ifdef CONFIG_CPU_HAS_SR_RB 63 mov #0, r0 64 ldc r0, r6_bank 65#endif 66 67 /* 68 * Prefetch if possible to reduce cache miss penalty. 69 * 70 * We do this early on for SH-4A as a micro-optimization, 71 * as later on we will have speculative execution enabled 72 * and this will become less of an issue. 73 */ 74 PREFI(5f, r0) 75 PREFI(6f, r0) 76 77 ! 78 mov.l 2f, r0 79 mov r0, r15 ! Set initial r15 (stack pointer) 80#ifdef CONFIG_CPU_HAS_SR_RB 81 mov.l 7f, r0 82 ldc r0, r7_bank ! ... and initial thread_info 83#endif 84 85#ifndef CONFIG_SH_NO_BSS_INIT 86 /* 87 * Don't clear BSS if running on slow platforms such as an RTL simulation, 88 * remote memory via SHdebug link, etc. For these the memory can be guaranteed 89 * to be all zero on boot anyway. 90 */ 91 ! Clear BSS area 92#ifdef CONFIG_SMP 93 mov.l 3f, r0 94 cmp/eq #0, r0 ! skip clear if set to zero 95 bt 10f 96#endif 97 98 mov.l 3f, r1 99 add #4, r1 100 mov.l 4f, r2 101 mov #0, r0 1029: cmp/hs r2, r1 103 bf/s 9b ! while (r1 < r2) 104 mov.l r0,@-r2 105 10610: 107#endif 108 109 ! Additional CPU initialization 110 mov.l 6f, r0 111 jsr @r0 112 nop 113 114 SYNCO() ! Wait for pending instructions.. 115 116 ! Start kernel 117 mov.l 5f, r0 118 jmp @r0 119 nop 120 121 .balign 4 122#if defined(CONFIG_CPU_SH2) 1231: .long 0x000000F0 ! IMASK=0xF 124#else 1251: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF 126#endif 127ENTRY(stack_start) 1282: .long init_thread_union+THREAD_SIZE 1293: .long __bss_start 1304: .long _end 1315: .long start_kernel 1326: .long sh_cpu_init 1337: .long init_thread_union 134