1 /* 2 * Disassemble SuperH instructions. 3 * 4 * Copyright (C) 1999 kaz Kojima 5 * Copyright (C) 2008 Paul Mundt 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/uaccess.h> 14 15 #include <asm/ptrace.h> 16 17 /* 18 * Format of an instruction in memory. 19 */ 20 typedef enum { 21 HEX_0, HEX_1, HEX_2, HEX_3, HEX_4, HEX_5, HEX_6, HEX_7, 22 HEX_8, HEX_9, HEX_A, HEX_B, HEX_C, HEX_D, HEX_E, HEX_F, 23 REG_N, REG_M, REG_NM, REG_B, 24 BRANCH_12, BRANCH_8, 25 DISP_8, DISP_4, 26 IMM_4, IMM_4BY2, IMM_4BY4, PCRELIMM_8BY2, PCRELIMM_8BY4, 27 IMM_8, IMM_8BY2, IMM_8BY4, 28 } sh_nibble_type; 29 30 typedef enum { 31 A_END, A_BDISP12, A_BDISP8, 32 A_DEC_M, A_DEC_N, 33 A_DISP_GBR, A_DISP_PC, A_DISP_REG_M, A_DISP_REG_N, 34 A_GBR, 35 A_IMM, 36 A_INC_M, A_INC_N, 37 A_IND_M, A_IND_N, A_IND_R0_REG_M, A_IND_R0_REG_N, 38 A_MACH, A_MACL, 39 A_PR, A_R0, A_R0_GBR, A_REG_M, A_REG_N, A_REG_B, 40 A_SR, A_VBR, A_SSR, A_SPC, A_SGR, A_DBR, 41 F_REG_N, F_REG_M, D_REG_N, D_REG_M, 42 X_REG_N, /* Only used for argument parsing */ 43 X_REG_M, /* Only used for argument parsing */ 44 DX_REG_N, DX_REG_M, V_REG_N, V_REG_M, 45 FD_REG_N, 46 XMTRX_M4, 47 F_FR0, 48 FPUL_N, FPUL_M, FPSCR_N, FPSCR_M, 49 } sh_arg_type; 50 51 static struct sh_opcode_info { 52 char *name; 53 sh_arg_type arg[7]; 54 sh_nibble_type nibbles[4]; 55 } sh_table[] = { 56 {"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}}, 57 {"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}}, 58 {"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}}, 59 {"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}}, 60 {"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}}, 61 {"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}}, 62 {"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}}, 63 {"bra",{A_BDISP12},{HEX_A,BRANCH_12}}, 64 {"bsr",{A_BDISP12},{HEX_B,BRANCH_12}}, 65 {"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}}, 66 {"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}}, 67 {"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, 68 {"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, 69 {"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, 70 {"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, 71 {"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}}, 72 {"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}}, 73 {"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}}, 74 {"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}}, 75 {"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}}, 76 {"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}}, 77 {"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}}, 78 {"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}}, 79 {"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}}, 80 {"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}}, 81 {"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}}, 82 {"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}}, 83 {"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}}, 84 {"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}}, 85 {"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}}, 86 {"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}}, 87 {"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}}, 88 {"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}}, 89 {"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}}, 90 {"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}}, 91 {"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}}, 92 {"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}}, 93 {"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}}, 94 {"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}}, 95 {"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}}, 96 {"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}}, 97 {"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}}, 98 {"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}}, 99 {"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}}, 100 {"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}}, 101 {"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}}, 102 {"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}}, 103 {"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}}, 104 {"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}}, 105 {"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}}, 106 {"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}}, 107 {"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}}, 108 {"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}}, 109 {"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}}, 110 {"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}}, 111 {"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}}, 112 {"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}}, 113 {"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}}, 114 {"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}}, 115 {"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}}, 116 {"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}}, 117 {"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}}, 118 {"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}}, 119 {"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}}, 120 {"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}}, 121 {"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}}, 122 {"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}}, 123 {"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}}, 124 {"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}}, 125 {"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}}, 126 {"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}}, 127 {"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}}, 128 {"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}}, 129 {"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}}, 130 {"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}}, 131 {"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}}, 132 {"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}}, 133 {"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}}, 134 {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}}, 135 {"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}}, 136 {"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}}, 137 {"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}}, 138 {"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}}, 139 {"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}}, 140 {"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}}, 141 {"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}}, 142 {"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}}, 143 {"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}}, 144 {"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}}, 145 {"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}}, 146 {"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}}, 147 {"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}}, 148 {"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}}, 149 {"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}}, 150 {"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}}, 151 {"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}}, 152 {"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}}, 153 {"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}}, 154 {"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}}, 155 {"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}}, 156 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, 157 {"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}}, 158 {"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}}, 159 {"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}}, 160 {"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}}, 161 {"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}}, 162 {"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}}, 163 {"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}}, 164 {"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}}, 165 {"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}}, 166 {"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}}, 167 {"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}}, 168 {"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}}, 169 {"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}}, 170 {"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}}, 171 {"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}}, 172 {"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}}, 173 {"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}}, 174 {"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}}, 175 {"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}}, 176 {"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}}, 177 {"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}}, 178 {"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}}, 179 {"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}}, 180 {"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}}, 181 {"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}}, 182 {"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}}, 183 {"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}}, 184 {"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}}, 185 {"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}}, 186 {"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}}, 187 {"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}}, 188 {"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}}, 189 {"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}}, 190 {"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}}, 191 {"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}}, 192 {"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}}, 193 {"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}}, 194 {"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}}, 195 {"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}}, 196 {"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}}, 197 {"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}}, 198 {"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}}, 199 {"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}}, 200 {"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}}, 201 {"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}}, 202 {"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}}, 203 {"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}}, 204 {"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}}, 205 {"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}}, 206 {"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}}, 207 {"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}}, 208 {"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}}, 209 {"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}}, 210 {"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}}, 211 {"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}}, 212 {"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}}, 213 {"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}}, 214 {"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}}, 215 {"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}}, 216 {"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}}, 217 {"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}}, 218 {"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}}, 219 {"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}}, 220 {"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}}, 221 {"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}}, 222 {"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}}, 223 {"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}}, 224 {"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}}, 225 {"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}}, 226 {"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}}, 227 {"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}}, 228 {"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}}, 229 {"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}}, 230 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, 231 {"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}}, 232 {"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}}, 233 {"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}}, 234 {"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}}, 235 {"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}}, 236 {"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}}, 237 {"fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}}, 238 {"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, 239 {"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, 240 {"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, 241 {"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, 242 {"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, 243 {"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, 244 {"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}}, 245 {"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}}, 246 {"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, 247 {"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, 248 {"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}}, 249 {"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}}, 250 {"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}}, 251 {"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}}, 252 {"float",{FPUL_M,FD_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}}, 253 {"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}}, 254 {"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, 255 {"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, 256 {"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, 257 {"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, 258 {"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, 259 {"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, 260 {"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, 261 {"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, 262 {"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, 263 {"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, 264 {"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, 265 {"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, 266 {"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, 267 {"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, 268 {"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, 269 {"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, 270 {"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, 271 {"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, 272 {"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, 273 {"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, 274 {"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, 275 {"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, 276 {"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, 277 {"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, 278 {"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, 279 {"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, 280 {"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, 281 {"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, 282 {"fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}}, 283 {"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}}, 284 {"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}}, 285 {"fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}}, 286 {"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}}, 287 {"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, 288 {"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, 289 {"ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}}, 290 {"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}}, 291 { 0 }, 292 }; 293 294 static void print_sh_insn(u32 memaddr, u16 insn) 295 { 296 int relmask = ~0; 297 int nibs[4] = { (insn >> 12) & 0xf, (insn >> 8) & 0xf, (insn >> 4) & 0xf, insn & 0xf}; 298 int lastsp; 299 struct sh_opcode_info *op = sh_table; 300 301 for (; op->name; op++) { 302 int n; 303 int imm = 0; 304 int rn = 0; 305 int rm = 0; 306 int rb = 0; 307 int disp_pc; 308 int disp_pc_addr = 0; 309 310 for (n = 0; n < 4; n++) { 311 int i = op->nibbles[n]; 312 313 if (i < 16) { 314 if (nibs[n] == i) 315 continue; 316 goto fail; 317 } 318 switch (i) { 319 case BRANCH_8: 320 imm = (nibs[2] << 4) | (nibs[3]); 321 if (imm & 0x80) 322 imm |= ~0xff; 323 imm = ((char)imm) * 2 + 4 ; 324 goto ok; 325 case BRANCH_12: 326 imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); 327 if (imm & 0x800) 328 imm |= ~0xfff; 329 imm = imm * 2 + 4; 330 goto ok; 331 case IMM_4: 332 imm = nibs[3]; 333 goto ok; 334 case IMM_4BY2: 335 imm = nibs[3] <<1; 336 goto ok; 337 case IMM_4BY4: 338 imm = nibs[3] <<2; 339 goto ok; 340 case IMM_8: 341 imm = (nibs[2] << 4) | nibs[3]; 342 goto ok; 343 case PCRELIMM_8BY2: 344 imm = ((nibs[2] << 4) | nibs[3]) <<1; 345 relmask = ~1; 346 goto ok; 347 case PCRELIMM_8BY4: 348 imm = ((nibs[2] << 4) | nibs[3]) <<2; 349 relmask = ~3; 350 goto ok; 351 case IMM_8BY2: 352 imm = ((nibs[2] << 4) | nibs[3]) <<1; 353 goto ok; 354 case IMM_8BY4: 355 imm = ((nibs[2] << 4) | nibs[3]) <<2; 356 goto ok; 357 case DISP_8: 358 imm = (nibs[2] << 4) | (nibs[3]); 359 goto ok; 360 case DISP_4: 361 imm = nibs[3]; 362 goto ok; 363 case REG_N: 364 rn = nibs[n]; 365 break; 366 case REG_M: 367 rm = nibs[n]; 368 break; 369 case REG_NM: 370 rn = (nibs[n] & 0xc) >> 2; 371 rm = (nibs[n] & 0x3); 372 break; 373 case REG_B: 374 rb = nibs[n] & 0x07; 375 break; 376 default: 377 return; 378 } 379 } 380 381 ok: 382 printk("%-8s ", op->name); 383 lastsp = (op->arg[0] == A_END); 384 disp_pc = 0; 385 for (n = 0; n < 6 && op->arg[n] != A_END; n++) { 386 if (n && op->arg[1] != A_END) 387 printk(", "); 388 switch (op->arg[n]) { 389 case A_IMM: 390 printk("#%d", (char)(imm)); 391 break; 392 case A_R0: 393 printk("r0"); 394 break; 395 case A_REG_N: 396 printk("r%d", rn); 397 break; 398 case A_INC_N: 399 printk("@r%d+", rn); 400 break; 401 case A_DEC_N: 402 printk("@-r%d", rn); 403 break; 404 case A_IND_N: 405 printk("@r%d", rn); 406 break; 407 case A_DISP_REG_N: 408 printk("@(%d,r%d)", imm, rn); 409 break; 410 case A_REG_M: 411 printk("r%d", rm); 412 break; 413 case A_INC_M: 414 printk("@r%d+", rm); 415 break; 416 case A_DEC_M: 417 printk("@-r%d", rm); 418 break; 419 case A_IND_M: 420 printk("@r%d", rm); 421 break; 422 case A_DISP_REG_M: 423 printk("@(%d,r%d)", imm, rm); 424 break; 425 case A_REG_B: 426 printk("r%d_bank", rb); 427 break; 428 case A_DISP_PC: 429 disp_pc = 1; 430 disp_pc_addr = imm + 4 + (memaddr & relmask); 431 printk("%08x <%pS>", disp_pc_addr, 432 (void *)disp_pc_addr); 433 break; 434 case A_IND_R0_REG_N: 435 printk("@(r0,r%d)", rn); 436 break; 437 case A_IND_R0_REG_M: 438 printk("@(r0,r%d)", rm); 439 break; 440 case A_DISP_GBR: 441 printk("@(%d,gbr)",imm); 442 break; 443 case A_R0_GBR: 444 printk("@(r0,gbr)"); 445 break; 446 case A_BDISP12: 447 case A_BDISP8: 448 printk("%08x", imm + memaddr); 449 break; 450 case A_SR: 451 printk("sr"); 452 break; 453 case A_GBR: 454 printk("gbr"); 455 break; 456 case A_VBR: 457 printk("vbr"); 458 break; 459 case A_SSR: 460 printk("ssr"); 461 break; 462 case A_SPC: 463 printk("spc"); 464 break; 465 case A_MACH: 466 printk("mach"); 467 break; 468 case A_MACL: 469 printk("macl"); 470 break; 471 case A_PR: 472 printk("pr"); 473 break; 474 case A_SGR: 475 printk("sgr"); 476 break; 477 case A_DBR: 478 printk("dbr"); 479 break; 480 case FD_REG_N: 481 if (0) 482 goto d_reg_n; 483 case F_REG_N: 484 printk("fr%d", rn); 485 break; 486 case F_REG_M: 487 printk("fr%d", rm); 488 break; 489 case DX_REG_N: 490 if (rn & 1) { 491 printk("xd%d", rn & ~1); 492 break; 493 } 494 d_reg_n: 495 case D_REG_N: 496 printk("dr%d", rn); 497 break; 498 case DX_REG_M: 499 if (rm & 1) { 500 printk("xd%d", rm & ~1); 501 break; 502 } 503 case D_REG_M: 504 printk("dr%d", rm); 505 break; 506 case FPSCR_M: 507 case FPSCR_N: 508 printk("fpscr"); 509 break; 510 case FPUL_M: 511 case FPUL_N: 512 printk("fpul"); 513 break; 514 case F_FR0: 515 printk("fr0"); 516 break; 517 case V_REG_N: 518 printk("fv%d", rn*4); 519 break; 520 case V_REG_M: 521 printk("fv%d", rm*4); 522 break; 523 case XMTRX_M4: 524 printk("xmtrx"); 525 break; 526 default: 527 return; 528 } 529 } 530 531 if (disp_pc && strcmp(op->name, "mova") != 0) { 532 u32 val; 533 534 if (relmask == ~1) 535 __get_user(val, (u16 *)disp_pc_addr); 536 else 537 __get_user(val, (u32 *)disp_pc_addr); 538 539 printk(" ! %08x <%pS>", val, (void *)val); 540 } 541 542 return; 543 fail: 544 ; 545 546 } 547 548 printk(".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); 549 } 550 551 void show_code(struct pt_regs *regs) 552 { 553 unsigned short *pc = (unsigned short *)regs->pc; 554 long i; 555 556 if (regs->pc & 0x1) 557 return; 558 559 printk("Code:\n"); 560 561 for (i = -3 ; i < 6 ; i++) { 562 unsigned short insn; 563 564 if (__get_user(insn, pc + i)) { 565 printk(" (Bad address in pc)\n"); 566 break; 567 } 568 569 printk("%s%08lx: ", (i ? " ": "->"), (unsigned long)(pc + i)); 570 print_sh_insn((unsigned long)(pc + i), insn); 571 printk("\n"); 572 } 573 574 printk("\n"); 575 } 576