1 /* 2 * SH7780 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/io.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_timer.h> 16 #include <asm/dma-sh.h> 17 18 static struct sh_timer_config tmu0_platform_data = { 19 .name = "TMU0", 20 .channel_offset = 0x04, 21 .timer_bit = 0, 22 .clk = "peripheral_clk", 23 .clockevent_rating = 200, 24 }; 25 26 static struct resource tmu0_resources[] = { 27 [0] = { 28 .name = "TMU0", 29 .start = 0xffd80008, 30 .end = 0xffd80013, 31 .flags = IORESOURCE_MEM, 32 }, 33 [1] = { 34 .start = 28, 35 .flags = IORESOURCE_IRQ, 36 }, 37 }; 38 39 static struct platform_device tmu0_device = { 40 .name = "sh_tmu", 41 .id = 0, 42 .dev = { 43 .platform_data = &tmu0_platform_data, 44 }, 45 .resource = tmu0_resources, 46 .num_resources = ARRAY_SIZE(tmu0_resources), 47 }; 48 49 static struct sh_timer_config tmu1_platform_data = { 50 .name = "TMU1", 51 .channel_offset = 0x10, 52 .timer_bit = 1, 53 .clk = "peripheral_clk", 54 .clocksource_rating = 200, 55 }; 56 57 static struct resource tmu1_resources[] = { 58 [0] = { 59 .name = "TMU1", 60 .start = 0xffd80014, 61 .end = 0xffd8001f, 62 .flags = IORESOURCE_MEM, 63 }, 64 [1] = { 65 .start = 29, 66 .flags = IORESOURCE_IRQ, 67 }, 68 }; 69 70 static struct platform_device tmu1_device = { 71 .name = "sh_tmu", 72 .id = 1, 73 .dev = { 74 .platform_data = &tmu1_platform_data, 75 }, 76 .resource = tmu1_resources, 77 .num_resources = ARRAY_SIZE(tmu1_resources), 78 }; 79 80 static struct sh_timer_config tmu2_platform_data = { 81 .name = "TMU2", 82 .channel_offset = 0x1c, 83 .timer_bit = 2, 84 .clk = "peripheral_clk", 85 }; 86 87 static struct resource tmu2_resources[] = { 88 [0] = { 89 .name = "TMU2", 90 .start = 0xffd80020, 91 .end = 0xffd8002f, 92 .flags = IORESOURCE_MEM, 93 }, 94 [1] = { 95 .start = 30, 96 .flags = IORESOURCE_IRQ, 97 }, 98 }; 99 100 static struct platform_device tmu2_device = { 101 .name = "sh_tmu", 102 .id = 2, 103 .dev = { 104 .platform_data = &tmu2_platform_data, 105 }, 106 .resource = tmu2_resources, 107 .num_resources = ARRAY_SIZE(tmu2_resources), 108 }; 109 110 static struct sh_timer_config tmu3_platform_data = { 111 .name = "TMU3", 112 .channel_offset = 0x04, 113 .timer_bit = 0, 114 .clk = "peripheral_clk", 115 }; 116 117 static struct resource tmu3_resources[] = { 118 [0] = { 119 .name = "TMU3", 120 .start = 0xffdc0008, 121 .end = 0xffdc0013, 122 .flags = IORESOURCE_MEM, 123 }, 124 [1] = { 125 .start = 96, 126 .flags = IORESOURCE_IRQ, 127 }, 128 }; 129 130 static struct platform_device tmu3_device = { 131 .name = "sh_tmu", 132 .id = 3, 133 .dev = { 134 .platform_data = &tmu3_platform_data, 135 }, 136 .resource = tmu3_resources, 137 .num_resources = ARRAY_SIZE(tmu3_resources), 138 }; 139 140 static struct sh_timer_config tmu4_platform_data = { 141 .name = "TMU4", 142 .channel_offset = 0x10, 143 .timer_bit = 1, 144 .clk = "peripheral_clk", 145 }; 146 147 static struct resource tmu4_resources[] = { 148 [0] = { 149 .name = "TMU4", 150 .start = 0xffdc0014, 151 .end = 0xffdc001f, 152 .flags = IORESOURCE_MEM, 153 }, 154 [1] = { 155 .start = 97, 156 .flags = IORESOURCE_IRQ, 157 }, 158 }; 159 160 static struct platform_device tmu4_device = { 161 .name = "sh_tmu", 162 .id = 4, 163 .dev = { 164 .platform_data = &tmu4_platform_data, 165 }, 166 .resource = tmu4_resources, 167 .num_resources = ARRAY_SIZE(tmu4_resources), 168 }; 169 170 static struct sh_timer_config tmu5_platform_data = { 171 .name = "TMU5", 172 .channel_offset = 0x1c, 173 .timer_bit = 2, 174 .clk = "peripheral_clk", 175 }; 176 177 static struct resource tmu5_resources[] = { 178 [0] = { 179 .name = "TMU5", 180 .start = 0xffdc0020, 181 .end = 0xffdc002b, 182 .flags = IORESOURCE_MEM, 183 }, 184 [1] = { 185 .start = 98, 186 .flags = IORESOURCE_IRQ, 187 }, 188 }; 189 190 static struct platform_device tmu5_device = { 191 .name = "sh_tmu", 192 .id = 5, 193 .dev = { 194 .platform_data = &tmu5_platform_data, 195 }, 196 .resource = tmu5_resources, 197 .num_resources = ARRAY_SIZE(tmu5_resources), 198 }; 199 200 static struct resource rtc_resources[] = { 201 [0] = { 202 .start = 0xffe80000, 203 .end = 0xffe80000 + 0x58 - 1, 204 .flags = IORESOURCE_IO, 205 }, 206 [1] = { 207 /* Shared Period/Carry/Alarm IRQ */ 208 .start = 20, 209 .flags = IORESOURCE_IRQ, 210 }, 211 }; 212 213 static struct platform_device rtc_device = { 214 .name = "sh-rtc", 215 .id = -1, 216 .num_resources = ARRAY_SIZE(rtc_resources), 217 .resource = rtc_resources, 218 }; 219 220 static struct plat_sci_port sci_platform_data[] = { 221 { 222 .mapbase = 0xffe00000, 223 .flags = UPF_BOOT_AUTOCONF, 224 .type = PORT_SCIF, 225 .irqs = { 40, 40, 40, 40 }, 226 }, { 227 .mapbase = 0xffe10000, 228 .flags = UPF_BOOT_AUTOCONF, 229 .type = PORT_SCIF, 230 .irqs = { 76, 76, 76, 76 }, 231 }, { 232 .flags = 0, 233 } 234 }; 235 236 static struct platform_device sci_device = { 237 .name = "sh-sci", 238 .id = -1, 239 .dev = { 240 .platform_data = sci_platform_data, 241 }, 242 }; 243 244 static struct sh_dmae_pdata dma_platform_data = { 245 .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1), 246 }; 247 248 static struct platform_device dma_device = { 249 .name = "sh-dma-engine", 250 .id = -1, 251 .dev = { 252 .platform_data = &dma_platform_data, 253 }, 254 }; 255 256 static struct platform_device *sh7780_devices[] __initdata = { 257 &tmu0_device, 258 &tmu1_device, 259 &tmu2_device, 260 &tmu3_device, 261 &tmu4_device, 262 &tmu5_device, 263 &rtc_device, 264 &sci_device, 265 &dma_device, 266 }; 267 268 static int __init sh7780_devices_setup(void) 269 { 270 return platform_add_devices(sh7780_devices, 271 ARRAY_SIZE(sh7780_devices)); 272 } 273 arch_initcall(sh7780_devices_setup); 274 275 static struct platform_device *sh7780_early_devices[] __initdata = { 276 &tmu0_device, 277 &tmu1_device, 278 &tmu2_device, 279 &tmu3_device, 280 &tmu4_device, 281 &tmu5_device, 282 }; 283 284 void __init plat_early_device_setup(void) 285 { 286 early_platform_add_devices(sh7780_early_devices, 287 ARRAY_SIZE(sh7780_early_devices)); 288 } 289 290 enum { 291 UNUSED = 0, 292 293 /* interrupt sources */ 294 295 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 296 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 297 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 298 IRL_HHLL, IRL_HHLH, IRL_HHHL, 299 300 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 301 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 302 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC, 303 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5, 304 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO, 305 306 /* interrupt groups */ 307 308 TMU012, TMU345, 309 }; 310 311 static struct intc_vect vectors[] __initdata = { 312 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 313 INTC_VECT(RTC, 0x4c0), 314 INTC_VECT(WDT, 0x560), 315 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 316 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 317 INTC_VECT(HUDI, 0x600), 318 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), 319 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), 320 INTC_VECT(DMAC0, 0x6c0), 321 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720), 322 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760), 323 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), 324 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0), 325 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980), 326 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 327 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 328 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0), 329 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0), 330 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20), 331 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0), 332 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0), 333 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80), 334 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20), 335 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60), 336 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0), 337 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0), 338 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 339 INTC_VECT(TMU5, 0xe40), 340 INTC_VECT(SSI, 0xe80), 341 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20), 342 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60), 343 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0), 344 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0), 345 }; 346 347 static struct intc_group groups[] __initdata = { 348 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 349 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 350 }; 351 352 static struct intc_mask_reg mask_registers[] __initdata = { 353 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 354 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL, 355 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB, 356 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0, 357 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, 358 }; 359 360 static struct intc_prio_reg prio_registers[] __initdata = { 361 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, 362 TMU2, TMU2_TICPI } }, 363 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, 364 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, 365 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } }, 366 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC, 367 PCISERR, PCIINTA, } }, 368 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, 369 PCIINTD, PCIC5 } }, 370 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } }, 371 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } }, 372 }; 373 374 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, 375 mask_registers, prio_registers, NULL); 376 377 /* Support for external interrupt pins in IRQ mode */ 378 379 static struct intc_vect irq_vectors[] __initdata = { 380 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 381 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 382 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 383 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 384 }; 385 386 static struct intc_mask_reg irq_mask_registers[] __initdata = { 387 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 388 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 389 }; 390 391 static struct intc_prio_reg irq_prio_registers[] __initdata = { 392 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 393 IRQ4, IRQ5, IRQ6, IRQ7 } }, 394 }; 395 396 static struct intc_sense_reg irq_sense_registers[] __initdata = { 397 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 398 IRQ4, IRQ5, IRQ6, IRQ7 } }, 399 }; 400 401 static struct intc_mask_reg irq_ack_registers[] __initdata = { 402 { 0xffd00024, 0, 32, /* INTREQ */ 403 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 404 }; 405 406 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors, 407 NULL, irq_mask_registers, irq_prio_registers, 408 irq_sense_registers, irq_ack_registers); 409 410 /* External interrupt pins in IRL mode */ 411 412 static struct intc_vect irl_vectors[] __initdata = { 413 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 414 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 415 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 416 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), 417 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), 418 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), 419 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), 420 INTC_VECT(IRL_HHHL, 0x3c0), 421 }; 422 423 static struct intc_mask_reg irl3210_mask_registers[] __initdata = { 424 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 425 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 426 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 427 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 428 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 429 }; 430 431 static struct intc_mask_reg irl7654_mask_registers[] __initdata = { 432 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 433 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 434 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 435 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 436 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 437 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 438 }; 439 440 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors, 441 NULL, irl7654_mask_registers, NULL, NULL); 442 443 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, 444 NULL, irl3210_mask_registers, NULL, NULL); 445 446 #define INTC_ICR0 0xffd00000 447 #define INTC_INTMSK0 0xffd00044 448 #define INTC_INTMSK1 0xffd00048 449 #define INTC_INTMSK2 0xffd40080 450 #define INTC_INTMSKCLR1 0xffd00068 451 #define INTC_INTMSKCLR2 0xffd40084 452 453 void __init plat_irq_setup(void) 454 { 455 /* disable IRQ7-0 */ 456 ctrl_outl(0xff000000, INTC_INTMSK0); 457 458 /* disable IRL3-0 + IRL7-4 */ 459 ctrl_outl(0xc0000000, INTC_INTMSK1); 460 ctrl_outl(0xfffefffe, INTC_INTMSK2); 461 462 /* select IRL mode for IRL3-0 + IRL7-4 */ 463 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 464 465 /* disable holding function, ie enable "SH-4 Mode" */ 466 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 467 468 register_intc_controller(&intc_desc); 469 } 470 471 void __init plat_irq_setup_pins(int mode) 472 { 473 switch (mode) { 474 case IRQ_MODE_IRQ: 475 /* select IRQ mode for IRL3-0 + IRL7-4 */ 476 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 477 register_intc_controller(&intc_irq_desc); 478 break; 479 case IRQ_MODE_IRL7654: 480 /* enable IRL7-4 but don't provide any masking */ 481 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 482 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 483 break; 484 case IRQ_MODE_IRL3210: 485 /* enable IRL0-3 but don't provide any masking */ 486 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 487 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 488 break; 489 case IRQ_MODE_IRL7654_MASK: 490 /* enable IRL7-4 and mask using cpu intc controller */ 491 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 492 register_intc_controller(&intc_irl7654_desc); 493 break; 494 case IRQ_MODE_IRL3210_MASK: 495 /* enable IRL0-3 and mask using cpu intc controller */ 496 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 497 register_intc_controller(&intc_irl3210_desc); 498 break; 499 default: 500 BUG(); 501 } 502 } 503