1 /* 2 * SH7780 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/io.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_timer.h> 16 17 #include <asm/dmaengine.h> 18 19 #include <cpu/dma-register.h> 20 21 static struct plat_sci_port scif0_platform_data = { 22 .mapbase = 0xffe00000, 23 .flags = UPF_BOOT_AUTOCONF, 24 .type = PORT_SCIF, 25 .irqs = { 40, 40, 40, 40 }, 26 }; 27 28 static struct platform_device scif0_device = { 29 .name = "sh-sci", 30 .id = 0, 31 .dev = { 32 .platform_data = &scif0_platform_data, 33 }, 34 }; 35 36 static struct plat_sci_port scif1_platform_data = { 37 .mapbase = 0xffe10000, 38 .flags = UPF_BOOT_AUTOCONF, 39 .type = PORT_SCIF, 40 .irqs = { 76, 76, 76, 76 }, 41 }; 42 43 static struct platform_device scif1_device = { 44 .name = "sh-sci", 45 .id = 1, 46 .dev = { 47 .platform_data = &scif1_platform_data, 48 }, 49 }; 50 51 static struct sh_timer_config tmu0_platform_data = { 52 .name = "TMU0", 53 .channel_offset = 0x04, 54 .timer_bit = 0, 55 .clk = "peripheral_clk", 56 .clockevent_rating = 200, 57 }; 58 59 static struct resource tmu0_resources[] = { 60 [0] = { 61 .name = "TMU0", 62 .start = 0xffd80008, 63 .end = 0xffd80013, 64 .flags = IORESOURCE_MEM, 65 }, 66 [1] = { 67 .start = 28, 68 .flags = IORESOURCE_IRQ, 69 }, 70 }; 71 72 static struct platform_device tmu0_device = { 73 .name = "sh_tmu", 74 .id = 0, 75 .dev = { 76 .platform_data = &tmu0_platform_data, 77 }, 78 .resource = tmu0_resources, 79 .num_resources = ARRAY_SIZE(tmu0_resources), 80 }; 81 82 static struct sh_timer_config tmu1_platform_data = { 83 .name = "TMU1", 84 .channel_offset = 0x10, 85 .timer_bit = 1, 86 .clk = "peripheral_clk", 87 .clocksource_rating = 200, 88 }; 89 90 static struct resource tmu1_resources[] = { 91 [0] = { 92 .name = "TMU1", 93 .start = 0xffd80014, 94 .end = 0xffd8001f, 95 .flags = IORESOURCE_MEM, 96 }, 97 [1] = { 98 .start = 29, 99 .flags = IORESOURCE_IRQ, 100 }, 101 }; 102 103 static struct platform_device tmu1_device = { 104 .name = "sh_tmu", 105 .id = 1, 106 .dev = { 107 .platform_data = &tmu1_platform_data, 108 }, 109 .resource = tmu1_resources, 110 .num_resources = ARRAY_SIZE(tmu1_resources), 111 }; 112 113 static struct sh_timer_config tmu2_platform_data = { 114 .name = "TMU2", 115 .channel_offset = 0x1c, 116 .timer_bit = 2, 117 .clk = "peripheral_clk", 118 }; 119 120 static struct resource tmu2_resources[] = { 121 [0] = { 122 .name = "TMU2", 123 .start = 0xffd80020, 124 .end = 0xffd8002f, 125 .flags = IORESOURCE_MEM, 126 }, 127 [1] = { 128 .start = 30, 129 .flags = IORESOURCE_IRQ, 130 }, 131 }; 132 133 static struct platform_device tmu2_device = { 134 .name = "sh_tmu", 135 .id = 2, 136 .dev = { 137 .platform_data = &tmu2_platform_data, 138 }, 139 .resource = tmu2_resources, 140 .num_resources = ARRAY_SIZE(tmu2_resources), 141 }; 142 143 static struct sh_timer_config tmu3_platform_data = { 144 .name = "TMU3", 145 .channel_offset = 0x04, 146 .timer_bit = 0, 147 .clk = "peripheral_clk", 148 }; 149 150 static struct resource tmu3_resources[] = { 151 [0] = { 152 .name = "TMU3", 153 .start = 0xffdc0008, 154 .end = 0xffdc0013, 155 .flags = IORESOURCE_MEM, 156 }, 157 [1] = { 158 .start = 96, 159 .flags = IORESOURCE_IRQ, 160 }, 161 }; 162 163 static struct platform_device tmu3_device = { 164 .name = "sh_tmu", 165 .id = 3, 166 .dev = { 167 .platform_data = &tmu3_platform_data, 168 }, 169 .resource = tmu3_resources, 170 .num_resources = ARRAY_SIZE(tmu3_resources), 171 }; 172 173 static struct sh_timer_config tmu4_platform_data = { 174 .name = "TMU4", 175 .channel_offset = 0x10, 176 .timer_bit = 1, 177 .clk = "peripheral_clk", 178 }; 179 180 static struct resource tmu4_resources[] = { 181 [0] = { 182 .name = "TMU4", 183 .start = 0xffdc0014, 184 .end = 0xffdc001f, 185 .flags = IORESOURCE_MEM, 186 }, 187 [1] = { 188 .start = 97, 189 .flags = IORESOURCE_IRQ, 190 }, 191 }; 192 193 static struct platform_device tmu4_device = { 194 .name = "sh_tmu", 195 .id = 4, 196 .dev = { 197 .platform_data = &tmu4_platform_data, 198 }, 199 .resource = tmu4_resources, 200 .num_resources = ARRAY_SIZE(tmu4_resources), 201 }; 202 203 static struct sh_timer_config tmu5_platform_data = { 204 .name = "TMU5", 205 .channel_offset = 0x1c, 206 .timer_bit = 2, 207 .clk = "peripheral_clk", 208 }; 209 210 static struct resource tmu5_resources[] = { 211 [0] = { 212 .name = "TMU5", 213 .start = 0xffdc0020, 214 .end = 0xffdc002b, 215 .flags = IORESOURCE_MEM, 216 }, 217 [1] = { 218 .start = 98, 219 .flags = IORESOURCE_IRQ, 220 }, 221 }; 222 223 static struct platform_device tmu5_device = { 224 .name = "sh_tmu", 225 .id = 5, 226 .dev = { 227 .platform_data = &tmu5_platform_data, 228 }, 229 .resource = tmu5_resources, 230 .num_resources = ARRAY_SIZE(tmu5_resources), 231 }; 232 233 static struct resource rtc_resources[] = { 234 [0] = { 235 .start = 0xffe80000, 236 .end = 0xffe80000 + 0x58 - 1, 237 .flags = IORESOURCE_IO, 238 }, 239 [1] = { 240 /* Shared Period/Carry/Alarm IRQ */ 241 .start = 20, 242 .flags = IORESOURCE_IRQ, 243 }, 244 }; 245 246 static struct platform_device rtc_device = { 247 .name = "sh-rtc", 248 .id = -1, 249 .num_resources = ARRAY_SIZE(rtc_resources), 250 .resource = rtc_resources, 251 }; 252 253 /* DMA */ 254 static struct sh_dmae_channel sh7780_dmae0_channels[] = { 255 { 256 .offset = 0, 257 .dmars = 0, 258 .dmars_bit = 0, 259 }, { 260 .offset = 0x10, 261 .dmars = 0, 262 .dmars_bit = 8, 263 }, { 264 .offset = 0x20, 265 .dmars = 4, 266 .dmars_bit = 0, 267 }, { 268 .offset = 0x30, 269 .dmars = 4, 270 .dmars_bit = 8, 271 }, { 272 .offset = 0x50, 273 .dmars = 8, 274 .dmars_bit = 0, 275 }, { 276 .offset = 0x60, 277 .dmars = 8, 278 .dmars_bit = 8, 279 } 280 }; 281 282 static struct sh_dmae_channel sh7780_dmae1_channels[] = { 283 { 284 .offset = 0, 285 }, { 286 .offset = 0x10, 287 }, { 288 .offset = 0x20, 289 }, { 290 .offset = 0x30, 291 }, { 292 .offset = 0x50, 293 }, { 294 .offset = 0x60, 295 } 296 }; 297 298 static unsigned int ts_shift[] = TS_SHIFT; 299 300 static struct sh_dmae_pdata dma0_platform_data = { 301 .channel = sh7780_dmae0_channels, 302 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels), 303 .ts_low_shift = CHCR_TS_LOW_SHIFT, 304 .ts_low_mask = CHCR_TS_LOW_MASK, 305 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 306 .ts_high_mask = CHCR_TS_HIGH_MASK, 307 .ts_shift = ts_shift, 308 .ts_shift_num = ARRAY_SIZE(ts_shift), 309 .dmaor_init = DMAOR_INIT, 310 }; 311 312 static struct sh_dmae_pdata dma1_platform_data = { 313 .channel = sh7780_dmae1_channels, 314 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels), 315 .ts_low_shift = CHCR_TS_LOW_SHIFT, 316 .ts_low_mask = CHCR_TS_LOW_MASK, 317 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 318 .ts_high_mask = CHCR_TS_HIGH_MASK, 319 .ts_shift = ts_shift, 320 .ts_shift_num = ARRAY_SIZE(ts_shift), 321 .dmaor_init = DMAOR_INIT, 322 }; 323 324 static struct resource sh7780_dmae0_resources[] = { 325 [0] = { 326 /* Channel registers and DMAOR */ 327 .start = 0xfc808020, 328 .end = 0xfc80808f, 329 .flags = IORESOURCE_MEM, 330 }, 331 [1] = { 332 /* DMARSx */ 333 .start = 0xfc809000, 334 .end = 0xfc80900b, 335 .flags = IORESOURCE_MEM, 336 }, 337 { 338 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */ 339 .start = 34, 340 .end = 34, 341 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 342 }, 343 }; 344 345 static struct resource sh7780_dmae1_resources[] = { 346 [0] = { 347 /* Channel registers and DMAOR */ 348 .start = 0xfc818020, 349 .end = 0xfc81808f, 350 .flags = IORESOURCE_MEM, 351 }, 352 /* DMAC1 has no DMARS */ 353 { 354 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */ 355 .start = 46, 356 .end = 46, 357 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 358 }, 359 }; 360 361 static struct platform_device dma0_device = { 362 .name = "sh-dma-engine", 363 .id = 0, 364 .resource = sh7780_dmae0_resources, 365 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources), 366 .dev = { 367 .platform_data = &dma0_platform_data, 368 }, 369 }; 370 371 static struct platform_device dma1_device = { 372 .name = "sh-dma-engine", 373 .id = 1, 374 .resource = sh7780_dmae1_resources, 375 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources), 376 .dev = { 377 .platform_data = &dma1_platform_data, 378 }, 379 }; 380 381 static struct platform_device *sh7780_devices[] __initdata = { 382 &scif0_device, 383 &scif1_device, 384 &tmu0_device, 385 &tmu1_device, 386 &tmu2_device, 387 &tmu3_device, 388 &tmu4_device, 389 &tmu5_device, 390 &rtc_device, 391 &dma0_device, 392 &dma1_device, 393 }; 394 395 static int __init sh7780_devices_setup(void) 396 { 397 return platform_add_devices(sh7780_devices, 398 ARRAY_SIZE(sh7780_devices)); 399 } 400 arch_initcall(sh7780_devices_setup); 401 static struct platform_device *sh7780_early_devices[] __initdata = { 402 &scif0_device, 403 &scif1_device, 404 &tmu0_device, 405 &tmu1_device, 406 &tmu2_device, 407 &tmu3_device, 408 &tmu4_device, 409 &tmu5_device, 410 }; 411 412 void __init plat_early_device_setup(void) 413 { 414 early_platform_add_devices(sh7780_early_devices, 415 ARRAY_SIZE(sh7780_early_devices)); 416 } 417 418 enum { 419 UNUSED = 0, 420 421 /* interrupt sources */ 422 423 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 424 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 425 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 426 IRL_HHLL, IRL_HHLH, IRL_HHHL, 427 428 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 429 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 430 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC, 431 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5, 432 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO, 433 434 /* interrupt groups */ 435 436 TMU012, TMU345, 437 }; 438 439 static struct intc_vect vectors[] __initdata = { 440 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 441 INTC_VECT(RTC, 0x4c0), 442 INTC_VECT(WDT, 0x560), 443 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 444 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 445 INTC_VECT(HUDI, 0x600), 446 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), 447 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), 448 INTC_VECT(DMAC0, 0x6c0), 449 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720), 450 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760), 451 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), 452 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0), 453 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980), 454 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 455 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 456 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0), 457 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0), 458 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20), 459 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0), 460 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0), 461 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80), 462 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20), 463 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60), 464 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0), 465 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0), 466 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 467 INTC_VECT(TMU5, 0xe40), 468 INTC_VECT(SSI, 0xe80), 469 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20), 470 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60), 471 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0), 472 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0), 473 }; 474 475 static struct intc_group groups[] __initdata = { 476 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 477 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 478 }; 479 480 static struct intc_mask_reg mask_registers[] __initdata = { 481 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 482 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL, 483 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB, 484 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0, 485 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, 486 }; 487 488 static struct intc_prio_reg prio_registers[] __initdata = { 489 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, 490 TMU2, TMU2_TICPI } }, 491 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, 492 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, 493 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } }, 494 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC, 495 PCISERR, PCIINTA, } }, 496 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, 497 PCIINTD, PCIC5 } }, 498 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } }, 499 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } }, 500 }; 501 502 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, 503 mask_registers, prio_registers, NULL); 504 505 /* Support for external interrupt pins in IRQ mode */ 506 507 static struct intc_vect irq_vectors[] __initdata = { 508 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 509 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 510 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 511 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 512 }; 513 514 static struct intc_mask_reg irq_mask_registers[] __initdata = { 515 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 516 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 517 }; 518 519 static struct intc_prio_reg irq_prio_registers[] __initdata = { 520 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 521 IRQ4, IRQ5, IRQ6, IRQ7 } }, 522 }; 523 524 static struct intc_sense_reg irq_sense_registers[] __initdata = { 525 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 526 IRQ4, IRQ5, IRQ6, IRQ7 } }, 527 }; 528 529 static struct intc_mask_reg irq_ack_registers[] __initdata = { 530 { 0xffd00024, 0, 32, /* INTREQ */ 531 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 532 }; 533 534 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors, 535 NULL, irq_mask_registers, irq_prio_registers, 536 irq_sense_registers, irq_ack_registers); 537 538 /* External interrupt pins in IRL mode */ 539 540 static struct intc_vect irl_vectors[] __initdata = { 541 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 542 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 543 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 544 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), 545 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), 546 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), 547 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), 548 INTC_VECT(IRL_HHHL, 0x3c0), 549 }; 550 551 static struct intc_mask_reg irl3210_mask_registers[] __initdata = { 552 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 553 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 554 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 555 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 556 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 557 }; 558 559 static struct intc_mask_reg irl7654_mask_registers[] __initdata = { 560 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 561 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 562 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 563 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 564 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 565 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 566 }; 567 568 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors, 569 NULL, irl7654_mask_registers, NULL, NULL); 570 571 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, 572 NULL, irl3210_mask_registers, NULL, NULL); 573 574 #define INTC_ICR0 0xffd00000 575 #define INTC_INTMSK0 0xffd00044 576 #define INTC_INTMSK1 0xffd00048 577 #define INTC_INTMSK2 0xffd40080 578 #define INTC_INTMSKCLR1 0xffd00068 579 #define INTC_INTMSKCLR2 0xffd40084 580 581 void __init plat_irq_setup(void) 582 { 583 /* disable IRQ7-0 */ 584 __raw_writel(0xff000000, INTC_INTMSK0); 585 586 /* disable IRL3-0 + IRL7-4 */ 587 __raw_writel(0xc0000000, INTC_INTMSK1); 588 __raw_writel(0xfffefffe, INTC_INTMSK2); 589 590 /* select IRL mode for IRL3-0 + IRL7-4 */ 591 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 592 593 /* disable holding function, ie enable "SH-4 Mode" */ 594 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 595 596 register_intc_controller(&intc_desc); 597 } 598 599 void __init plat_irq_setup_pins(int mode) 600 { 601 switch (mode) { 602 case IRQ_MODE_IRQ: 603 /* select IRQ mode for IRL3-0 + IRL7-4 */ 604 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 605 register_intc_controller(&intc_irq_desc); 606 break; 607 case IRQ_MODE_IRL7654: 608 /* enable IRL7-4 but don't provide any masking */ 609 __raw_writel(0x40000000, INTC_INTMSKCLR1); 610 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 611 break; 612 case IRQ_MODE_IRL3210: 613 /* enable IRL0-3 but don't provide any masking */ 614 __raw_writel(0x80000000, INTC_INTMSKCLR1); 615 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 616 break; 617 case IRQ_MODE_IRL7654_MASK: 618 /* enable IRL7-4 and mask using cpu intc controller */ 619 __raw_writel(0x40000000, INTC_INTMSKCLR1); 620 register_intc_controller(&intc_irl7654_desc); 621 break; 622 case IRQ_MODE_IRL3210_MASK: 623 /* enable IRL0-3 and mask using cpu intc controller */ 624 __raw_writel(0x80000000, INTC_INTMSKCLR1); 625 register_intc_controller(&intc_irl3210_desc); 626 break; 627 default: 628 BUG(); 629 } 630 } 631