1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7770 Setup 4 * 5 * Copyright (C) 2006 - 2008 Paul Mundt 6 */ 7 #include <linux/platform_device.h> 8 #include <linux/init.h> 9 #include <linux/serial.h> 10 #include <linux/serial_sci.h> 11 #include <linux/sh_timer.h> 12 #include <linux/sh_intc.h> 13 #include <linux/io.h> 14 15 static struct plat_sci_port scif0_platform_data = { 16 .scscr = SCSCR_REIE | SCSCR_TOIE, 17 .type = PORT_SCIF, 18 }; 19 20 static struct resource scif0_resources[] = { 21 DEFINE_RES_MEM(0xff923000, 0x100), 22 DEFINE_RES_IRQ(evt2irq(0x9a0)), 23 }; 24 25 static struct platform_device scif0_device = { 26 .name = "sh-sci", 27 .id = 0, 28 .resource = scif0_resources, 29 .num_resources = ARRAY_SIZE(scif0_resources), 30 .dev = { 31 .platform_data = &scif0_platform_data, 32 }, 33 }; 34 35 static struct plat_sci_port scif1_platform_data = { 36 .scscr = SCSCR_REIE | SCSCR_TOIE, 37 .type = PORT_SCIF, 38 }; 39 40 static struct resource scif1_resources[] = { 41 DEFINE_RES_MEM(0xff924000, 0x100), 42 DEFINE_RES_IRQ(evt2irq(0x9c0)), 43 }; 44 45 static struct platform_device scif1_device = { 46 .name = "sh-sci", 47 .id = 1, 48 .resource = scif1_resources, 49 .num_resources = ARRAY_SIZE(scif1_resources), 50 .dev = { 51 .platform_data = &scif1_platform_data, 52 }, 53 }; 54 55 static struct plat_sci_port scif2_platform_data = { 56 .scscr = SCSCR_REIE | SCSCR_TOIE, 57 .type = PORT_SCIF, 58 }; 59 60 static struct resource scif2_resources[] = { 61 DEFINE_RES_MEM(0xff925000, 0x100), 62 DEFINE_RES_IRQ(evt2irq(0x9e0)), 63 }; 64 65 static struct platform_device scif2_device = { 66 .name = "sh-sci", 67 .id = 2, 68 .resource = scif2_resources, 69 .num_resources = ARRAY_SIZE(scif2_resources), 70 .dev = { 71 .platform_data = &scif2_platform_data, 72 }, 73 }; 74 75 static struct plat_sci_port scif3_platform_data = { 76 .scscr = SCSCR_REIE | SCSCR_TOIE, 77 .type = PORT_SCIF, 78 }; 79 80 static struct resource scif3_resources[] = { 81 DEFINE_RES_MEM(0xff926000, 0x100), 82 DEFINE_RES_IRQ(evt2irq(0xa00)), 83 }; 84 85 static struct platform_device scif3_device = { 86 .name = "sh-sci", 87 .id = 3, 88 .resource = scif3_resources, 89 .num_resources = ARRAY_SIZE(scif3_resources), 90 .dev = { 91 .platform_data = &scif3_platform_data, 92 }, 93 }; 94 95 static struct plat_sci_port scif4_platform_data = { 96 .scscr = SCSCR_REIE | SCSCR_TOIE, 97 .type = PORT_SCIF, 98 }; 99 100 static struct resource scif4_resources[] = { 101 DEFINE_RES_MEM(0xff927000, 0x100), 102 DEFINE_RES_IRQ(evt2irq(0xa20)), 103 }; 104 105 static struct platform_device scif4_device = { 106 .name = "sh-sci", 107 .id = 4, 108 .resource = scif4_resources, 109 .num_resources = ARRAY_SIZE(scif4_resources), 110 .dev = { 111 .platform_data = &scif4_platform_data, 112 }, 113 }; 114 115 static struct plat_sci_port scif5_platform_data = { 116 .scscr = SCSCR_REIE | SCSCR_TOIE, 117 .type = PORT_SCIF, 118 }; 119 120 static struct resource scif5_resources[] = { 121 DEFINE_RES_MEM(0xff928000, 0x100), 122 DEFINE_RES_IRQ(evt2irq(0xa40)), 123 }; 124 125 static struct platform_device scif5_device = { 126 .name = "sh-sci", 127 .id = 5, 128 .resource = scif5_resources, 129 .num_resources = ARRAY_SIZE(scif5_resources), 130 .dev = { 131 .platform_data = &scif5_platform_data, 132 }, 133 }; 134 135 static struct plat_sci_port scif6_platform_data = { 136 .scscr = SCSCR_REIE | SCSCR_TOIE, 137 .type = PORT_SCIF, 138 }; 139 140 static struct resource scif6_resources[] = { 141 DEFINE_RES_MEM(0xff929000, 0x100), 142 DEFINE_RES_IRQ(evt2irq(0xa60)), 143 }; 144 145 static struct platform_device scif6_device = { 146 .name = "sh-sci", 147 .id = 6, 148 .resource = scif6_resources, 149 .num_resources = ARRAY_SIZE(scif6_resources), 150 .dev = { 151 .platform_data = &scif6_platform_data, 152 }, 153 }; 154 155 static struct plat_sci_port scif7_platform_data = { 156 .scscr = SCSCR_REIE | SCSCR_TOIE, 157 .type = PORT_SCIF, 158 }; 159 160 static struct resource scif7_resources[] = { 161 DEFINE_RES_MEM(0xff92a000, 0x100), 162 DEFINE_RES_IRQ(evt2irq(0xa80)), 163 }; 164 165 static struct platform_device scif7_device = { 166 .name = "sh-sci", 167 .id = 7, 168 .resource = scif7_resources, 169 .num_resources = ARRAY_SIZE(scif7_resources), 170 .dev = { 171 .platform_data = &scif7_platform_data, 172 }, 173 }; 174 175 static struct plat_sci_port scif8_platform_data = { 176 .scscr = SCSCR_REIE | SCSCR_TOIE, 177 .type = PORT_SCIF, 178 }; 179 180 static struct resource scif8_resources[] = { 181 DEFINE_RES_MEM(0xff92b000, 0x100), 182 DEFINE_RES_IRQ(evt2irq(0xaa0)), 183 }; 184 185 static struct platform_device scif8_device = { 186 .name = "sh-sci", 187 .id = 8, 188 .resource = scif8_resources, 189 .num_resources = ARRAY_SIZE(scif8_resources), 190 .dev = { 191 .platform_data = &scif8_platform_data, 192 }, 193 }; 194 195 static struct plat_sci_port scif9_platform_data = { 196 .scscr = SCSCR_REIE | SCSCR_TOIE, 197 .type = PORT_SCIF, 198 }; 199 200 static struct resource scif9_resources[] = { 201 DEFINE_RES_MEM(0xff92c000, 0x100), 202 DEFINE_RES_IRQ(evt2irq(0xac0)), 203 }; 204 205 static struct platform_device scif9_device = { 206 .name = "sh-sci", 207 .id = 9, 208 .resource = scif9_resources, 209 .num_resources = ARRAY_SIZE(scif9_resources), 210 .dev = { 211 .platform_data = &scif9_platform_data, 212 }, 213 }; 214 215 static struct sh_timer_config tmu0_platform_data = { 216 .channels_mask = 7, 217 }; 218 219 static struct resource tmu0_resources[] = { 220 DEFINE_RES_MEM(0xffd80000, 0x30), 221 DEFINE_RES_IRQ(evt2irq(0x400)), 222 DEFINE_RES_IRQ(evt2irq(0x420)), 223 DEFINE_RES_IRQ(evt2irq(0x440)), 224 }; 225 226 static struct platform_device tmu0_device = { 227 .name = "sh-tmu", 228 .id = 0, 229 .dev = { 230 .platform_data = &tmu0_platform_data, 231 }, 232 .resource = tmu0_resources, 233 .num_resources = ARRAY_SIZE(tmu0_resources), 234 }; 235 236 static struct sh_timer_config tmu1_platform_data = { 237 .channels_mask = 7, 238 }; 239 240 static struct resource tmu1_resources[] = { 241 DEFINE_RES_MEM(0xffd81000, 0x30), 242 DEFINE_RES_IRQ(evt2irq(0x460)), 243 DEFINE_RES_IRQ(evt2irq(0x480)), 244 DEFINE_RES_IRQ(evt2irq(0x4a0)), 245 }; 246 247 static struct platform_device tmu1_device = { 248 .name = "sh-tmu", 249 .id = 1, 250 .dev = { 251 .platform_data = &tmu1_platform_data, 252 }, 253 .resource = tmu1_resources, 254 .num_resources = ARRAY_SIZE(tmu1_resources), 255 }; 256 257 static struct sh_timer_config tmu2_platform_data = { 258 .channels_mask = 7, 259 }; 260 261 static struct resource tmu2_resources[] = { 262 DEFINE_RES_MEM(0xffd82000, 0x2c), 263 DEFINE_RES_IRQ(evt2irq(0x4c0)), 264 DEFINE_RES_IRQ(evt2irq(0x4e0)), 265 DEFINE_RES_IRQ(evt2irq(0x500)), 266 }; 267 268 static struct platform_device tmu2_device = { 269 .name = "sh-tmu", 270 .id = 2, 271 .dev = { 272 .platform_data = &tmu2_platform_data, 273 }, 274 .resource = tmu2_resources, 275 .num_resources = ARRAY_SIZE(tmu2_resources), 276 }; 277 278 static struct platform_device *sh7770_devices[] __initdata = { 279 &scif0_device, 280 &scif1_device, 281 &scif2_device, 282 &scif3_device, 283 &scif4_device, 284 &scif5_device, 285 &scif6_device, 286 &scif7_device, 287 &scif8_device, 288 &scif9_device, 289 &tmu0_device, 290 &tmu1_device, 291 &tmu2_device, 292 }; 293 294 static int __init sh7770_devices_setup(void) 295 { 296 return platform_add_devices(sh7770_devices, 297 ARRAY_SIZE(sh7770_devices)); 298 } 299 arch_initcall(sh7770_devices_setup); 300 301 static struct platform_device *sh7770_early_devices[] __initdata = { 302 &scif0_device, 303 &scif1_device, 304 &scif2_device, 305 &scif3_device, 306 &scif4_device, 307 &scif5_device, 308 &scif6_device, 309 &scif7_device, 310 &scif8_device, 311 &scif9_device, 312 &tmu0_device, 313 &tmu1_device, 314 &tmu2_device, 315 }; 316 317 void __init plat_early_device_setup(void) 318 { 319 early_platform_add_devices(sh7770_early_devices, 320 ARRAY_SIZE(sh7770_early_devices)); 321 } 322 323 enum { 324 UNUSED = 0, 325 326 /* interrupt sources */ 327 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 328 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 329 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 330 IRL_HHLL, IRL_HHLH, IRL_HHHL, 331 332 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 333 334 GPIO, 335 TMU0, TMU1, TMU2, TMU2_TICPI, 336 TMU3, TMU4, TMU5, TMU5_TICPI, 337 TMU6, TMU7, TMU8, 338 HAC, IPI, SPDIF, HUDI, I2C, 339 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, 340 I2S0, I2S1, I2S2, I2S3, 341 SRC_RX, SRC_TX, SRC_SPDIF, 342 DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D, 343 GFX3D_MBX, GFX3D_DMAC, 344 EXBUS_ATA, 345 SPI0, SPI1, 346 SCIF089, SCIF1234, SCIF567, 347 ADC, 348 BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, 349 BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, 350 BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31, 351 352 /* interrupt groups */ 353 TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC, 354 }; 355 356 static struct intc_vect vectors[] __initdata = { 357 INTC_VECT(GPIO, 0x3e0), 358 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 359 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 360 INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0), 361 INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0), 362 INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520), 363 INTC_VECT(TMU8, 0x540), 364 INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0), 365 INTC_VECT(SPDIF, 0x5e0), 366 INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620), 367 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), 368 INTC_VECT(DMAC0_DMINT2, 0x680), 369 INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0), 370 INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700), 371 INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740), 372 INTC_VECT(SRC_SPDIF, 0x760), 373 INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0), 374 INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0), 375 INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860), 376 INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0), 377 INTC_VECT(GFX2D, 0x8c0), 378 INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920), 379 INTC_VECT(EXBUS_ATA, 0x940), 380 INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980), 381 INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0), 382 INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00), 383 INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40), 384 INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80), 385 INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0), 386 INTC_VECT(ADC, 0xb20), 387 INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0), 388 INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00), 389 INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40), 390 INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80), 391 INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0), 392 INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00), 393 INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40), 394 INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80), 395 INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0), 396 INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00), 397 INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40), 398 INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80), 399 INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0), 400 INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00), 401 INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40), 402 INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80), 403 }; 404 405 static struct intc_group groups[] __initdata = { 406 INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, 407 TMU5_TICPI, TMU6, TMU7, TMU8), 408 INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2), 409 INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3), 410 INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF), 411 INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC), 412 INTC_GROUP(SPI, SPI0, SPI1), 413 INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567), 414 INTC_GROUP(BBDMAC, 415 BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, 416 BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, 417 BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31), 418 }; 419 420 static struct intc_mask_reg mask_registers[] __initdata = { 421 { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */ 422 { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D, 423 GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S, 424 DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } }, 425 }; 426 427 static struct intc_prio_reg prio_registers[] __initdata = { 428 { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } }, 429 { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } }, 430 { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } }, 431 { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } }, 432 { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } }, 433 { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } }, 434 { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } }, 435 { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } }, 436 { 0xffe00020, 0, 32, 8, /* INT2PRI8 */ 437 { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } }, 438 { 0xffe00024, 0, 32, 8, /* INT2PRI9 */ 439 { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } }, 440 { 0xffe00028, 0, 32, 8, /* INT2PRI10 */ 441 { BBDMAC_29, BBDMAC_30, BBDMAC_31 } }, 442 { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */ 443 { TMU1, TMU2, TMU2_TICPI, TMU3 } }, 444 { 0xffe00030, 0, 32, 8, /* INT2PRI12 */ 445 { TMU4, TMU5, TMU5_TICPI, TMU6 } }, 446 { 0xffe00034, 0, 32, 8, /* INT2PRI13 */ 447 { TMU7, TMU8 } }, 448 }; 449 450 static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups, 451 mask_registers, prio_registers, NULL); 452 453 /* Support for external interrupt pins in IRQ mode */ 454 static struct intc_vect irq_vectors[] __initdata = { 455 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 456 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 457 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 458 }; 459 460 static struct intc_mask_reg irq_mask_registers[] __initdata = { 461 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 462 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } }, 463 }; 464 465 static struct intc_prio_reg irq_prio_registers[] __initdata = { 466 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 467 IRQ4, IRQ5, } }, 468 }; 469 470 static struct intc_sense_reg irq_sense_registers[] __initdata = { 471 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 472 IRQ4, IRQ5, } }, 473 }; 474 475 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors, 476 NULL, irq_mask_registers, irq_prio_registers, 477 irq_sense_registers); 478 479 /* External interrupt pins in IRL mode */ 480 static struct intc_vect irl_vectors[] __initdata = { 481 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 482 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 483 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 484 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), 485 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), 486 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), 487 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), 488 INTC_VECT(IRL_HHHL, 0x3c0), 489 }; 490 491 static struct intc_mask_reg irl3210_mask_registers[] __initdata = { 492 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 493 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 494 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 495 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 496 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 497 }; 498 499 static struct intc_mask_reg irl7654_mask_registers[] __initdata = { 500 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 501 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 502 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 503 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 504 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 505 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 506 }; 507 508 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors, 509 NULL, irl7654_mask_registers, NULL, NULL); 510 511 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, 512 NULL, irl3210_mask_registers, NULL, NULL); 513 514 #define INTC_ICR0 0xffd00000 515 #define INTC_INTMSK0 0xffd00044 516 #define INTC_INTMSK1 0xffd00048 517 #define INTC_INTMSK2 0xffd40080 518 #define INTC_INTMSKCLR1 0xffd00068 519 #define INTC_INTMSKCLR2 0xffd40084 520 521 void __init plat_irq_setup(void) 522 { 523 /* disable IRQ7-0 */ 524 __raw_writel(0xff000000, INTC_INTMSK0); 525 526 /* disable IRL3-0 + IRL7-4 */ 527 __raw_writel(0xc0000000, INTC_INTMSK1); 528 __raw_writel(0xfffefffe, INTC_INTMSK2); 529 530 /* select IRL mode for IRL3-0 + IRL7-4 */ 531 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 532 533 /* disable holding function, ie enable "SH-4 Mode" */ 534 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 535 536 register_intc_controller(&intc_desc); 537 } 538 539 void __init plat_irq_setup_pins(int mode) 540 { 541 switch (mode) { 542 case IRQ_MODE_IRQ: 543 /* select IRQ mode for IRL3-0 + IRL7-4 */ 544 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 545 register_intc_controller(&intc_irq_desc); 546 break; 547 case IRQ_MODE_IRL7654: 548 /* enable IRL7-4 but don't provide any masking */ 549 __raw_writel(0x40000000, INTC_INTMSKCLR1); 550 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 551 break; 552 case IRQ_MODE_IRL3210: 553 /* enable IRL0-3 but don't provide any masking */ 554 __raw_writel(0x80000000, INTC_INTMSKCLR1); 555 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 556 break; 557 case IRQ_MODE_IRL7654_MASK: 558 /* enable IRL7-4 and mask using cpu intc controller */ 559 __raw_writel(0x40000000, INTC_INTMSKCLR1); 560 register_intc_controller(&intc_irl7654_desc); 561 break; 562 case IRQ_MODE_IRL3210_MASK: 563 /* enable IRL0-3 and mask using cpu intc controller */ 564 __raw_writel(0x80000000, INTC_INTMSKCLR1); 565 register_intc_controller(&intc_irl3210_desc); 566 break; 567 default: 568 BUG(); 569 } 570 } 571