1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7757 Setup 4 * 5 * Copyright (C) 2009, 2011 Renesas Solutions Corp. 6 * 7 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt 8 */ 9 #include <linux/platform_device.h> 10 #include <linux/init.h> 11 #include <linux/serial.h> 12 #include <linux/serial_sci.h> 13 #include <linux/io.h> 14 #include <linux/mm.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sh_timer.h> 17 #include <linux/sh_dma.h> 18 #include <linux/sh_intc.h> 19 #include <linux/usb/ohci_pdriver.h> 20 21 #include <cpu/dma-register.h> 22 #include <cpu/sh7757.h> 23 24 #include <asm/mmzone.h> 25 #include <asm/platform_early.h> 26 27 static struct plat_sci_port scif2_platform_data = { 28 .scscr = SCSCR_REIE, 29 .type = PORT_SCIF, 30 }; 31 32 static struct resource scif2_resources[] = { 33 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */ 34 DEFINE_RES_IRQ(evt2irq(0x700)), 35 }; 36 37 static struct platform_device scif2_device = { 38 .name = "sh-sci", 39 .id = 0, 40 .resource = scif2_resources, 41 .num_resources = ARRAY_SIZE(scif2_resources), 42 .dev = { 43 .platform_data = &scif2_platform_data, 44 }, 45 }; 46 47 static struct plat_sci_port scif3_platform_data = { 48 .scscr = SCSCR_REIE, 49 .type = PORT_SCIF, 50 }; 51 52 static struct resource scif3_resources[] = { 53 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */ 54 DEFINE_RES_IRQ(evt2irq(0xb80)), 55 }; 56 57 static struct platform_device scif3_device = { 58 .name = "sh-sci", 59 .id = 1, 60 .resource = scif3_resources, 61 .num_resources = ARRAY_SIZE(scif3_resources), 62 .dev = { 63 .platform_data = &scif3_platform_data, 64 }, 65 }; 66 67 static struct plat_sci_port scif4_platform_data = { 68 .scscr = SCSCR_REIE, 69 .type = PORT_SCIF, 70 }; 71 72 static struct resource scif4_resources[] = { 73 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */ 74 DEFINE_RES_IRQ(evt2irq(0xf00)), 75 }; 76 77 static struct platform_device scif4_device = { 78 .name = "sh-sci", 79 .id = 2, 80 .resource = scif4_resources, 81 .num_resources = ARRAY_SIZE(scif4_resources), 82 .dev = { 83 .platform_data = &scif4_platform_data, 84 }, 85 }; 86 87 static struct sh_timer_config tmu0_platform_data = { 88 .channels_mask = 3, 89 }; 90 91 static struct resource tmu0_resources[] = { 92 DEFINE_RES_MEM(0xfe430000, 0x20), 93 DEFINE_RES_IRQ(evt2irq(0x580)), 94 DEFINE_RES_IRQ(evt2irq(0x5a0)), 95 }; 96 97 static struct platform_device tmu0_device = { 98 .name = "sh-tmu", 99 .id = 0, 100 .dev = { 101 .platform_data = &tmu0_platform_data, 102 }, 103 .resource = tmu0_resources, 104 .num_resources = ARRAY_SIZE(tmu0_resources), 105 }; 106 107 static struct resource spi0_resources[] = { 108 [0] = { 109 .start = 0xfe002000, 110 .end = 0xfe0020ff, 111 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 112 }, 113 [1] = { 114 .start = evt2irq(0xcc0), 115 .flags = IORESOURCE_IRQ, 116 }, 117 }; 118 119 /* DMA */ 120 static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = { 121 { 122 .slave_id = SHDMA_SLAVE_SDHI_TX, 123 .addr = 0x1fe50030, 124 .chcr = SM_INC | RS_ERS | 0x40000000 | 125 TS_INDEX2VAL(XMIT_SZ_16BIT), 126 .mid_rid = 0xc5, 127 }, 128 { 129 .slave_id = SHDMA_SLAVE_SDHI_RX, 130 .addr = 0x1fe50030, 131 .chcr = DM_INC | RS_ERS | 0x40000000 | 132 TS_INDEX2VAL(XMIT_SZ_16BIT), 133 .mid_rid = 0xc6, 134 }, 135 { 136 .slave_id = SHDMA_SLAVE_MMCIF_TX, 137 .addr = 0x1fcb0034, 138 .chcr = SM_INC | RS_ERS | 0x40000000 | 139 TS_INDEX2VAL(XMIT_SZ_32BIT), 140 .mid_rid = 0xd3, 141 }, 142 { 143 .slave_id = SHDMA_SLAVE_MMCIF_RX, 144 .addr = 0x1fcb0034, 145 .chcr = DM_INC | RS_ERS | 0x40000000 | 146 TS_INDEX2VAL(XMIT_SZ_32BIT), 147 .mid_rid = 0xd7, 148 }, 149 }; 150 151 static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = { 152 { 153 .slave_id = SHDMA_SLAVE_SCIF2_TX, 154 .addr = 0x1f4b000c, 155 .chcr = SM_INC | RS_ERS | 0x40000000 | 156 TS_INDEX2VAL(XMIT_SZ_8BIT), 157 .mid_rid = 0x21, 158 }, 159 { 160 .slave_id = SHDMA_SLAVE_SCIF2_RX, 161 .addr = 0x1f4b0014, 162 .chcr = DM_INC | RS_ERS | 0x40000000 | 163 TS_INDEX2VAL(XMIT_SZ_8BIT), 164 .mid_rid = 0x22, 165 }, 166 { 167 .slave_id = SHDMA_SLAVE_SCIF3_TX, 168 .addr = 0x1f4c000c, 169 .chcr = SM_INC | RS_ERS | 0x40000000 | 170 TS_INDEX2VAL(XMIT_SZ_8BIT), 171 .mid_rid = 0x29, 172 }, 173 { 174 .slave_id = SHDMA_SLAVE_SCIF3_RX, 175 .addr = 0x1f4c0014, 176 .chcr = DM_INC | RS_ERS | 0x40000000 | 177 TS_INDEX2VAL(XMIT_SZ_8BIT), 178 .mid_rid = 0x2a, 179 }, 180 { 181 .slave_id = SHDMA_SLAVE_SCIF4_TX, 182 .addr = 0x1f4d000c, 183 .chcr = SM_INC | RS_ERS | 0x40000000 | 184 TS_INDEX2VAL(XMIT_SZ_8BIT), 185 .mid_rid = 0x41, 186 }, 187 { 188 .slave_id = SHDMA_SLAVE_SCIF4_RX, 189 .addr = 0x1f4d0014, 190 .chcr = DM_INC | RS_ERS | 0x40000000 | 191 TS_INDEX2VAL(XMIT_SZ_8BIT), 192 .mid_rid = 0x42, 193 }, 194 { 195 .slave_id = SHDMA_SLAVE_RSPI_TX, 196 .addr = 0xfe480004, 197 .chcr = SM_INC | RS_ERS | 0x40000000 | 198 TS_INDEX2VAL(XMIT_SZ_16BIT), 199 .mid_rid = 0xc1, 200 }, 201 { 202 .slave_id = SHDMA_SLAVE_RSPI_RX, 203 .addr = 0xfe480004, 204 .chcr = DM_INC | RS_ERS | 0x40000000 | 205 TS_INDEX2VAL(XMIT_SZ_16BIT), 206 .mid_rid = 0xc2, 207 }, 208 }; 209 210 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = { 211 { 212 .slave_id = SHDMA_SLAVE_RIIC0_TX, 213 .addr = 0x1e500012, 214 .chcr = SM_INC | RS_ERS | 0x40000000 | 215 TS_INDEX2VAL(XMIT_SZ_8BIT), 216 .mid_rid = 0x21, 217 }, 218 { 219 .slave_id = SHDMA_SLAVE_RIIC0_RX, 220 .addr = 0x1e500013, 221 .chcr = DM_INC | RS_ERS | 0x40000000 | 222 TS_INDEX2VAL(XMIT_SZ_8BIT), 223 .mid_rid = 0x22, 224 }, 225 { 226 .slave_id = SHDMA_SLAVE_RIIC1_TX, 227 .addr = 0x1e510012, 228 .chcr = SM_INC | RS_ERS | 0x40000000 | 229 TS_INDEX2VAL(XMIT_SZ_8BIT), 230 .mid_rid = 0x29, 231 }, 232 { 233 .slave_id = SHDMA_SLAVE_RIIC1_RX, 234 .addr = 0x1e510013, 235 .chcr = DM_INC | RS_ERS | 0x40000000 | 236 TS_INDEX2VAL(XMIT_SZ_8BIT), 237 .mid_rid = 0x2a, 238 }, 239 { 240 .slave_id = SHDMA_SLAVE_RIIC2_TX, 241 .addr = 0x1e520012, 242 .chcr = SM_INC | RS_ERS | 0x40000000 | 243 TS_INDEX2VAL(XMIT_SZ_8BIT), 244 .mid_rid = 0xa1, 245 }, 246 { 247 .slave_id = SHDMA_SLAVE_RIIC2_RX, 248 .addr = 0x1e520013, 249 .chcr = DM_INC | RS_ERS | 0x40000000 | 250 TS_INDEX2VAL(XMIT_SZ_8BIT), 251 .mid_rid = 0xa2, 252 }, 253 { 254 .slave_id = SHDMA_SLAVE_RIIC3_TX, 255 .addr = 0x1e530012, 256 .chcr = SM_INC | RS_ERS | 0x40000000 | 257 TS_INDEX2VAL(XMIT_SZ_8BIT), 258 .mid_rid = 0xa9, 259 }, 260 { 261 .slave_id = SHDMA_SLAVE_RIIC3_RX, 262 .addr = 0x1e530013, 263 .chcr = DM_INC | RS_ERS | 0x40000000 | 264 TS_INDEX2VAL(XMIT_SZ_8BIT), 265 .mid_rid = 0xaf, 266 }, 267 { 268 .slave_id = SHDMA_SLAVE_RIIC4_TX, 269 .addr = 0x1e540012, 270 .chcr = SM_INC | RS_ERS | 0x40000000 | 271 TS_INDEX2VAL(XMIT_SZ_8BIT), 272 .mid_rid = 0xc5, 273 }, 274 { 275 .slave_id = SHDMA_SLAVE_RIIC4_RX, 276 .addr = 0x1e540013, 277 .chcr = DM_INC | RS_ERS | 0x40000000 | 278 TS_INDEX2VAL(XMIT_SZ_8BIT), 279 .mid_rid = 0xc6, 280 }, 281 }; 282 283 static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = { 284 { 285 .slave_id = SHDMA_SLAVE_RIIC5_TX, 286 .addr = 0x1e550012, 287 .chcr = SM_INC | RS_ERS | 0x40000000 | 288 TS_INDEX2VAL(XMIT_SZ_8BIT), 289 .mid_rid = 0x21, 290 }, 291 { 292 .slave_id = SHDMA_SLAVE_RIIC5_RX, 293 .addr = 0x1e550013, 294 .chcr = DM_INC | RS_ERS | 0x40000000 | 295 TS_INDEX2VAL(XMIT_SZ_8BIT), 296 .mid_rid = 0x22, 297 }, 298 { 299 .slave_id = SHDMA_SLAVE_RIIC6_TX, 300 .addr = 0x1e560012, 301 .chcr = SM_INC | RS_ERS | 0x40000000 | 302 TS_INDEX2VAL(XMIT_SZ_8BIT), 303 .mid_rid = 0x29, 304 }, 305 { 306 .slave_id = SHDMA_SLAVE_RIIC6_RX, 307 .addr = 0x1e560013, 308 .chcr = DM_INC | RS_ERS | 0x40000000 | 309 TS_INDEX2VAL(XMIT_SZ_8BIT), 310 .mid_rid = 0x2a, 311 }, 312 { 313 .slave_id = SHDMA_SLAVE_RIIC7_TX, 314 .addr = 0x1e570012, 315 .chcr = SM_INC | RS_ERS | 0x40000000 | 316 TS_INDEX2VAL(XMIT_SZ_8BIT), 317 .mid_rid = 0x41, 318 }, 319 { 320 .slave_id = SHDMA_SLAVE_RIIC7_RX, 321 .addr = 0x1e570013, 322 .chcr = DM_INC | RS_ERS | 0x40000000 | 323 TS_INDEX2VAL(XMIT_SZ_8BIT), 324 .mid_rid = 0x42, 325 }, 326 { 327 .slave_id = SHDMA_SLAVE_RIIC8_TX, 328 .addr = 0x1e580012, 329 .chcr = SM_INC | RS_ERS | 0x40000000 | 330 TS_INDEX2VAL(XMIT_SZ_8BIT), 331 .mid_rid = 0x45, 332 }, 333 { 334 .slave_id = SHDMA_SLAVE_RIIC8_RX, 335 .addr = 0x1e580013, 336 .chcr = DM_INC | RS_ERS | 0x40000000 | 337 TS_INDEX2VAL(XMIT_SZ_8BIT), 338 .mid_rid = 0x46, 339 }, 340 { 341 .slave_id = SHDMA_SLAVE_RIIC9_TX, 342 .addr = 0x1e590012, 343 .chcr = SM_INC | RS_ERS | 0x40000000 | 344 TS_INDEX2VAL(XMIT_SZ_8BIT), 345 .mid_rid = 0x51, 346 }, 347 { 348 .slave_id = SHDMA_SLAVE_RIIC9_RX, 349 .addr = 0x1e590013, 350 .chcr = DM_INC | RS_ERS | 0x40000000 | 351 TS_INDEX2VAL(XMIT_SZ_8BIT), 352 .mid_rid = 0x52, 353 }, 354 }; 355 356 static const struct sh_dmae_channel sh7757_dmae_channels[] = { 357 { 358 .offset = 0, 359 .dmars = 0, 360 .dmars_bit = 0, 361 }, { 362 .offset = 0x10, 363 .dmars = 0, 364 .dmars_bit = 8, 365 }, { 366 .offset = 0x20, 367 .dmars = 4, 368 .dmars_bit = 0, 369 }, { 370 .offset = 0x30, 371 .dmars = 4, 372 .dmars_bit = 8, 373 }, { 374 .offset = 0x50, 375 .dmars = 8, 376 .dmars_bit = 0, 377 }, { 378 .offset = 0x60, 379 .dmars = 8, 380 .dmars_bit = 8, 381 } 382 }; 383 384 static const unsigned int ts_shift[] = TS_SHIFT; 385 386 static struct sh_dmae_pdata dma0_platform_data = { 387 .slave = sh7757_dmae0_slaves, 388 .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves), 389 .channel = sh7757_dmae_channels, 390 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 391 .ts_low_shift = CHCR_TS_LOW_SHIFT, 392 .ts_low_mask = CHCR_TS_LOW_MASK, 393 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 394 .ts_high_mask = CHCR_TS_HIGH_MASK, 395 .ts_shift = ts_shift, 396 .ts_shift_num = ARRAY_SIZE(ts_shift), 397 .dmaor_init = DMAOR_INIT, 398 }; 399 400 static struct sh_dmae_pdata dma1_platform_data = { 401 .slave = sh7757_dmae1_slaves, 402 .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves), 403 .channel = sh7757_dmae_channels, 404 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 405 .ts_low_shift = CHCR_TS_LOW_SHIFT, 406 .ts_low_mask = CHCR_TS_LOW_MASK, 407 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 408 .ts_high_mask = CHCR_TS_HIGH_MASK, 409 .ts_shift = ts_shift, 410 .ts_shift_num = ARRAY_SIZE(ts_shift), 411 .dmaor_init = DMAOR_INIT, 412 }; 413 414 static struct sh_dmae_pdata dma2_platform_data = { 415 .slave = sh7757_dmae2_slaves, 416 .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves), 417 .channel = sh7757_dmae_channels, 418 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 419 .ts_low_shift = CHCR_TS_LOW_SHIFT, 420 .ts_low_mask = CHCR_TS_LOW_MASK, 421 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 422 .ts_high_mask = CHCR_TS_HIGH_MASK, 423 .ts_shift = ts_shift, 424 .ts_shift_num = ARRAY_SIZE(ts_shift), 425 .dmaor_init = DMAOR_INIT, 426 }; 427 428 static struct sh_dmae_pdata dma3_platform_data = { 429 .slave = sh7757_dmae3_slaves, 430 .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves), 431 .channel = sh7757_dmae_channels, 432 .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 433 .ts_low_shift = CHCR_TS_LOW_SHIFT, 434 .ts_low_mask = CHCR_TS_LOW_MASK, 435 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 436 .ts_high_mask = CHCR_TS_HIGH_MASK, 437 .ts_shift = ts_shift, 438 .ts_shift_num = ARRAY_SIZE(ts_shift), 439 .dmaor_init = DMAOR_INIT, 440 }; 441 442 /* channel 0 to 5 */ 443 static struct resource sh7757_dmae0_resources[] = { 444 [0] = { 445 /* Channel registers and DMAOR */ 446 .start = 0xff608020, 447 .end = 0xff60808f, 448 .flags = IORESOURCE_MEM, 449 }, 450 [1] = { 451 /* DMARSx */ 452 .start = 0xff609000, 453 .end = 0xff60900b, 454 .flags = IORESOURCE_MEM, 455 }, 456 { 457 .name = "error_irq", 458 .start = evt2irq(0x640), 459 .end = evt2irq(0x640), 460 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 461 }, 462 }; 463 464 /* channel 6 to 11 */ 465 static struct resource sh7757_dmae1_resources[] = { 466 [0] = { 467 /* Channel registers and DMAOR */ 468 .start = 0xff618020, 469 .end = 0xff61808f, 470 .flags = IORESOURCE_MEM, 471 }, 472 [1] = { 473 /* DMARSx */ 474 .start = 0xff619000, 475 .end = 0xff61900b, 476 .flags = IORESOURCE_MEM, 477 }, 478 { 479 .name = "error_irq", 480 .start = evt2irq(0x640), 481 .end = evt2irq(0x640), 482 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 483 }, 484 { 485 /* IRQ for channels 4 */ 486 .start = evt2irq(0x7c0), 487 .end = evt2irq(0x7c0), 488 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 489 }, 490 { 491 /* IRQ for channels 5 */ 492 .start = evt2irq(0x7c0), 493 .end = evt2irq(0x7c0), 494 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 495 }, 496 { 497 /* IRQ for channels 6 */ 498 .start = evt2irq(0xd00), 499 .end = evt2irq(0xd00), 500 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 501 }, 502 { 503 /* IRQ for channels 7 */ 504 .start = evt2irq(0xd00), 505 .end = evt2irq(0xd00), 506 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 507 }, 508 { 509 /* IRQ for channels 8 */ 510 .start = evt2irq(0xd00), 511 .end = evt2irq(0xd00), 512 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 513 }, 514 { 515 /* IRQ for channels 9 */ 516 .start = evt2irq(0xd00), 517 .end = evt2irq(0xd00), 518 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 519 }, 520 { 521 /* IRQ for channels 10 */ 522 .start = evt2irq(0xd00), 523 .end = evt2irq(0xd00), 524 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 525 }, 526 { 527 /* IRQ for channels 11 */ 528 .start = evt2irq(0xd00), 529 .end = evt2irq(0xd00), 530 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 531 }, 532 }; 533 534 /* channel 12 to 17 */ 535 static struct resource sh7757_dmae2_resources[] = { 536 [0] = { 537 /* Channel registers and DMAOR */ 538 .start = 0xff708020, 539 .end = 0xff70808f, 540 .flags = IORESOURCE_MEM, 541 }, 542 [1] = { 543 /* DMARSx */ 544 .start = 0xff709000, 545 .end = 0xff70900b, 546 .flags = IORESOURCE_MEM, 547 }, 548 { 549 .name = "error_irq", 550 .start = evt2irq(0x2a60), 551 .end = evt2irq(0x2a60), 552 .flags = IORESOURCE_IRQ, 553 }, 554 { 555 /* IRQ for channels 12 to 16 */ 556 .start = evt2irq(0x2400), 557 .end = evt2irq(0x2480), 558 .flags = IORESOURCE_IRQ, 559 }, 560 { 561 /* IRQ for channel 17 */ 562 .start = evt2irq(0x24e0), 563 .end = evt2irq(0x24e0), 564 .flags = IORESOURCE_IRQ, 565 }, 566 }; 567 568 /* channel 18 to 23 */ 569 static struct resource sh7757_dmae3_resources[] = { 570 [0] = { 571 /* Channel registers and DMAOR */ 572 .start = 0xff718020, 573 .end = 0xff71808f, 574 .flags = IORESOURCE_MEM, 575 }, 576 [1] = { 577 /* DMARSx */ 578 .start = 0xff719000, 579 .end = 0xff71900b, 580 .flags = IORESOURCE_MEM, 581 }, 582 { 583 .name = "error_irq", 584 .start = evt2irq(0x2a80), 585 .end = evt2irq(0x2a80), 586 .flags = IORESOURCE_IRQ, 587 }, 588 { 589 /* IRQ for channels 18 to 22 */ 590 .start = evt2irq(0x2500), 591 .end = evt2irq(0x2580), 592 .flags = IORESOURCE_IRQ, 593 }, 594 { 595 /* IRQ for channel 23 */ 596 .start = evt2irq(0x2600), 597 .end = evt2irq(0x2600), 598 .flags = IORESOURCE_IRQ, 599 }, 600 }; 601 602 static struct platform_device dma0_device = { 603 .name = "sh-dma-engine", 604 .id = 0, 605 .resource = sh7757_dmae0_resources, 606 .num_resources = ARRAY_SIZE(sh7757_dmae0_resources), 607 .dev = { 608 .platform_data = &dma0_platform_data, 609 }, 610 }; 611 612 static struct platform_device dma1_device = { 613 .name = "sh-dma-engine", 614 .id = 1, 615 .resource = sh7757_dmae1_resources, 616 .num_resources = ARRAY_SIZE(sh7757_dmae1_resources), 617 .dev = { 618 .platform_data = &dma1_platform_data, 619 }, 620 }; 621 622 static struct platform_device dma2_device = { 623 .name = "sh-dma-engine", 624 .id = 2, 625 .resource = sh7757_dmae2_resources, 626 .num_resources = ARRAY_SIZE(sh7757_dmae2_resources), 627 .dev = { 628 .platform_data = &dma2_platform_data, 629 }, 630 }; 631 632 static struct platform_device dma3_device = { 633 .name = "sh-dma-engine", 634 .id = 3, 635 .resource = sh7757_dmae3_resources, 636 .num_resources = ARRAY_SIZE(sh7757_dmae3_resources), 637 .dev = { 638 .platform_data = &dma3_platform_data, 639 }, 640 }; 641 642 static struct platform_device spi0_device = { 643 .name = "sh_spi", 644 .id = 0, 645 .dev = { 646 .dma_mask = NULL, 647 .coherent_dma_mask = 0xffffffff, 648 }, 649 .num_resources = ARRAY_SIZE(spi0_resources), 650 .resource = spi0_resources, 651 }; 652 653 static struct resource spi1_resources[] = { 654 { 655 .start = 0xffd8ee70, 656 .end = 0xffd8eeff, 657 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 658 }, 659 { 660 .start = evt2irq(0x8c0), 661 .flags = IORESOURCE_IRQ, 662 }, 663 }; 664 665 static struct platform_device spi1_device = { 666 .name = "sh_spi", 667 .id = 1, 668 .num_resources = ARRAY_SIZE(spi1_resources), 669 .resource = spi1_resources, 670 }; 671 672 static struct resource rspi_resources[] = { 673 { 674 .start = 0xfe480000, 675 .end = 0xfe4800ff, 676 .flags = IORESOURCE_MEM, 677 }, 678 { 679 .start = evt2irq(0x1d80), 680 .flags = IORESOURCE_IRQ, 681 }, 682 }; 683 684 static struct platform_device rspi_device = { 685 .name = "rspi", 686 .id = 2, 687 .num_resources = ARRAY_SIZE(rspi_resources), 688 .resource = rspi_resources, 689 }; 690 691 static struct resource usb_ehci_resources[] = { 692 [0] = { 693 .start = 0xfe4f1000, 694 .end = 0xfe4f10ff, 695 .flags = IORESOURCE_MEM, 696 }, 697 [1] = { 698 .start = evt2irq(0x920), 699 .end = evt2irq(0x920), 700 .flags = IORESOURCE_IRQ, 701 }, 702 }; 703 704 static struct platform_device usb_ehci_device = { 705 .name = "sh_ehci", 706 .id = -1, 707 .dev = { 708 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask, 709 .coherent_dma_mask = DMA_BIT_MASK(32), 710 }, 711 .num_resources = ARRAY_SIZE(usb_ehci_resources), 712 .resource = usb_ehci_resources, 713 }; 714 715 static struct resource usb_ohci_resources[] = { 716 [0] = { 717 .start = 0xfe4f1800, 718 .end = 0xfe4f18ff, 719 .flags = IORESOURCE_MEM, 720 }, 721 [1] = { 722 .start = evt2irq(0x920), 723 .end = evt2irq(0x920), 724 .flags = IORESOURCE_IRQ, 725 }, 726 }; 727 728 static struct usb_ohci_pdata usb_ohci_pdata; 729 730 static struct platform_device usb_ohci_device = { 731 .name = "ohci-platform", 732 .id = -1, 733 .dev = { 734 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask, 735 .coherent_dma_mask = DMA_BIT_MASK(32), 736 .platform_data = &usb_ohci_pdata, 737 }, 738 .num_resources = ARRAY_SIZE(usb_ohci_resources), 739 .resource = usb_ohci_resources, 740 }; 741 742 static struct platform_device *sh7757_devices[] __initdata = { 743 &scif2_device, 744 &scif3_device, 745 &scif4_device, 746 &tmu0_device, 747 &dma0_device, 748 &dma1_device, 749 &dma2_device, 750 &dma3_device, 751 &spi0_device, 752 &spi1_device, 753 &rspi_device, 754 &usb_ehci_device, 755 &usb_ohci_device, 756 }; 757 758 static int __init sh7757_devices_setup(void) 759 { 760 return platform_add_devices(sh7757_devices, 761 ARRAY_SIZE(sh7757_devices)); 762 } 763 arch_initcall(sh7757_devices_setup); 764 765 static struct platform_device *sh7757_early_devices[] __initdata = { 766 &scif2_device, 767 &scif3_device, 768 &scif4_device, 769 &tmu0_device, 770 }; 771 772 void __init plat_early_device_setup(void) 773 { 774 sh_early_platform_add_devices(sh7757_early_devices, 775 ARRAY_SIZE(sh7757_early_devices)); 776 } 777 778 enum { 779 UNUSED = 0, 780 781 /* interrupt sources */ 782 783 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 784 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 785 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 786 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 787 788 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 789 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 790 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 791 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 792 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 793 794 SDHI, DVC, 795 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15, 796 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, 797 HUDI, 798 ARC4, 799 DMAC0_5, DMAC6_7, DMAC8_11, 800 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, 801 USB0, USB1, 802 JMC, 803 SPI0, SPI1, 804 TMR01, TMR23, TMR45, 805 FRT, 806 LPC, LPC5, LPC6, LPC7, LPC8, 807 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5, 808 ETHERC, 809 ADC0, ADC1, 810 SIM, 811 IIC0_0, IIC0_1, IIC0_2, IIC0_3, 812 IIC1_0, IIC1_1, IIC1_2, IIC1_3, 813 IIC2_0, IIC2_1, IIC2_2, IIC2_3, 814 IIC3_0, IIC3_1, IIC3_2, IIC3_3, 815 IIC4_0, IIC4_1, IIC4_2, IIC4_3, 816 IIC5_0, IIC5_1, IIC5_2, IIC5_3, 817 IIC6_0, IIC6_1, IIC6_2, IIC6_3, 818 IIC7_0, IIC7_1, IIC7_2, IIC7_3, 819 IIC8_0, IIC8_1, IIC8_2, IIC8_3, 820 IIC9_0, IIC9_1, IIC9_2, IIC9_3, 821 ONFICTL, 822 MMC1, MMC2, 823 ECCU, 824 PCIC, 825 G200, 826 RSPI, 827 SGPIO, 828 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19, 829 DMINT20, DMINT21, DMINT22, DMINT23, 830 DDRECC, 831 TSIP, 832 PCIE_BRIDGE, 833 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B, 834 GETHER0, GETHER1, GETHER2, 835 PBIA, PBIB, PBIC, 836 DMAE2, DMAE3, 837 SERMUX2, SERMUX3, 838 839 /* interrupt groups */ 840 841 TMU012, TMU345, 842 }; 843 844 static struct intc_vect vectors[] __initdata = { 845 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0), 846 INTC_VECT(SDHI, 0x4c0), 847 INTC_VECT(DVC, 0x4e0), 848 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), 849 INTC_VECT(IRQ10, 0x540), 850 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 851 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 852 INTC_VECT(HUDI, 0x600), 853 INTC_VECT(ARC4, 0x620), 854 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660), 855 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0), 856 INTC_VECT(DMAC0_5, 0x6c0), 857 INTC_VECT(IRQ11, 0x6e0), 858 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), 859 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), 860 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0), 861 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0), 862 INTC_VECT(USB0, 0x840), 863 INTC_VECT(IRQ12, 0x880), 864 INTC_VECT(JMC, 0x8a0), 865 INTC_VECT(SPI1, 0x8c0), 866 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900), 867 INTC_VECT(USB1, 0x920), 868 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), 869 INTC_VECT(TMR45, 0xa40), 870 INTC_VECT(FRT, 0xa80), 871 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), 872 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), 873 INTC_VECT(LPC, 0xb20), 874 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), 875 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), 876 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), 877 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20), 878 INTC_VECT(PECI2, 0xc40), 879 INTC_VECT(IRQ15, 0xc60), 880 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), 881 INTC_VECT(SPI0, 0xcc0), 882 INTC_VECT(ADC1, 0xce0), 883 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20), 884 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60), 885 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 886 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 887 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 888 INTC_VECT(TMU5, 0xe40), 889 INTC_VECT(ADC0, 0xe60), 890 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20), 891 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60), 892 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420), 893 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460), 894 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0), 895 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520), 896 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560), 897 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600), 898 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640), 899 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700), 900 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800), 901 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840), 902 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), 903 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), 904 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), 905 INTC_VECT(IIC6_2, 0x1920), 906 INTC_VECT(ONFICTL, 0x1960), 907 INTC_VECT(IIC6_3, 0x1980), 908 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), 909 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), 910 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), 911 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), 912 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), 913 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), 914 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80), 915 INTC_VECT(ECCU, 0x1cc0), 916 INTC_VECT(PCIC, 0x1ce0), 917 INTC_VECT(G200, 0x1d00), 918 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0), 919 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0), 920 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0), 921 INTC_VECT(PECI5, 0x1f00), 922 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0), 923 INTC_VECT(SGPIO, 0x1fc0), 924 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420), 925 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460), 926 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0), 927 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520), 928 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560), 929 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600), 930 INTC_VECT(DDRECC, 0x2620), 931 INTC_VECT(TSIP, 0x2640), 932 INTC_VECT(PCIE_BRIDGE, 0x27c0), 933 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820), 934 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860), 935 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0), 936 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0), 937 INTC_VECT(WDT8B, 0x2900), 938 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980), 939 INTC_VECT(GETHER2, 0x29a0), 940 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20), 941 INTC_VECT(PBIC, 0x2a40), 942 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80), 943 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40), 944 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80), 945 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20), 946 }; 947 948 static struct intc_group groups[] __initdata = { 949 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 950 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 951 }; 952 953 static struct intc_mask_reg mask_registers[] __initdata = { 954 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 955 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 956 957 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 958 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 959 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 960 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 961 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, 962 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 963 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 964 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 965 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 966 967 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 968 { 0, 0, 0, 0, 0, 0, 0, 0, 969 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45, 970 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5, 971 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012 972 } }, 973 974 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 975 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, 976 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, 977 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1, 978 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC 979 } }, 980 981 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ 982 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0, 983 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, 984 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, 985 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2 986 } }, 987 988 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */ 989 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2, 990 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, 991 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3, 992 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 993 } }, 994 995 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */ 996 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0, 997 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC, 998 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP, 999 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22 1000 } }, 1001 1002 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */ 1003 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0, 1004 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0, 1005 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8, 1006 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17 1007 } }, 1008 }; 1009 1010 #define INTPRI 0xffd00010 1011 #define INT2PRI0 0xffd40000 1012 #define INT2PRI1 0xffd40004 1013 #define INT2PRI2 0xffd40008 1014 #define INT2PRI3 0xffd4000c 1015 #define INT2PRI4 0xffd40010 1016 #define INT2PRI5 0xffd40014 1017 #define INT2PRI6 0xffd40018 1018 #define INT2PRI7 0xffd4001c 1019 #define INT2PRI8 0xffd400a0 1020 #define INT2PRI9 0xffd400a4 1021 #define INT2PRI10 0xffd400a8 1022 #define INT2PRI11 0xffd400ac 1023 #define INT2PRI12 0xffd400b0 1024 #define INT2PRI13 0xffd400b4 1025 #define INT2PRI14 0xffd400b8 1026 #define INT2PRI15 0xffd400bc 1027 #define INT2PRI16 0xffd10000 1028 #define INT2PRI17 0xffd10004 1029 #define INT2PRI18 0xffd10008 1030 #define INT2PRI19 0xffd1000c 1031 #define INT2PRI20 0xffd10010 1032 #define INT2PRI21 0xffd10014 1033 #define INT2PRI22 0xffd10018 1034 #define INT2PRI23 0xffd1001c 1035 #define INT2PRI24 0xffd100a0 1036 #define INT2PRI25 0xffd100a4 1037 #define INT2PRI26 0xffd100a8 1038 #define INT2PRI27 0xffd100ac 1039 #define INT2PRI28 0xffd100b0 1040 #define INT2PRI29 0xffd100b4 1041 #define INT2PRI30 0xffd100b8 1042 #define INT2PRI31 0xffd100bc 1043 #define INT2PRI32 0xffd20000 1044 #define INT2PRI33 0xffd20004 1045 #define INT2PRI34 0xffd20008 1046 #define INT2PRI35 0xffd2000c 1047 #define INT2PRI36 0xffd20010 1048 #define INT2PRI37 0xffd20014 1049 #define INT2PRI38 0xffd20018 1050 #define INT2PRI39 0xffd2001c 1051 #define INT2PRI40 0xffd200a0 1052 #define INT2PRI41 0xffd200a4 1053 #define INT2PRI42 0xffd200a8 1054 #define INT2PRI43 0xffd200ac 1055 #define INT2PRI44 0xffd200b0 1056 #define INT2PRI45 0xffd200b4 1057 #define INT2PRI46 0xffd200b8 1058 #define INT2PRI47 0xffd200bc 1059 1060 static struct intc_prio_reg prio_registers[] __initdata = { 1061 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, 1062 IRQ4, IRQ5, IRQ6, IRQ7 } }, 1063 1064 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, 1065 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, 1066 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } }, 1067 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } }, 1068 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, 1069 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } }, 1070 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } }, 1071 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, 1072 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, 1073 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, 1074 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } }, 1075 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } }, 1076 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, 1077 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, 1078 1079 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, 1080 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } }, 1081 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, 1082 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, 1083 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, 1084 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, 1085 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } }, 1086 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } }, 1087 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } }, 1088 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, 1089 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } }, 1090 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } }, 1091 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } }, 1092 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, 1093 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } }, 1094 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, 1095 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } }, 1096 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } }, 1097 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } }, 1098 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } }, 1099 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } }, 1100 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } }, 1101 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } }, 1102 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } }, 1103 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } }, 1104 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } }, 1105 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } }, 1106 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } }, 1107 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } }, 1108 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } }, 1109 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } }, 1110 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } }, 1111 }; 1112 1113 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = { 1114 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12, 1115 IRQ11, IRQ10, IRQ9, IRQ8 } }, 1116 }; 1117 1118 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, 1119 mask_registers, prio_registers, 1120 sense_registers_irq8to15); 1121 1122 /* Support for external interrupt pins in IRQ mode */ 1123 static struct intc_vect vectors_irq0123[] __initdata = { 1124 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), 1125 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), 1126 }; 1127 1128 static struct intc_vect vectors_irq4567[] __initdata = { 1129 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340), 1130 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), 1131 }; 1132 1133 static struct intc_sense_reg sense_registers[] __initdata = { 1134 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 1135 IRQ4, IRQ5, IRQ6, IRQ7 } }, 1136 }; 1137 1138 static struct intc_mask_reg ack_registers[] __initdata = { 1139 { 0xffd00024, 0, 32, /* INTREQ */ 1140 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1141 }; 1142 1143 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123", 1144 vectors_irq0123, NULL, mask_registers, 1145 prio_registers, sense_registers, ack_registers); 1146 1147 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567", 1148 vectors_irq4567, NULL, mask_registers, 1149 prio_registers, sense_registers, ack_registers); 1150 1151 /* External interrupt pins in IRL mode */ 1152 static struct intc_vect vectors_irl0123[] __initdata = { 1153 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), 1154 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), 1155 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), 1156 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), 1157 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), 1158 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), 1159 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), 1160 INTC_VECT(IRL0_HHHL, 0x3c0), 1161 }; 1162 1163 static struct intc_vect vectors_irl4567[] __initdata = { 1164 INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220), 1165 INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260), 1166 INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0), 1167 INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0), 1168 INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320), 1169 INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360), 1170 INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0), 1171 INTC_VECT(IRL4_HHHL, 0x3c0), 1172 }; 1173 1174 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123, 1175 NULL, mask_registers, NULL, NULL); 1176 1177 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567, 1178 NULL, mask_registers, NULL, NULL); 1179 1180 #define INTC_ICR0 0xffd00000 1181 #define INTC_INTMSK0 0xffd00044 1182 #define INTC_INTMSK1 0xffd00048 1183 #define INTC_INTMSK2 0xffd40080 1184 #define INTC_INTMSKCLR1 0xffd00068 1185 #define INTC_INTMSKCLR2 0xffd40084 1186 1187 void __init plat_irq_setup(void) 1188 { 1189 /* disable IRQ3-0 + IRQ7-4 */ 1190 __raw_writel(0xff000000, INTC_INTMSK0); 1191 1192 /* disable IRL3-0 + IRL7-4 */ 1193 __raw_writel(0xc0000000, INTC_INTMSK1); 1194 __raw_writel(0xfffefffe, INTC_INTMSK2); 1195 1196 /* select IRL mode for IRL3-0 + IRL7-4 */ 1197 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 1198 1199 /* disable holding function, ie enable "SH-4 Mode" */ 1200 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); 1201 1202 register_intc_controller(&intc_desc); 1203 } 1204 1205 void __init plat_irq_setup_pins(int mode) 1206 { 1207 switch (mode) { 1208 case IRQ_MODE_IRQ7654: 1209 /* select IRQ mode for IRL7-4 */ 1210 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); 1211 register_intc_controller(&intc_desc_irq4567); 1212 break; 1213 case IRQ_MODE_IRQ3210: 1214 /* select IRQ mode for IRL3-0 */ 1215 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); 1216 register_intc_controller(&intc_desc_irq0123); 1217 break; 1218 case IRQ_MODE_IRL7654: 1219 /* enable IRL7-4 but don't provide any masking */ 1220 __raw_writel(0x40000000, INTC_INTMSKCLR1); 1221 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 1222 break; 1223 case IRQ_MODE_IRL3210: 1224 /* enable IRL0-3 but don't provide any masking */ 1225 __raw_writel(0x80000000, INTC_INTMSKCLR1); 1226 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 1227 break; 1228 case IRQ_MODE_IRL7654_MASK: 1229 /* enable IRL7-4 and mask using cpu intc controller */ 1230 __raw_writel(0x40000000, INTC_INTMSKCLR1); 1231 register_intc_controller(&intc_desc_irl4567); 1232 break; 1233 case IRQ_MODE_IRL3210_MASK: 1234 /* enable IRL0-3 and mask using cpu intc controller */ 1235 __raw_writel(0x80000000, INTC_INTMSKCLR1); 1236 register_intc_controller(&intc_desc_irl0123); 1237 break; 1238 default: 1239 BUG(); 1240 } 1241 } 1242 1243 void __init plat_mem_setup(void) 1244 { 1245 } 1246