1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7724 Setup 4 * 5 * Copyright (C) 2009 Renesas Solutions Corp. 6 * 7 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 8 * 9 * Based on SH7723 Setup 10 * Copyright (C) 2008 Paul Mundt 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/mm.h> 16 #include <linux/serial_sci.h> 17 #include <linux/uio_driver.h> 18 #include <linux/sh_dma.h> 19 #include <linux/sh_timer.h> 20 #include <linux/sh_intc.h> 21 #include <linux/io.h> 22 #include <linux/notifier.h> 23 24 #include <asm/cacheflush.h> 25 #include <asm/suspend.h> 26 #include <asm/clock.h> 27 #include <asm/mmzone.h> 28 #include <asm/platform_early.h> 29 30 #include <cpu/dma-register.h> 31 #include <cpu/sh7724.h> 32 33 /* DMA */ 34 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = { 35 { 36 .slave_id = SHDMA_SLAVE_SCIF0_TX, 37 .addr = 0xffe0000c, 38 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 39 .mid_rid = 0x21, 40 }, { 41 .slave_id = SHDMA_SLAVE_SCIF0_RX, 42 .addr = 0xffe00014, 43 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 44 .mid_rid = 0x22, 45 }, { 46 .slave_id = SHDMA_SLAVE_SCIF1_TX, 47 .addr = 0xffe1000c, 48 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 49 .mid_rid = 0x25, 50 }, { 51 .slave_id = SHDMA_SLAVE_SCIF1_RX, 52 .addr = 0xffe10014, 53 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 54 .mid_rid = 0x26, 55 }, { 56 .slave_id = SHDMA_SLAVE_SCIF2_TX, 57 .addr = 0xffe2000c, 58 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 59 .mid_rid = 0x29, 60 }, { 61 .slave_id = SHDMA_SLAVE_SCIF2_RX, 62 .addr = 0xffe20014, 63 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 64 .mid_rid = 0x2a, 65 }, { 66 .slave_id = SHDMA_SLAVE_SCIF3_TX, 67 .addr = 0xa4e30020, 68 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 69 .mid_rid = 0x2d, 70 }, { 71 .slave_id = SHDMA_SLAVE_SCIF3_RX, 72 .addr = 0xa4e30024, 73 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 74 .mid_rid = 0x2e, 75 }, { 76 .slave_id = SHDMA_SLAVE_SCIF4_TX, 77 .addr = 0xa4e40020, 78 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 79 .mid_rid = 0x31, 80 }, { 81 .slave_id = SHDMA_SLAVE_SCIF4_RX, 82 .addr = 0xa4e40024, 83 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 84 .mid_rid = 0x32, 85 }, { 86 .slave_id = SHDMA_SLAVE_SCIF5_TX, 87 .addr = 0xa4e50020, 88 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 89 .mid_rid = 0x35, 90 }, { 91 .slave_id = SHDMA_SLAVE_SCIF5_RX, 92 .addr = 0xa4e50024, 93 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 94 .mid_rid = 0x36, 95 }, { 96 .slave_id = SHDMA_SLAVE_USB0D0_TX, 97 .addr = 0xA4D80100, 98 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 99 .mid_rid = 0x73, 100 }, { 101 .slave_id = SHDMA_SLAVE_USB0D0_RX, 102 .addr = 0xA4D80100, 103 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 104 .mid_rid = 0x73, 105 }, { 106 .slave_id = SHDMA_SLAVE_USB0D1_TX, 107 .addr = 0xA4D80120, 108 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 109 .mid_rid = 0x77, 110 }, { 111 .slave_id = SHDMA_SLAVE_USB0D1_RX, 112 .addr = 0xA4D80120, 113 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 114 .mid_rid = 0x77, 115 }, { 116 .slave_id = SHDMA_SLAVE_USB1D0_TX, 117 .addr = 0xA4D90100, 118 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 119 .mid_rid = 0xab, 120 }, { 121 .slave_id = SHDMA_SLAVE_USB1D0_RX, 122 .addr = 0xA4D90100, 123 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 124 .mid_rid = 0xab, 125 }, { 126 .slave_id = SHDMA_SLAVE_USB1D1_TX, 127 .addr = 0xA4D90120, 128 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 129 .mid_rid = 0xaf, 130 }, { 131 .slave_id = SHDMA_SLAVE_USB1D1_RX, 132 .addr = 0xA4D90120, 133 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 134 .mid_rid = 0xaf, 135 }, { 136 .slave_id = SHDMA_SLAVE_SDHI0_TX, 137 .addr = 0x04ce0030, 138 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 139 .mid_rid = 0xc1, 140 }, { 141 .slave_id = SHDMA_SLAVE_SDHI0_RX, 142 .addr = 0x04ce0030, 143 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 144 .mid_rid = 0xc2, 145 }, { 146 .slave_id = SHDMA_SLAVE_SDHI1_TX, 147 .addr = 0x04cf0030, 148 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 149 .mid_rid = 0xc9, 150 }, { 151 .slave_id = SHDMA_SLAVE_SDHI1_RX, 152 .addr = 0x04cf0030, 153 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 154 .mid_rid = 0xca, 155 }, 156 }; 157 158 static const struct sh_dmae_channel sh7724_dmae_channels[] = { 159 { 160 .offset = 0, 161 .dmars = 0, 162 .dmars_bit = 0, 163 }, { 164 .offset = 0x10, 165 .dmars = 0, 166 .dmars_bit = 8, 167 }, { 168 .offset = 0x20, 169 .dmars = 4, 170 .dmars_bit = 0, 171 }, { 172 .offset = 0x30, 173 .dmars = 4, 174 .dmars_bit = 8, 175 }, { 176 .offset = 0x50, 177 .dmars = 8, 178 .dmars_bit = 0, 179 }, { 180 .offset = 0x60, 181 .dmars = 8, 182 .dmars_bit = 8, 183 } 184 }; 185 186 static const unsigned int ts_shift[] = TS_SHIFT; 187 188 static struct sh_dmae_pdata dma_platform_data = { 189 .slave = sh7724_dmae_slaves, 190 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves), 191 .channel = sh7724_dmae_channels, 192 .channel_num = ARRAY_SIZE(sh7724_dmae_channels), 193 .ts_low_shift = CHCR_TS_LOW_SHIFT, 194 .ts_low_mask = CHCR_TS_LOW_MASK, 195 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 196 .ts_high_mask = CHCR_TS_HIGH_MASK, 197 .ts_shift = ts_shift, 198 .ts_shift_num = ARRAY_SIZE(ts_shift), 199 .dmaor_init = DMAOR_INIT, 200 }; 201 202 /* Resource order important! */ 203 static struct resource sh7724_dmae0_resources[] = { 204 { 205 /* Channel registers and DMAOR */ 206 .start = 0xfe008020, 207 .end = 0xfe00808f, 208 .flags = IORESOURCE_MEM, 209 }, 210 { 211 /* DMARSx */ 212 .start = 0xfe009000, 213 .end = 0xfe00900b, 214 .flags = IORESOURCE_MEM, 215 }, 216 { 217 .name = "error_irq", 218 .start = evt2irq(0xbc0), 219 .end = evt2irq(0xbc0), 220 .flags = IORESOURCE_IRQ, 221 }, 222 { 223 /* IRQ for channels 0-3 */ 224 .start = evt2irq(0x800), 225 .end = evt2irq(0x860), 226 .flags = IORESOURCE_IRQ, 227 }, 228 { 229 /* IRQ for channels 4-5 */ 230 .start = evt2irq(0xb80), 231 .end = evt2irq(0xba0), 232 .flags = IORESOURCE_IRQ, 233 }, 234 }; 235 236 /* Resource order important! */ 237 static struct resource sh7724_dmae1_resources[] = { 238 { 239 /* Channel registers and DMAOR */ 240 .start = 0xfdc08020, 241 .end = 0xfdc0808f, 242 .flags = IORESOURCE_MEM, 243 }, 244 { 245 /* DMARSx */ 246 .start = 0xfdc09000, 247 .end = 0xfdc0900b, 248 .flags = IORESOURCE_MEM, 249 }, 250 { 251 .name = "error_irq", 252 .start = evt2irq(0xb40), 253 .end = evt2irq(0xb40), 254 .flags = IORESOURCE_IRQ, 255 }, 256 { 257 /* IRQ for channels 0-3 */ 258 .start = evt2irq(0x700), 259 .end = evt2irq(0x760), 260 .flags = IORESOURCE_IRQ, 261 }, 262 { 263 /* IRQ for channels 4-5 */ 264 .start = evt2irq(0xb00), 265 .end = evt2irq(0xb20), 266 .flags = IORESOURCE_IRQ, 267 }, 268 }; 269 270 static struct platform_device dma0_device = { 271 .name = "sh-dma-engine", 272 .id = 0, 273 .resource = sh7724_dmae0_resources, 274 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), 275 .dev = { 276 .platform_data = &dma_platform_data, 277 }, 278 }; 279 280 static struct platform_device dma1_device = { 281 .name = "sh-dma-engine", 282 .id = 1, 283 .resource = sh7724_dmae1_resources, 284 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), 285 .dev = { 286 .platform_data = &dma_platform_data, 287 }, 288 }; 289 290 /* Serial */ 291 static struct plat_sci_port scif0_platform_data = { 292 .scscr = SCSCR_REIE, 293 .type = PORT_SCIF, 294 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 295 }; 296 297 static struct resource scif0_resources[] = { 298 DEFINE_RES_MEM(0xffe00000, 0x100), 299 DEFINE_RES_IRQ(evt2irq(0xc00)), 300 }; 301 302 static struct platform_device scif0_device = { 303 .name = "sh-sci", 304 .id = 0, 305 .resource = scif0_resources, 306 .num_resources = ARRAY_SIZE(scif0_resources), 307 .dev = { 308 .platform_data = &scif0_platform_data, 309 }, 310 }; 311 312 static struct plat_sci_port scif1_platform_data = { 313 .scscr = SCSCR_REIE, 314 .type = PORT_SCIF, 315 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 316 }; 317 318 static struct resource scif1_resources[] = { 319 DEFINE_RES_MEM(0xffe10000, 0x100), 320 DEFINE_RES_IRQ(evt2irq(0xc20)), 321 }; 322 323 static struct platform_device scif1_device = { 324 .name = "sh-sci", 325 .id = 1, 326 .resource = scif1_resources, 327 .num_resources = ARRAY_SIZE(scif1_resources), 328 .dev = { 329 .platform_data = &scif1_platform_data, 330 }, 331 }; 332 333 static struct plat_sci_port scif2_platform_data = { 334 .scscr = SCSCR_REIE, 335 .type = PORT_SCIF, 336 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 337 }; 338 339 static struct resource scif2_resources[] = { 340 DEFINE_RES_MEM(0xffe20000, 0x100), 341 DEFINE_RES_IRQ(evt2irq(0xc40)), 342 }; 343 344 static struct platform_device scif2_device = { 345 .name = "sh-sci", 346 .id = 2, 347 .resource = scif2_resources, 348 .num_resources = ARRAY_SIZE(scif2_resources), 349 .dev = { 350 .platform_data = &scif2_platform_data, 351 }, 352 }; 353 354 static struct plat_sci_port scif3_platform_data = { 355 .sampling_rate = 8, 356 .type = PORT_SCIFA, 357 }; 358 359 static struct resource scif3_resources[] = { 360 DEFINE_RES_MEM(0xa4e30000, 0x100), 361 DEFINE_RES_IRQ(evt2irq(0x900)), 362 }; 363 364 static struct platform_device scif3_device = { 365 .name = "sh-sci", 366 .id = 3, 367 .resource = scif3_resources, 368 .num_resources = ARRAY_SIZE(scif3_resources), 369 .dev = { 370 .platform_data = &scif3_platform_data, 371 }, 372 }; 373 374 static struct plat_sci_port scif4_platform_data = { 375 .sampling_rate = 8, 376 .type = PORT_SCIFA, 377 }; 378 379 static struct resource scif4_resources[] = { 380 DEFINE_RES_MEM(0xa4e40000, 0x100), 381 DEFINE_RES_IRQ(evt2irq(0xd00)), 382 }; 383 384 static struct platform_device scif4_device = { 385 .name = "sh-sci", 386 .id = 4, 387 .resource = scif4_resources, 388 .num_resources = ARRAY_SIZE(scif4_resources), 389 .dev = { 390 .platform_data = &scif4_platform_data, 391 }, 392 }; 393 394 static struct plat_sci_port scif5_platform_data = { 395 .sampling_rate = 8, 396 .type = PORT_SCIFA, 397 }; 398 399 static struct resource scif5_resources[] = { 400 DEFINE_RES_MEM(0xa4e50000, 0x100), 401 DEFINE_RES_IRQ(evt2irq(0xfa0)), 402 }; 403 404 static struct platform_device scif5_device = { 405 .name = "sh-sci", 406 .id = 5, 407 .resource = scif5_resources, 408 .num_resources = ARRAY_SIZE(scif5_resources), 409 .dev = { 410 .platform_data = &scif5_platform_data, 411 }, 412 }; 413 414 /* RTC */ 415 static struct resource rtc_resources[] = { 416 [0] = { 417 .start = 0xa465fec0, 418 .end = 0xa465fec0 + 0x58 - 1, 419 .flags = IORESOURCE_IO, 420 }, 421 [1] = { 422 /* Period IRQ */ 423 .start = evt2irq(0xaa0), 424 .flags = IORESOURCE_IRQ, 425 }, 426 [2] = { 427 /* Carry IRQ */ 428 .start = evt2irq(0xac0), 429 .flags = IORESOURCE_IRQ, 430 }, 431 [3] = { 432 /* Alarm IRQ */ 433 .start = evt2irq(0xa80), 434 .flags = IORESOURCE_IRQ, 435 }, 436 }; 437 438 static struct platform_device rtc_device = { 439 .name = "sh-rtc", 440 .id = -1, 441 .num_resources = ARRAY_SIZE(rtc_resources), 442 .resource = rtc_resources, 443 }; 444 445 /* I2C0 */ 446 static struct resource iic0_resources[] = { 447 [0] = { 448 .name = "IIC0", 449 .start = 0x04470000, 450 .end = 0x04470018 - 1, 451 .flags = IORESOURCE_MEM, 452 }, 453 [1] = { 454 .start = evt2irq(0xe00), 455 .end = evt2irq(0xe60), 456 .flags = IORESOURCE_IRQ, 457 }, 458 }; 459 460 static struct platform_device iic0_device = { 461 .name = "i2c-sh_mobile", 462 .id = 0, /* "i2c0" clock */ 463 .num_resources = ARRAY_SIZE(iic0_resources), 464 .resource = iic0_resources, 465 }; 466 467 /* I2C1 */ 468 static struct resource iic1_resources[] = { 469 [0] = { 470 .name = "IIC1", 471 .start = 0x04750000, 472 .end = 0x04750018 - 1, 473 .flags = IORESOURCE_MEM, 474 }, 475 [1] = { 476 .start = evt2irq(0xd80), 477 .end = evt2irq(0xde0), 478 .flags = IORESOURCE_IRQ, 479 }, 480 }; 481 482 static struct platform_device iic1_device = { 483 .name = "i2c-sh_mobile", 484 .id = 1, /* "i2c1" clock */ 485 .num_resources = ARRAY_SIZE(iic1_resources), 486 .resource = iic1_resources, 487 }; 488 489 /* VPU */ 490 static struct uio_info vpu_platform_data = { 491 .name = "VPU5F", 492 .version = "0", 493 .irq = evt2irq(0x980), 494 }; 495 496 static struct resource vpu_resources[] = { 497 [0] = { 498 .name = "VPU", 499 .start = 0xfe900000, 500 .end = 0xfe902807, 501 .flags = IORESOURCE_MEM, 502 }, 503 [1] = { 504 /* place holder for contiguous memory */ 505 }, 506 }; 507 508 static struct platform_device vpu_device = { 509 .name = "uio_pdrv_genirq", 510 .id = 0, 511 .dev = { 512 .platform_data = &vpu_platform_data, 513 }, 514 .resource = vpu_resources, 515 .num_resources = ARRAY_SIZE(vpu_resources), 516 }; 517 518 /* VEU0 */ 519 static struct uio_info veu0_platform_data = { 520 .name = "VEU3F0", 521 .version = "0", 522 .irq = evt2irq(0xc60), 523 }; 524 525 static struct resource veu0_resources[] = { 526 [0] = { 527 .name = "VEU3F0", 528 .start = 0xfe920000, 529 .end = 0xfe9200cb, 530 .flags = IORESOURCE_MEM, 531 }, 532 [1] = { 533 /* place holder for contiguous memory */ 534 }, 535 }; 536 537 static struct platform_device veu0_device = { 538 .name = "uio_pdrv_genirq", 539 .id = 1, 540 .dev = { 541 .platform_data = &veu0_platform_data, 542 }, 543 .resource = veu0_resources, 544 .num_resources = ARRAY_SIZE(veu0_resources), 545 }; 546 547 /* VEU1 */ 548 static struct uio_info veu1_platform_data = { 549 .name = "VEU3F1", 550 .version = "0", 551 .irq = evt2irq(0x8c0), 552 }; 553 554 static struct resource veu1_resources[] = { 555 [0] = { 556 .name = "VEU3F1", 557 .start = 0xfe924000, 558 .end = 0xfe9240cb, 559 .flags = IORESOURCE_MEM, 560 }, 561 [1] = { 562 /* place holder for contiguous memory */ 563 }, 564 }; 565 566 static struct platform_device veu1_device = { 567 .name = "uio_pdrv_genirq", 568 .id = 2, 569 .dev = { 570 .platform_data = &veu1_platform_data, 571 }, 572 .resource = veu1_resources, 573 .num_resources = ARRAY_SIZE(veu1_resources), 574 }; 575 576 /* BEU0 */ 577 static struct uio_info beu0_platform_data = { 578 .name = "BEU0", 579 .version = "0", 580 .irq = evt2irq(0x8A0), 581 }; 582 583 static struct resource beu0_resources[] = { 584 [0] = { 585 .name = "BEU0", 586 .start = 0xfe930000, 587 .end = 0xfe933400, 588 .flags = IORESOURCE_MEM, 589 }, 590 [1] = { 591 /* place holder for contiguous memory */ 592 }, 593 }; 594 595 static struct platform_device beu0_device = { 596 .name = "uio_pdrv_genirq", 597 .id = 6, 598 .dev = { 599 .platform_data = &beu0_platform_data, 600 }, 601 .resource = beu0_resources, 602 .num_resources = ARRAY_SIZE(beu0_resources), 603 }; 604 605 /* BEU1 */ 606 static struct uio_info beu1_platform_data = { 607 .name = "BEU1", 608 .version = "0", 609 .irq = evt2irq(0xA00), 610 }; 611 612 static struct resource beu1_resources[] = { 613 [0] = { 614 .name = "BEU1", 615 .start = 0xfe940000, 616 .end = 0xfe943400, 617 .flags = IORESOURCE_MEM, 618 }, 619 [1] = { 620 /* place holder for contiguous memory */ 621 }, 622 }; 623 624 static struct platform_device beu1_device = { 625 .name = "uio_pdrv_genirq", 626 .id = 7, 627 .dev = { 628 .platform_data = &beu1_platform_data, 629 }, 630 .resource = beu1_resources, 631 .num_resources = ARRAY_SIZE(beu1_resources), 632 }; 633 634 static struct sh_timer_config cmt_platform_data = { 635 .channels_mask = 0x20, 636 }; 637 638 static struct resource cmt_resources[] = { 639 DEFINE_RES_MEM(0x044a0000, 0x70), 640 DEFINE_RES_IRQ(evt2irq(0xf00)), 641 }; 642 643 static struct platform_device cmt_device = { 644 .name = "sh-cmt-32", 645 .id = 0, 646 .dev = { 647 .platform_data = &cmt_platform_data, 648 }, 649 .resource = cmt_resources, 650 .num_resources = ARRAY_SIZE(cmt_resources), 651 }; 652 653 static struct sh_timer_config tmu0_platform_data = { 654 .channels_mask = 7, 655 }; 656 657 static struct resource tmu0_resources[] = { 658 DEFINE_RES_MEM(0xffd80000, 0x2c), 659 DEFINE_RES_IRQ(evt2irq(0x400)), 660 DEFINE_RES_IRQ(evt2irq(0x420)), 661 DEFINE_RES_IRQ(evt2irq(0x440)), 662 }; 663 664 static struct platform_device tmu0_device = { 665 .name = "sh-tmu", 666 .id = 0, 667 .dev = { 668 .platform_data = &tmu0_platform_data, 669 }, 670 .resource = tmu0_resources, 671 .num_resources = ARRAY_SIZE(tmu0_resources), 672 }; 673 674 static struct sh_timer_config tmu1_platform_data = { 675 .channels_mask = 7, 676 }; 677 678 static struct resource tmu1_resources[] = { 679 DEFINE_RES_MEM(0xffd90000, 0x2c), 680 DEFINE_RES_IRQ(evt2irq(0x920)), 681 DEFINE_RES_IRQ(evt2irq(0x940)), 682 DEFINE_RES_IRQ(evt2irq(0x960)), 683 }; 684 685 static struct platform_device tmu1_device = { 686 .name = "sh-tmu", 687 .id = 1, 688 .dev = { 689 .platform_data = &tmu1_platform_data, 690 }, 691 .resource = tmu1_resources, 692 .num_resources = ARRAY_SIZE(tmu1_resources), 693 }; 694 695 /* JPU */ 696 static struct uio_info jpu_platform_data = { 697 .name = "JPU", 698 .version = "0", 699 .irq = evt2irq(0x560), 700 }; 701 702 static struct resource jpu_resources[] = { 703 [0] = { 704 .name = "JPU", 705 .start = 0xfe980000, 706 .end = 0xfe9902d3, 707 .flags = IORESOURCE_MEM, 708 }, 709 [1] = { 710 /* place holder for contiguous memory */ 711 }, 712 }; 713 714 static struct platform_device jpu_device = { 715 .name = "uio_pdrv_genirq", 716 .id = 3, 717 .dev = { 718 .platform_data = &jpu_platform_data, 719 }, 720 .resource = jpu_resources, 721 .num_resources = ARRAY_SIZE(jpu_resources), 722 }; 723 724 /* SPU2DSP0 */ 725 static struct uio_info spu0_platform_data = { 726 .name = "SPU2DSP0", 727 .version = "0", 728 .irq = evt2irq(0xcc0), 729 }; 730 731 static struct resource spu0_resources[] = { 732 [0] = { 733 .name = "SPU2DSP0", 734 .start = 0xFE200000, 735 .end = 0xFE2FFFFF, 736 .flags = IORESOURCE_MEM, 737 }, 738 [1] = { 739 /* place holder for contiguous memory */ 740 }, 741 }; 742 743 static struct platform_device spu0_device = { 744 .name = "uio_pdrv_genirq", 745 .id = 4, 746 .dev = { 747 .platform_data = &spu0_platform_data, 748 }, 749 .resource = spu0_resources, 750 .num_resources = ARRAY_SIZE(spu0_resources), 751 }; 752 753 /* SPU2DSP1 */ 754 static struct uio_info spu1_platform_data = { 755 .name = "SPU2DSP1", 756 .version = "0", 757 .irq = evt2irq(0xce0), 758 }; 759 760 static struct resource spu1_resources[] = { 761 [0] = { 762 .name = "SPU2DSP1", 763 .start = 0xFE300000, 764 .end = 0xFE3FFFFF, 765 .flags = IORESOURCE_MEM, 766 }, 767 [1] = { 768 /* place holder for contiguous memory */ 769 }, 770 }; 771 772 static struct platform_device spu1_device = { 773 .name = "uio_pdrv_genirq", 774 .id = 5, 775 .dev = { 776 .platform_data = &spu1_platform_data, 777 }, 778 .resource = spu1_resources, 779 .num_resources = ARRAY_SIZE(spu1_resources), 780 }; 781 782 static struct platform_device *sh7724_devices[] __initdata = { 783 &scif0_device, 784 &scif1_device, 785 &scif2_device, 786 &scif3_device, 787 &scif4_device, 788 &scif5_device, 789 &cmt_device, 790 &tmu0_device, 791 &tmu1_device, 792 &dma0_device, 793 &dma1_device, 794 &rtc_device, 795 &iic0_device, 796 &iic1_device, 797 &vpu_device, 798 &veu0_device, 799 &veu1_device, 800 &beu0_device, 801 &beu1_device, 802 &jpu_device, 803 &spu0_device, 804 &spu1_device, 805 }; 806 807 static int __init sh7724_devices_setup(void) 808 { 809 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 810 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 811 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 812 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 813 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20); 814 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20); 815 816 return platform_add_devices(sh7724_devices, 817 ARRAY_SIZE(sh7724_devices)); 818 } 819 arch_initcall(sh7724_devices_setup); 820 821 static struct platform_device *sh7724_early_devices[] __initdata = { 822 &scif0_device, 823 &scif1_device, 824 &scif2_device, 825 &scif3_device, 826 &scif4_device, 827 &scif5_device, 828 &cmt_device, 829 &tmu0_device, 830 &tmu1_device, 831 }; 832 833 void __init plat_early_device_setup(void) 834 { 835 sh_early_platform_add_devices(sh7724_early_devices, 836 ARRAY_SIZE(sh7724_early_devices)); 837 } 838 839 #define RAMCR_CACHE_L2FC 0x0002 840 #define RAMCR_CACHE_L2E 0x0001 841 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 842 843 void l2_cache_init(void) 844 { 845 /* Enable L2 cache */ 846 __raw_writel(L2_CACHE_ENABLE, RAMCR); 847 } 848 849 enum { 850 UNUSED = 0, 851 ENABLED, 852 DISABLED, 853 854 /* interrupt sources */ 855 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 856 HUDI, 857 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, 858 _2DG_TRI, _2DG_INI, _2DG_CEI, 859 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, 860 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, 861 SCIFA3, 862 VPU, 863 TPU, 864 CEU1, 865 BEU1, 866 USB0, USB1, 867 ATAPI, 868 RTC_ATI, RTC_PRI, RTC_CUI, 869 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, 870 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, 871 KEYSC, 872 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, 873 VEU0, 874 MSIOF_MSIOFI0, MSIOF_MSIOFI1, 875 SPU_SPUI0, SPU_SPUI1, 876 SCIFA4, 877 ICB, 878 ETHI, 879 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 880 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 881 CMT, 882 TSIF, 883 FSI, 884 SCIFA5, 885 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 886 IRDA, 887 JPU, 888 _2DDMAC, 889 MMC_MMC2I, MMC_MMC3I, 890 LCDC, 891 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 892 893 /* interrupt groups */ 894 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, 895 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, 896 }; 897 898 static struct intc_vect vectors[] __initdata = { 899 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 900 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 901 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 902 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 903 904 INTC_VECT(DMAC1A_DEI0, 0x700), 905 INTC_VECT(DMAC1A_DEI1, 0x720), 906 INTC_VECT(DMAC1A_DEI2, 0x740), 907 INTC_VECT(DMAC1A_DEI3, 0x760), 908 909 INTC_VECT(_2DG_TRI, 0x780), 910 INTC_VECT(_2DG_INI, 0x7A0), 911 INTC_VECT(_2DG_CEI, 0x7C0), 912 913 INTC_VECT(DMAC0A_DEI0, 0x800), 914 INTC_VECT(DMAC0A_DEI1, 0x820), 915 INTC_VECT(DMAC0A_DEI2, 0x840), 916 INTC_VECT(DMAC0A_DEI3, 0x860), 917 918 INTC_VECT(VIO_CEU0, 0x880), 919 INTC_VECT(VIO_BEU0, 0x8A0), 920 INTC_VECT(VIO_VEU1, 0x8C0), 921 INTC_VECT(VIO_VOU, 0x8E0), 922 923 INTC_VECT(SCIFA3, 0x900), 924 INTC_VECT(VPU, 0x980), 925 INTC_VECT(TPU, 0x9A0), 926 INTC_VECT(CEU1, 0x9E0), 927 INTC_VECT(BEU1, 0xA00), 928 INTC_VECT(USB0, 0xA20), 929 INTC_VECT(USB1, 0xA40), 930 INTC_VECT(ATAPI, 0xA60), 931 932 INTC_VECT(RTC_ATI, 0xA80), 933 INTC_VECT(RTC_PRI, 0xAA0), 934 INTC_VECT(RTC_CUI, 0xAC0), 935 936 INTC_VECT(DMAC1B_DEI4, 0xB00), 937 INTC_VECT(DMAC1B_DEI5, 0xB20), 938 INTC_VECT(DMAC1B_DADERR, 0xB40), 939 940 INTC_VECT(DMAC0B_DEI4, 0xB80), 941 INTC_VECT(DMAC0B_DEI5, 0xBA0), 942 INTC_VECT(DMAC0B_DADERR, 0xBC0), 943 944 INTC_VECT(KEYSC, 0xBE0), 945 INTC_VECT(SCIF_SCIF0, 0xC00), 946 INTC_VECT(SCIF_SCIF1, 0xC20), 947 INTC_VECT(SCIF_SCIF2, 0xC40), 948 INTC_VECT(VEU0, 0xC60), 949 INTC_VECT(MSIOF_MSIOFI0, 0xC80), 950 INTC_VECT(MSIOF_MSIOFI1, 0xCA0), 951 INTC_VECT(SPU_SPUI0, 0xCC0), 952 INTC_VECT(SPU_SPUI1, 0xCE0), 953 INTC_VECT(SCIFA4, 0xD00), 954 955 INTC_VECT(ICB, 0xD20), 956 INTC_VECT(ETHI, 0xD60), 957 958 INTC_VECT(I2C1_ALI, 0xD80), 959 INTC_VECT(I2C1_TACKI, 0xDA0), 960 INTC_VECT(I2C1_WAITI, 0xDC0), 961 INTC_VECT(I2C1_DTEI, 0xDE0), 962 963 INTC_VECT(I2C0_ALI, 0xE00), 964 INTC_VECT(I2C0_TACKI, 0xE20), 965 INTC_VECT(I2C0_WAITI, 0xE40), 966 INTC_VECT(I2C0_DTEI, 0xE60), 967 968 INTC_VECT(SDHI0, 0xE80), 969 INTC_VECT(SDHI0, 0xEA0), 970 INTC_VECT(SDHI0, 0xEC0), 971 INTC_VECT(SDHI0, 0xEE0), 972 973 INTC_VECT(CMT, 0xF00), 974 INTC_VECT(TSIF, 0xF20), 975 INTC_VECT(FSI, 0xF80), 976 INTC_VECT(SCIFA5, 0xFA0), 977 978 INTC_VECT(TMU0_TUNI0, 0x400), 979 INTC_VECT(TMU0_TUNI1, 0x420), 980 INTC_VECT(TMU0_TUNI2, 0x440), 981 982 INTC_VECT(IRDA, 0x480), 983 984 INTC_VECT(SDHI1, 0x4E0), 985 INTC_VECT(SDHI1, 0x500), 986 INTC_VECT(SDHI1, 0x520), 987 988 INTC_VECT(JPU, 0x560), 989 INTC_VECT(_2DDMAC, 0x4A0), 990 991 INTC_VECT(MMC_MMC2I, 0x5A0), 992 INTC_VECT(MMC_MMC3I, 0x5C0), 993 994 INTC_VECT(LCDC, 0xF40), 995 996 INTC_VECT(TMU1_TUNI0, 0x920), 997 INTC_VECT(TMU1_TUNI1, 0x940), 998 INTC_VECT(TMU1_TUNI2, 0x960), 999 }; 1000 1001 static struct intc_group groups[] __initdata = { 1002 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), 1003 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), 1004 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), 1005 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), 1006 INTC_GROUP(USB, USB0, USB1), 1007 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 1008 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), 1009 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 1010 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 1011 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 1012 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 1013 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 1014 }; 1015 1016 static struct intc_mask_reg mask_registers[] __initdata = { 1017 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 1018 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 1019 0, ENABLED, ENABLED, ENABLED } }, 1020 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 1021 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 1022 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 1023 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 1024 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, 1025 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 1026 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, 1027 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, 1028 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 1029 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, 1030 JPU, 0, 0, LCDC } }, 1031 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 1032 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 1033 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 1034 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 1035 { 0, 0, ICB, SCIFA4, 1036 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 1037 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 1038 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 1039 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 1040 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 1041 { DISABLED, ENABLED, ENABLED, ENABLED, 1042 0, 0, SCIFA5, FSI } }, 1043 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 1044 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 1045 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 1046 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, 1047 0, RTC_CUI, RTC_PRI, RTC_ATI } }, 1048 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 1049 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, 1050 0, TPU, 0, TSIF } }, 1051 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 1052 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, 1053 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 1054 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1055 }; 1056 1057 static struct intc_prio_reg prio_registers[] __initdata = { 1058 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, 1059 TMU0_TUNI2, IRDA } }, 1060 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, 1061 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, 1062 TMU1_TUNI2, SPU } }, 1063 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, 1064 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, 1065 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, 1066 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, 1067 SCIF_SCIF2, VEU0 } }, 1068 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, 1069 I2C1, I2C0 } }, 1070 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, 1071 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, 1072 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, 1073 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, 1074 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 1075 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1076 }; 1077 1078 static struct intc_sense_reg sense_registers[] __initdata = { 1079 { 0xa414001c, 16, 2, /* ICR1 */ 1080 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1081 }; 1082 1083 static struct intc_mask_reg ack_registers[] __initdata = { 1084 { 0xa4140024, 0, 8, /* INTREQ00 */ 1085 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1086 }; 1087 1088 static struct intc_desc intc_desc __initdata = { 1089 .name = "sh7724", 1090 .force_enable = ENABLED, 1091 .force_disable = DISABLED, 1092 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 1093 prio_registers, sense_registers, ack_registers), 1094 }; 1095 1096 void __init plat_irq_setup(void) 1097 { 1098 register_intc_controller(&intc_desc); 1099 } 1100 1101 static struct { 1102 /* BSC */ 1103 unsigned long mmselr; 1104 unsigned long cs0bcr; 1105 unsigned long cs4bcr; 1106 unsigned long cs5abcr; 1107 unsigned long cs5bbcr; 1108 unsigned long cs6abcr; 1109 unsigned long cs6bbcr; 1110 unsigned long cs4wcr; 1111 unsigned long cs5awcr; 1112 unsigned long cs5bwcr; 1113 unsigned long cs6awcr; 1114 unsigned long cs6bwcr; 1115 /* INTC */ 1116 unsigned short ipra; 1117 unsigned short iprb; 1118 unsigned short iprc; 1119 unsigned short iprd; 1120 unsigned short ipre; 1121 unsigned short iprf; 1122 unsigned short iprg; 1123 unsigned short iprh; 1124 unsigned short ipri; 1125 unsigned short iprj; 1126 unsigned short iprk; 1127 unsigned short iprl; 1128 unsigned char imr0; 1129 unsigned char imr1; 1130 unsigned char imr2; 1131 unsigned char imr3; 1132 unsigned char imr4; 1133 unsigned char imr5; 1134 unsigned char imr6; 1135 unsigned char imr7; 1136 unsigned char imr8; 1137 unsigned char imr9; 1138 unsigned char imr10; 1139 unsigned char imr11; 1140 unsigned char imr12; 1141 /* RWDT */ 1142 unsigned short rwtcnt; 1143 unsigned short rwtcsr; 1144 /* CPG */ 1145 unsigned long irdaclk; 1146 unsigned long spuclk; 1147 } sh7724_rstandby_state; 1148 1149 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb, 1150 unsigned long flags, void *unused) 1151 { 1152 if (!(flags & SUSP_SH_RSTANDBY)) 1153 return NOTIFY_DONE; 1154 1155 /* BCR */ 1156 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ 1157 sh7724_rstandby_state.mmselr |= 0xa5a50000; 1158 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ 1159 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ 1160 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ 1161 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ 1162 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ 1163 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ 1164 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ 1165 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ 1166 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ 1167 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ 1168 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ 1169 1170 /* INTC */ 1171 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */ 1172 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */ 1173 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */ 1174 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */ 1175 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */ 1176 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */ 1177 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */ 1178 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */ 1179 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */ 1180 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */ 1181 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */ 1182 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */ 1183 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */ 1184 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */ 1185 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */ 1186 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */ 1187 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */ 1188 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */ 1189 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */ 1190 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */ 1191 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */ 1192 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */ 1193 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */ 1194 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */ 1195 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */ 1196 1197 /* RWDT */ 1198 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */ 1199 sh7724_rstandby_state.rwtcnt |= 0x5a00; 1200 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */ 1201 sh7724_rstandby_state.rwtcsr |= 0xa500; 1202 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004); 1203 1204 /* CPG */ 1205 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */ 1206 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */ 1207 1208 return NOTIFY_DONE; 1209 } 1210 1211 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb, 1212 unsigned long flags, void *unused) 1213 { 1214 if (!(flags & SUSP_SH_RSTANDBY)) 1215 return NOTIFY_DONE; 1216 1217 /* BCR */ 1218 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ 1219 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ 1220 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ 1221 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ 1222 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ 1223 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ 1224 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ 1225 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ 1226 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ 1227 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */ 1228 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */ 1229 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */ 1230 1231 /* INTC */ 1232 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */ 1233 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */ 1234 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */ 1235 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */ 1236 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */ 1237 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */ 1238 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */ 1239 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */ 1240 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */ 1241 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */ 1242 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */ 1243 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */ 1244 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ 1245 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ 1246 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ 1247 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ 1248 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ 1249 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ 1250 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ 1251 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ 1252 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ 1253 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ 1254 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */ 1255 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */ 1256 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */ 1257 1258 /* RWDT */ 1259 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */ 1260 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */ 1261 1262 /* CPG */ 1263 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */ 1264 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */ 1265 1266 return NOTIFY_DONE; 1267 } 1268 1269 static struct notifier_block sh7724_pre_sleep_notifier = { 1270 .notifier_call = sh7724_pre_sleep_notifier_call, 1271 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU), 1272 }; 1273 1274 static struct notifier_block sh7724_post_sleep_notifier = { 1275 .notifier_call = sh7724_post_sleep_notifier_call, 1276 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU), 1277 }; 1278 1279 static int __init sh7724_sleep_setup(void) 1280 { 1281 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list, 1282 &sh7724_pre_sleep_notifier); 1283 1284 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list, 1285 &sh7724_post_sleep_notifier); 1286 return 0; 1287 } 1288 arch_initcall(sh7724_sleep_setup); 1289 1290