1 /* 2 * SH7724 Setup 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * Based on SH7723 Setup 9 * Copyright (C) 2008 Paul Mundt 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/platform_device.h> 16 #include <linux/init.h> 17 #include <linux/serial.h> 18 #include <linux/mm.h> 19 #include <linux/serial_sci.h> 20 #include <linux/uio_driver.h> 21 #include <linux/sh_timer.h> 22 #include <linux/io.h> 23 #include <asm/clock.h> 24 #include <asm/mmzone.h> 25 26 /* Serial */ 27 static struct plat_sci_port sci_platform_data[] = { 28 { 29 .mapbase = 0xffe00000, 30 .flags = UPF_BOOT_AUTOCONF, 31 .type = PORT_SCIF, 32 .irqs = { 80, 80, 80, 80 }, 33 .clk = "scif0", 34 }, { 35 .mapbase = 0xffe10000, 36 .flags = UPF_BOOT_AUTOCONF, 37 .type = PORT_SCIF, 38 .irqs = { 81, 81, 81, 81 }, 39 .clk = "scif1", 40 }, { 41 .mapbase = 0xffe20000, 42 .flags = UPF_BOOT_AUTOCONF, 43 .type = PORT_SCIF, 44 .irqs = { 82, 82, 82, 82 }, 45 .clk = "scif2", 46 }, { 47 .mapbase = 0xa4e30000, 48 .flags = UPF_BOOT_AUTOCONF, 49 .type = PORT_SCIFA, 50 .irqs = { 56, 56, 56, 56 }, 51 .clk = "scif3", 52 }, { 53 .mapbase = 0xa4e40000, 54 .flags = UPF_BOOT_AUTOCONF, 55 .type = PORT_SCIFA, 56 .irqs = { 88, 88, 88, 88 }, 57 .clk = "scif4", 58 }, { 59 .mapbase = 0xa4e50000, 60 .flags = UPF_BOOT_AUTOCONF, 61 .type = PORT_SCIFA, 62 .irqs = { 109, 109, 109, 109 }, 63 .clk = "scif5", 64 }, { 65 .flags = 0, 66 } 67 }; 68 69 static struct platform_device sci_device = { 70 .name = "sh-sci", 71 .id = -1, 72 .dev = { 73 .platform_data = sci_platform_data, 74 }, 75 }; 76 77 /* RTC */ 78 static struct resource rtc_resources[] = { 79 [0] = { 80 .start = 0xa465fec0, 81 .end = 0xa465fec0 + 0x58 - 1, 82 .flags = IORESOURCE_IO, 83 }, 84 [1] = { 85 /* Period IRQ */ 86 .start = 69, 87 .flags = IORESOURCE_IRQ, 88 }, 89 [2] = { 90 /* Carry IRQ */ 91 .start = 70, 92 .flags = IORESOURCE_IRQ, 93 }, 94 [3] = { 95 /* Alarm IRQ */ 96 .start = 68, 97 .flags = IORESOURCE_IRQ, 98 }, 99 }; 100 101 static struct platform_device rtc_device = { 102 .name = "sh-rtc", 103 .id = -1, 104 .num_resources = ARRAY_SIZE(rtc_resources), 105 .resource = rtc_resources, 106 }; 107 108 /* I2C0 */ 109 static struct resource iic0_resources[] = { 110 [0] = { 111 .name = "IIC0", 112 .start = 0x04470000, 113 .end = 0x04470018 - 1, 114 .flags = IORESOURCE_MEM, 115 }, 116 [1] = { 117 .start = 96, 118 .end = 99, 119 .flags = IORESOURCE_IRQ, 120 }, 121 }; 122 123 static struct platform_device iic0_device = { 124 .name = "i2c-sh_mobile", 125 .id = 0, /* "i2c0" clock */ 126 .num_resources = ARRAY_SIZE(iic0_resources), 127 .resource = iic0_resources, 128 }; 129 130 /* I2C1 */ 131 static struct resource iic1_resources[] = { 132 [0] = { 133 .name = "IIC1", 134 .start = 0x04750000, 135 .end = 0x04750018 - 1, 136 .flags = IORESOURCE_MEM, 137 }, 138 [1] = { 139 .start = 92, 140 .end = 95, 141 .flags = IORESOURCE_IRQ, 142 }, 143 }; 144 145 static struct platform_device iic1_device = { 146 .name = "i2c-sh_mobile", 147 .id = 1, /* "i2c1" clock */ 148 .num_resources = ARRAY_SIZE(iic1_resources), 149 .resource = iic1_resources, 150 }; 151 152 /* VPU */ 153 static struct uio_info vpu_platform_data = { 154 .name = "VPU5F", 155 .version = "0", 156 .irq = 60, 157 }; 158 159 static struct resource vpu_resources[] = { 160 [0] = { 161 .name = "VPU", 162 .start = 0xfe900000, 163 .end = 0xfe902807, 164 .flags = IORESOURCE_MEM, 165 }, 166 [1] = { 167 /* place holder for contiguous memory */ 168 }, 169 }; 170 171 static struct platform_device vpu_device = { 172 .name = "uio_pdrv_genirq", 173 .id = 0, 174 .dev = { 175 .platform_data = &vpu_platform_data, 176 }, 177 .resource = vpu_resources, 178 .num_resources = ARRAY_SIZE(vpu_resources), 179 }; 180 181 /* VEU0 */ 182 static struct uio_info veu0_platform_data = { 183 .name = "VEU3F0", 184 .version = "0", 185 .irq = 83, 186 }; 187 188 static struct resource veu0_resources[] = { 189 [0] = { 190 .name = "VEU3F0", 191 .start = 0xfe920000, 192 .end = 0xfe9200cb - 1, 193 .flags = IORESOURCE_MEM, 194 }, 195 [1] = { 196 /* place holder for contiguous memory */ 197 }, 198 }; 199 200 static struct platform_device veu0_device = { 201 .name = "uio_pdrv_genirq", 202 .id = 1, 203 .dev = { 204 .platform_data = &veu0_platform_data, 205 }, 206 .resource = veu0_resources, 207 .num_resources = ARRAY_SIZE(veu0_resources), 208 }; 209 210 /* VEU1 */ 211 static struct uio_info veu1_platform_data = { 212 .name = "VEU3F1", 213 .version = "0", 214 .irq = 54, 215 }; 216 217 static struct resource veu1_resources[] = { 218 [0] = { 219 .name = "VEU3F1", 220 .start = 0xfe924000, 221 .end = 0xfe9240cb - 1, 222 .flags = IORESOURCE_MEM, 223 }, 224 [1] = { 225 /* place holder for contiguous memory */ 226 }, 227 }; 228 229 static struct platform_device veu1_device = { 230 .name = "uio_pdrv_genirq", 231 .id = 2, 232 .dev = { 233 .platform_data = &veu1_platform_data, 234 }, 235 .resource = veu1_resources, 236 .num_resources = ARRAY_SIZE(veu1_resources), 237 }; 238 239 static struct sh_timer_config cmt_platform_data = { 240 .name = "CMT", 241 .channel_offset = 0x60, 242 .timer_bit = 5, 243 .clk = "cmt0", 244 .clockevent_rating = 125, 245 .clocksource_rating = 200, 246 }; 247 248 static struct resource cmt_resources[] = { 249 [0] = { 250 .name = "CMT", 251 .start = 0x044a0060, 252 .end = 0x044a006b, 253 .flags = IORESOURCE_MEM, 254 }, 255 [1] = { 256 .start = 104, 257 .flags = IORESOURCE_IRQ, 258 }, 259 }; 260 261 static struct platform_device cmt_device = { 262 .name = "sh_cmt", 263 .id = 0, 264 .dev = { 265 .platform_data = &cmt_platform_data, 266 }, 267 .resource = cmt_resources, 268 .num_resources = ARRAY_SIZE(cmt_resources), 269 }; 270 271 static struct sh_timer_config tmu0_platform_data = { 272 .name = "TMU0", 273 .channel_offset = 0x04, 274 .timer_bit = 0, 275 .clk = "tmu0", 276 .clockevent_rating = 200, 277 }; 278 279 static struct resource tmu0_resources[] = { 280 [0] = { 281 .name = "TMU0", 282 .start = 0xffd80008, 283 .end = 0xffd80013, 284 .flags = IORESOURCE_MEM, 285 }, 286 [1] = { 287 .start = 16, 288 .flags = IORESOURCE_IRQ, 289 }, 290 }; 291 292 static struct platform_device tmu0_device = { 293 .name = "sh_tmu", 294 .id = 0, 295 .dev = { 296 .platform_data = &tmu0_platform_data, 297 }, 298 .resource = tmu0_resources, 299 .num_resources = ARRAY_SIZE(tmu0_resources), 300 }; 301 302 static struct sh_timer_config tmu1_platform_data = { 303 .name = "TMU1", 304 .channel_offset = 0x10, 305 .timer_bit = 1, 306 .clk = "tmu0", 307 .clocksource_rating = 200, 308 }; 309 310 static struct resource tmu1_resources[] = { 311 [0] = { 312 .name = "TMU1", 313 .start = 0xffd80014, 314 .end = 0xffd8001f, 315 .flags = IORESOURCE_MEM, 316 }, 317 [1] = { 318 .start = 17, 319 .flags = IORESOURCE_IRQ, 320 }, 321 }; 322 323 static struct platform_device tmu1_device = { 324 .name = "sh_tmu", 325 .id = 1, 326 .dev = { 327 .platform_data = &tmu1_platform_data, 328 }, 329 .resource = tmu1_resources, 330 .num_resources = ARRAY_SIZE(tmu1_resources), 331 }; 332 333 static struct sh_timer_config tmu2_platform_data = { 334 .name = "TMU2", 335 .channel_offset = 0x1c, 336 .timer_bit = 2, 337 .clk = "tmu0", 338 }; 339 340 static struct resource tmu2_resources[] = { 341 [0] = { 342 .name = "TMU2", 343 .start = 0xffd80020, 344 .end = 0xffd8002b, 345 .flags = IORESOURCE_MEM, 346 }, 347 [1] = { 348 .start = 18, 349 .flags = IORESOURCE_IRQ, 350 }, 351 }; 352 353 static struct platform_device tmu2_device = { 354 .name = "sh_tmu", 355 .id = 2, 356 .dev = { 357 .platform_data = &tmu2_platform_data, 358 }, 359 .resource = tmu2_resources, 360 .num_resources = ARRAY_SIZE(tmu2_resources), 361 }; 362 363 364 static struct sh_timer_config tmu3_platform_data = { 365 .name = "TMU3", 366 .channel_offset = 0x04, 367 .timer_bit = 0, 368 .clk = "tmu1", 369 }; 370 371 static struct resource tmu3_resources[] = { 372 [0] = { 373 .name = "TMU3", 374 .start = 0xffd90008, 375 .end = 0xffd90013, 376 .flags = IORESOURCE_MEM, 377 }, 378 [1] = { 379 .start = 57, 380 .flags = IORESOURCE_IRQ, 381 }, 382 }; 383 384 static struct platform_device tmu3_device = { 385 .name = "sh_tmu", 386 .id = 3, 387 .dev = { 388 .platform_data = &tmu3_platform_data, 389 }, 390 .resource = tmu3_resources, 391 .num_resources = ARRAY_SIZE(tmu3_resources), 392 }; 393 394 static struct sh_timer_config tmu4_platform_data = { 395 .name = "TMU4", 396 .channel_offset = 0x10, 397 .timer_bit = 1, 398 .clk = "tmu1", 399 }; 400 401 static struct resource tmu4_resources[] = { 402 [0] = { 403 .name = "TMU4", 404 .start = 0xffd90014, 405 .end = 0xffd9001f, 406 .flags = IORESOURCE_MEM, 407 }, 408 [1] = { 409 .start = 58, 410 .flags = IORESOURCE_IRQ, 411 }, 412 }; 413 414 static struct platform_device tmu4_device = { 415 .name = "sh_tmu", 416 .id = 4, 417 .dev = { 418 .platform_data = &tmu4_platform_data, 419 }, 420 .resource = tmu4_resources, 421 .num_resources = ARRAY_SIZE(tmu4_resources), 422 }; 423 424 static struct sh_timer_config tmu5_platform_data = { 425 .name = "TMU5", 426 .channel_offset = 0x1c, 427 .timer_bit = 2, 428 .clk = "tmu1", 429 }; 430 431 static struct resource tmu5_resources[] = { 432 [0] = { 433 .name = "TMU5", 434 .start = 0xffd90020, 435 .end = 0xffd9002b, 436 .flags = IORESOURCE_MEM, 437 }, 438 [1] = { 439 .start = 57, 440 .flags = IORESOURCE_IRQ, 441 }, 442 }; 443 444 static struct platform_device tmu5_device = { 445 .name = "sh_tmu", 446 .id = 5, 447 .dev = { 448 .platform_data = &tmu5_platform_data, 449 }, 450 .resource = tmu5_resources, 451 .num_resources = ARRAY_SIZE(tmu5_resources), 452 }; 453 454 static struct platform_device *sh7724_devices[] __initdata = { 455 &cmt_device, 456 &tmu0_device, 457 &tmu1_device, 458 &tmu2_device, 459 &tmu3_device, 460 &tmu4_device, 461 &tmu5_device, 462 &sci_device, 463 &rtc_device, 464 &iic0_device, 465 &iic1_device, 466 &vpu_device, 467 &veu0_device, 468 &veu1_device, 469 }; 470 471 static int __init sh7724_devices_setup(void) 472 { 473 clk_always_enable("vpu0"); /* VPU */ 474 clk_always_enable("veu1"); /* VEU3F1 */ 475 clk_always_enable("veu0"); /* VEU3F0 */ 476 477 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 478 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 479 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 480 481 return platform_add_devices(sh7724_devices, 482 ARRAY_SIZE(sh7724_devices)); 483 } 484 device_initcall(sh7724_devices_setup); 485 486 static struct platform_device *sh7724_early_devices[] __initdata = { 487 &cmt_device, 488 &tmu0_device, 489 &tmu1_device, 490 &tmu2_device, 491 &tmu3_device, 492 &tmu4_device, 493 &tmu5_device, 494 }; 495 496 void __init plat_early_device_setup(void) 497 { 498 early_platform_add_devices(sh7724_early_devices, 499 ARRAY_SIZE(sh7724_early_devices)); 500 } 501 502 enum { 503 UNUSED = 0, 504 505 /* interrupt sources */ 506 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 507 HUDI, 508 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, 509 _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK, 510 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, 511 VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI, 512 SCIFA_SCIFA0, 513 VPU_VPUI, 514 TPU_TPUI, 515 CEU21I, 516 BEU21I, 517 USB_USI0, 518 ATAPI, 519 RTC_ATI, RTC_PRI, RTC_CUI, 520 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, 521 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, 522 KEYSC_KEYI, 523 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, 524 VEU3F0I, 525 MSIOF_MSIOFI0, MSIOF_MSIOFI1, 526 SPU_SPUI0, SPU_SPUI1, 527 SCIFA_SCIFA1, 528 /* ICB_ICBI, */ 529 ETHI, 530 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 531 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 532 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, 533 CMT_CMTI, 534 TSIF_TSIFI, 535 /* ICB_LMBI, */ 536 FSI_FSI, 537 SCIFA_SCIFA2, 538 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 539 IRDA_IRDAI, 540 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2, 541 JPU_JPUI, 542 MMC_MMCI0, MMC_MMCI1, MMC_MMCI2, 543 LCDC_LCDCI, 544 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 545 546 /* interrupt groups */ 547 DMAC1A, _2DG, DMAC0A, VIO, RTC, 548 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC, 549 }; 550 551 static struct intc_vect vectors[] __initdata = { 552 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 553 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 554 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 555 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 556 557 INTC_VECT(DMAC1A_DEI0, 0x700), 558 INTC_VECT(DMAC1A_DEI1, 0x720), 559 INTC_VECT(DMAC1A_DEI2, 0x740), 560 INTC_VECT(DMAC1A_DEI3, 0x760), 561 562 INTC_VECT(_2DG_TRI, 0x780), 563 INTC_VECT(_2DG_INI, 0x7A0), 564 INTC_VECT(_2DG_CEI, 0x7C0), 565 INTC_VECT(_2DG_BRK, 0x7E0), 566 567 INTC_VECT(DMAC0A_DEI0, 0x800), 568 INTC_VECT(DMAC0A_DEI1, 0x820), 569 INTC_VECT(DMAC0A_DEI2, 0x840), 570 INTC_VECT(DMAC0A_DEI3, 0x860), 571 572 INTC_VECT(VIO_CEU20I, 0x880), 573 INTC_VECT(VIO_BEU20I, 0x8A0), 574 INTC_VECT(VIO_VEU3F1, 0x8C0), 575 INTC_VECT(VIO_VOUI, 0x8E0), 576 577 INTC_VECT(SCIFA_SCIFA0, 0x900), 578 INTC_VECT(VPU_VPUI, 0x980), 579 INTC_VECT(TPU_TPUI, 0x9A0), 580 INTC_VECT(CEU21I, 0x9E0), 581 INTC_VECT(BEU21I, 0xA00), 582 INTC_VECT(USB_USI0, 0xA20), 583 INTC_VECT(ATAPI, 0xA60), 584 585 INTC_VECT(RTC_ATI, 0xA80), 586 INTC_VECT(RTC_PRI, 0xAA0), 587 INTC_VECT(RTC_CUI, 0xAC0), 588 589 INTC_VECT(DMAC1B_DEI4, 0xB00), 590 INTC_VECT(DMAC1B_DEI5, 0xB20), 591 INTC_VECT(DMAC1B_DADERR, 0xB40), 592 593 INTC_VECT(DMAC0B_DEI4, 0xB80), 594 INTC_VECT(DMAC0B_DEI5, 0xBA0), 595 INTC_VECT(DMAC0B_DADERR, 0xBC0), 596 597 INTC_VECT(KEYSC_KEYI, 0xBE0), 598 INTC_VECT(SCIF_SCIF0, 0xC00), 599 INTC_VECT(SCIF_SCIF1, 0xC20), 600 INTC_VECT(SCIF_SCIF2, 0xC40), 601 INTC_VECT(VEU3F0I, 0xC60), 602 INTC_VECT(MSIOF_MSIOFI0, 0xC80), 603 INTC_VECT(MSIOF_MSIOFI1, 0xCA0), 604 INTC_VECT(SPU_SPUI0, 0xCC0), 605 INTC_VECT(SPU_SPUI1, 0xCE0), 606 INTC_VECT(SCIFA_SCIFA1, 0xD00), 607 608 /* INTC_VECT(ICB_ICBI, 0xD20), */ 609 INTC_VECT(ETHI, 0xD60), 610 611 INTC_VECT(I2C1_ALI, 0xD80), 612 INTC_VECT(I2C1_TACKI, 0xDA0), 613 INTC_VECT(I2C1_WAITI, 0xDC0), 614 INTC_VECT(I2C1_DTEI, 0xDE0), 615 616 INTC_VECT(I2C0_ALI, 0xE00), 617 INTC_VECT(I2C0_TACKI, 0xE20), 618 INTC_VECT(I2C0_WAITI, 0xE40), 619 INTC_VECT(I2C0_DTEI, 0xE60), 620 621 INTC_VECT(SDHI0_SDHII0, 0xE80), 622 INTC_VECT(SDHI0_SDHII1, 0xEA0), 623 INTC_VECT(SDHI0_SDHII2, 0xEC0), 624 625 INTC_VECT(CMT_CMTI, 0xF00), 626 INTC_VECT(TSIF_TSIFI, 0xF20), 627 /* INTC_VECT(ICB_LMBI, 0xF60), */ 628 INTC_VECT(FSI_FSI, 0xF80), 629 INTC_VECT(SCIFA_SCIFA2, 0xFA0), 630 631 INTC_VECT(TMU0_TUNI0, 0x400), 632 INTC_VECT(TMU0_TUNI1, 0x420), 633 INTC_VECT(TMU0_TUNI2, 0x440), 634 635 INTC_VECT(IRDA_IRDAI, 0x480), 636 637 INTC_VECT(SDHI1_SDHII0, 0x4E0), 638 INTC_VECT(SDHI1_SDHII1, 0x500), 639 INTC_VECT(SDHI1_SDHII2, 0x520), 640 641 INTC_VECT(JPU_JPUI, 0x560), 642 643 INTC_VECT(MMC_MMCI0, 0x580), 644 INTC_VECT(MMC_MMCI1, 0x5A0), 645 INTC_VECT(MMC_MMCI2, 0x5C0), 646 647 INTC_VECT(LCDC_LCDCI, 0xF40), 648 649 INTC_VECT(TMU1_TUNI0, 0x920), 650 INTC_VECT(TMU1_TUNI1, 0x940), 651 INTC_VECT(TMU1_TUNI2, 0x960), 652 }; 653 654 static struct intc_group groups[] __initdata = { 655 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), 656 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK), 657 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), 658 INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI), 659 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 660 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), 661 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 662 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 663 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 664 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2), 665 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2), 666 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 667 INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2), 668 }; 669 670 /* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */ 671 /* very bad manual !! */ 672 static struct intc_mask_reg mask_registers[] __initdata = { 673 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 674 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 675 /*SDHII3?*/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } }, 676 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 677 { VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I, 678 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 679 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 680 { 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /*SCIFA3*/SCIFA_SCIFA0 } }, 681 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 682 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, 683 SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } }, 684 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 685 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, 686 JPU_JPUI, 0, 0, LCDC_LCDCI } }, 687 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 688 { KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 689 VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 690 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 691 { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1, 692 CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 693 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 694 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 695 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 696 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 697 { /*SDHII3*/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0, 698 0, 0, /*SCIFA5*/SCIFA_SCIFA2, FSI_FSI } }, 699 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 700 { 0, 0, 0, CMT_CMTI, 0, /*USB1*/0, USB_USI0, 0 } }, 701 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 702 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, 703 0, RTC_ATI, RTC_PRI, RTC_CUI } }, 704 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 705 { _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI, 706 0, TPU_TPUI, /*ICB_LMBI*/0, TSIF_TSIFI } }, 707 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 708 { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } }, 709 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 710 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 711 }; 712 713 static struct intc_prio_reg prio_registers[] __initdata = { 714 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, 715 TMU0_TUNI2, IRDA_IRDAI } }, 716 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI, 717 DMAC1A, BEU21I } }, 718 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, 719 TMU1_TUNI2, SPU } }, 720 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } }, 721 { 0xa4080010, 0, 16, 4, /* IPRE */ 722 { DMAC0A, /*BEU?VEU?*/VIO, /*SCIFA3*/SCIFA_SCIFA0, /*VPU5F*/ 723 VPU_VPUI } }, 724 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, 725 USB_USI0, CMT_CMTI } }, 726 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, 727 SCIF_SCIF2, VEU3F0I } }, 728 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, 729 I2C1, I2C0 } }, 730 { 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1, /*ICB*/0, 731 TSIF_TSIFI, _2DG/*ICB?*/ } }, 732 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } }, 733 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, /*ICB?*/0, SDHI0 } }, 734 { 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2, 0, 735 TPU_TPUI, /*2DDMAC*/0 } }, 736 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 737 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 738 }; 739 740 static struct intc_sense_reg sense_registers[] __initdata = { 741 { 0xa414001c, 16, 2, /* ICR1 */ 742 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 743 }; 744 745 static struct intc_mask_reg ack_registers[] __initdata = { 746 { 0xa4140024, 0, 8, /* INTREQ00 */ 747 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 748 }; 749 750 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups, 751 mask_registers, prio_registers, sense_registers, 752 ack_registers); 753 754 void __init plat_irq_setup(void) 755 { 756 register_intc_controller(&intc_desc); 757 } 758