1 /* 2 * SH7724 Setup 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * Based on SH7723 Setup 9 * Copyright (C) 2008 Paul Mundt 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/platform_device.h> 16 #include <linux/init.h> 17 #include <linux/serial.h> 18 #include <linux/mm.h> 19 #include <linux/serial_sci.h> 20 #include <linux/uio_driver.h> 21 #include <linux/sh_dma.h> 22 #include <linux/sh_timer.h> 23 #include <linux/io.h> 24 #include <linux/notifier.h> 25 26 #include <asm/suspend.h> 27 #include <asm/clock.h> 28 #include <asm/mmzone.h> 29 30 #include <cpu/dma-register.h> 31 #include <cpu/sh7724.h> 32 33 /* DMA */ 34 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = { 35 { 36 .slave_id = SHDMA_SLAVE_SCIF0_TX, 37 .addr = 0xffe0000c, 38 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 39 .mid_rid = 0x21, 40 }, { 41 .slave_id = SHDMA_SLAVE_SCIF0_RX, 42 .addr = 0xffe00014, 43 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 44 .mid_rid = 0x22, 45 }, { 46 .slave_id = SHDMA_SLAVE_SCIF1_TX, 47 .addr = 0xffe1000c, 48 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 49 .mid_rid = 0x25, 50 }, { 51 .slave_id = SHDMA_SLAVE_SCIF1_RX, 52 .addr = 0xffe10014, 53 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 54 .mid_rid = 0x26, 55 }, { 56 .slave_id = SHDMA_SLAVE_SCIF2_TX, 57 .addr = 0xffe2000c, 58 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 59 .mid_rid = 0x29, 60 }, { 61 .slave_id = SHDMA_SLAVE_SCIF2_RX, 62 .addr = 0xffe20014, 63 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 64 .mid_rid = 0x2a, 65 }, { 66 .slave_id = SHDMA_SLAVE_SCIF3_TX, 67 .addr = 0xa4e30020, 68 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 69 .mid_rid = 0x2d, 70 }, { 71 .slave_id = SHDMA_SLAVE_SCIF3_RX, 72 .addr = 0xa4e30024, 73 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 74 .mid_rid = 0x2e, 75 }, { 76 .slave_id = SHDMA_SLAVE_SCIF4_TX, 77 .addr = 0xa4e40020, 78 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 79 .mid_rid = 0x31, 80 }, { 81 .slave_id = SHDMA_SLAVE_SCIF4_RX, 82 .addr = 0xa4e40024, 83 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 84 .mid_rid = 0x32, 85 }, { 86 .slave_id = SHDMA_SLAVE_SCIF5_TX, 87 .addr = 0xa4e50020, 88 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 89 .mid_rid = 0x35, 90 }, { 91 .slave_id = SHDMA_SLAVE_SCIF5_RX, 92 .addr = 0xa4e50024, 93 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 94 .mid_rid = 0x36, 95 }, { 96 .slave_id = SHDMA_SLAVE_USB0D0_TX, 97 .addr = 0xA4D80100, 98 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 99 .mid_rid = 0x73, 100 }, { 101 .slave_id = SHDMA_SLAVE_USB0D0_RX, 102 .addr = 0xA4D80100, 103 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 104 .mid_rid = 0x73, 105 }, { 106 .slave_id = SHDMA_SLAVE_USB0D1_TX, 107 .addr = 0xA4D80120, 108 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 109 .mid_rid = 0x77, 110 }, { 111 .slave_id = SHDMA_SLAVE_USB0D1_RX, 112 .addr = 0xA4D80120, 113 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 114 .mid_rid = 0x77, 115 }, { 116 .slave_id = SHDMA_SLAVE_USB1D0_TX, 117 .addr = 0xA4D90100, 118 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 119 .mid_rid = 0xab, 120 }, { 121 .slave_id = SHDMA_SLAVE_USB1D0_RX, 122 .addr = 0xA4D90100, 123 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 124 .mid_rid = 0xab, 125 }, { 126 .slave_id = SHDMA_SLAVE_USB1D1_TX, 127 .addr = 0xA4D90120, 128 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 129 .mid_rid = 0xaf, 130 }, { 131 .slave_id = SHDMA_SLAVE_USB1D1_RX, 132 .addr = 0xA4D90120, 133 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 134 .mid_rid = 0xaf, 135 }, { 136 .slave_id = SHDMA_SLAVE_SDHI0_TX, 137 .addr = 0x04ce0030, 138 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 139 .mid_rid = 0xc1, 140 }, { 141 .slave_id = SHDMA_SLAVE_SDHI0_RX, 142 .addr = 0x04ce0030, 143 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 144 .mid_rid = 0xc2, 145 }, { 146 .slave_id = SHDMA_SLAVE_SDHI1_TX, 147 .addr = 0x04cf0030, 148 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 149 .mid_rid = 0xc9, 150 }, { 151 .slave_id = SHDMA_SLAVE_SDHI1_RX, 152 .addr = 0x04cf0030, 153 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 154 .mid_rid = 0xca, 155 }, 156 }; 157 158 static const struct sh_dmae_channel sh7724_dmae_channels[] = { 159 { 160 .offset = 0, 161 .dmars = 0, 162 .dmars_bit = 0, 163 }, { 164 .offset = 0x10, 165 .dmars = 0, 166 .dmars_bit = 8, 167 }, { 168 .offset = 0x20, 169 .dmars = 4, 170 .dmars_bit = 0, 171 }, { 172 .offset = 0x30, 173 .dmars = 4, 174 .dmars_bit = 8, 175 }, { 176 .offset = 0x50, 177 .dmars = 8, 178 .dmars_bit = 0, 179 }, { 180 .offset = 0x60, 181 .dmars = 8, 182 .dmars_bit = 8, 183 } 184 }; 185 186 static const unsigned int ts_shift[] = TS_SHIFT; 187 188 static struct sh_dmae_pdata dma_platform_data = { 189 .slave = sh7724_dmae_slaves, 190 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves), 191 .channel = sh7724_dmae_channels, 192 .channel_num = ARRAY_SIZE(sh7724_dmae_channels), 193 .ts_low_shift = CHCR_TS_LOW_SHIFT, 194 .ts_low_mask = CHCR_TS_LOW_MASK, 195 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 196 .ts_high_mask = CHCR_TS_HIGH_MASK, 197 .ts_shift = ts_shift, 198 .ts_shift_num = ARRAY_SIZE(ts_shift), 199 .dmaor_init = DMAOR_INIT, 200 }; 201 202 /* Resource order important! */ 203 static struct resource sh7724_dmae0_resources[] = { 204 { 205 /* Channel registers and DMAOR */ 206 .start = 0xfe008020, 207 .end = 0xfe00808f, 208 .flags = IORESOURCE_MEM, 209 }, 210 { 211 /* DMARSx */ 212 .start = 0xfe009000, 213 .end = 0xfe00900b, 214 .flags = IORESOURCE_MEM, 215 }, 216 { 217 .name = "error_irq", 218 .start = 78, 219 .end = 78, 220 .flags = IORESOURCE_IRQ, 221 }, 222 { 223 /* IRQ for channels 0-3 */ 224 .start = 48, 225 .end = 51, 226 .flags = IORESOURCE_IRQ, 227 }, 228 { 229 /* IRQ for channels 4-5 */ 230 .start = 76, 231 .end = 77, 232 .flags = IORESOURCE_IRQ, 233 }, 234 }; 235 236 /* Resource order important! */ 237 static struct resource sh7724_dmae1_resources[] = { 238 { 239 /* Channel registers and DMAOR */ 240 .start = 0xfdc08020, 241 .end = 0xfdc0808f, 242 .flags = IORESOURCE_MEM, 243 }, 244 { 245 /* DMARSx */ 246 .start = 0xfdc09000, 247 .end = 0xfdc0900b, 248 .flags = IORESOURCE_MEM, 249 }, 250 { 251 .name = "error_irq", 252 .start = 74, 253 .end = 74, 254 .flags = IORESOURCE_IRQ, 255 }, 256 { 257 /* IRQ for channels 0-3 */ 258 .start = 40, 259 .end = 43, 260 .flags = IORESOURCE_IRQ, 261 }, 262 { 263 /* IRQ for channels 4-5 */ 264 .start = 72, 265 .end = 73, 266 .flags = IORESOURCE_IRQ, 267 }, 268 }; 269 270 static struct platform_device dma0_device = { 271 .name = "sh-dma-engine", 272 .id = 0, 273 .resource = sh7724_dmae0_resources, 274 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), 275 .dev = { 276 .platform_data = &dma_platform_data, 277 }, 278 }; 279 280 static struct platform_device dma1_device = { 281 .name = "sh-dma-engine", 282 .id = 1, 283 .resource = sh7724_dmae1_resources, 284 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), 285 .dev = { 286 .platform_data = &dma_platform_data, 287 }, 288 }; 289 290 /* Serial */ 291 static struct plat_sci_port scif0_platform_data = { 292 .mapbase = 0xffe00000, 293 .port_reg = SCIx_NOT_SUPPORTED, 294 .flags = UPF_BOOT_AUTOCONF, 295 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 296 .scbrr_algo_id = SCBRR_ALGO_2, 297 .type = PORT_SCIF, 298 .irqs = { 80, 80, 80, 80 }, 299 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 300 }; 301 302 static struct platform_device scif0_device = { 303 .name = "sh-sci", 304 .id = 0, 305 .dev = { 306 .platform_data = &scif0_platform_data, 307 }, 308 }; 309 310 static struct plat_sci_port scif1_platform_data = { 311 .mapbase = 0xffe10000, 312 .port_reg = SCIx_NOT_SUPPORTED, 313 .flags = UPF_BOOT_AUTOCONF, 314 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 315 .scbrr_algo_id = SCBRR_ALGO_2, 316 .type = PORT_SCIF, 317 .irqs = { 81, 81, 81, 81 }, 318 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 319 }; 320 321 static struct platform_device scif1_device = { 322 .name = "sh-sci", 323 .id = 1, 324 .dev = { 325 .platform_data = &scif1_platform_data, 326 }, 327 }; 328 329 static struct plat_sci_port scif2_platform_data = { 330 .mapbase = 0xffe20000, 331 .port_reg = SCIx_NOT_SUPPORTED, 332 .flags = UPF_BOOT_AUTOCONF, 333 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 334 .scbrr_algo_id = SCBRR_ALGO_2, 335 .type = PORT_SCIF, 336 .irqs = { 82, 82, 82, 82 }, 337 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 338 }; 339 340 static struct platform_device scif2_device = { 341 .name = "sh-sci", 342 .id = 2, 343 .dev = { 344 .platform_data = &scif2_platform_data, 345 }, 346 }; 347 348 static struct plat_sci_port scif3_platform_data = { 349 .mapbase = 0xa4e30000, 350 .port_reg = SCIx_NOT_SUPPORTED, 351 .flags = UPF_BOOT_AUTOCONF, 352 .scscr = SCSCR_RE | SCSCR_TE, 353 .scbrr_algo_id = SCBRR_ALGO_3, 354 .type = PORT_SCIFA, 355 .irqs = { 56, 56, 56, 56 }, 356 }; 357 358 static struct platform_device scif3_device = { 359 .name = "sh-sci", 360 .id = 3, 361 .dev = { 362 .platform_data = &scif3_platform_data, 363 }, 364 }; 365 366 static struct plat_sci_port scif4_platform_data = { 367 .mapbase = 0xa4e40000, 368 .port_reg = SCIx_NOT_SUPPORTED, 369 .flags = UPF_BOOT_AUTOCONF, 370 .scscr = SCSCR_RE | SCSCR_TE, 371 .scbrr_algo_id = SCBRR_ALGO_3, 372 .type = PORT_SCIFA, 373 .irqs = { 88, 88, 88, 88 }, 374 }; 375 376 static struct platform_device scif4_device = { 377 .name = "sh-sci", 378 .id = 4, 379 .dev = { 380 .platform_data = &scif4_platform_data, 381 }, 382 }; 383 384 static struct plat_sci_port scif5_platform_data = { 385 .mapbase = 0xa4e50000, 386 .port_reg = SCIx_NOT_SUPPORTED, 387 .flags = UPF_BOOT_AUTOCONF, 388 .scscr = SCSCR_RE | SCSCR_TE, 389 .scbrr_algo_id = SCBRR_ALGO_3, 390 .type = PORT_SCIFA, 391 .irqs = { 109, 109, 109, 109 }, 392 }; 393 394 static struct platform_device scif5_device = { 395 .name = "sh-sci", 396 .id = 5, 397 .dev = { 398 .platform_data = &scif5_platform_data, 399 }, 400 }; 401 402 /* RTC */ 403 static struct resource rtc_resources[] = { 404 [0] = { 405 .start = 0xa465fec0, 406 .end = 0xa465fec0 + 0x58 - 1, 407 .flags = IORESOURCE_IO, 408 }, 409 [1] = { 410 /* Period IRQ */ 411 .start = 69, 412 .flags = IORESOURCE_IRQ, 413 }, 414 [2] = { 415 /* Carry IRQ */ 416 .start = 70, 417 .flags = IORESOURCE_IRQ, 418 }, 419 [3] = { 420 /* Alarm IRQ */ 421 .start = 68, 422 .flags = IORESOURCE_IRQ, 423 }, 424 }; 425 426 static struct platform_device rtc_device = { 427 .name = "sh-rtc", 428 .id = -1, 429 .num_resources = ARRAY_SIZE(rtc_resources), 430 .resource = rtc_resources, 431 }; 432 433 /* I2C0 */ 434 static struct resource iic0_resources[] = { 435 [0] = { 436 .name = "IIC0", 437 .start = 0x04470000, 438 .end = 0x04470018 - 1, 439 .flags = IORESOURCE_MEM, 440 }, 441 [1] = { 442 .start = 96, 443 .end = 99, 444 .flags = IORESOURCE_IRQ, 445 }, 446 }; 447 448 static struct platform_device iic0_device = { 449 .name = "i2c-sh_mobile", 450 .id = 0, /* "i2c0" clock */ 451 .num_resources = ARRAY_SIZE(iic0_resources), 452 .resource = iic0_resources, 453 }; 454 455 /* I2C1 */ 456 static struct resource iic1_resources[] = { 457 [0] = { 458 .name = "IIC1", 459 .start = 0x04750000, 460 .end = 0x04750018 - 1, 461 .flags = IORESOURCE_MEM, 462 }, 463 [1] = { 464 .start = 92, 465 .end = 95, 466 .flags = IORESOURCE_IRQ, 467 }, 468 }; 469 470 static struct platform_device iic1_device = { 471 .name = "i2c-sh_mobile", 472 .id = 1, /* "i2c1" clock */ 473 .num_resources = ARRAY_SIZE(iic1_resources), 474 .resource = iic1_resources, 475 }; 476 477 /* VPU */ 478 static struct uio_info vpu_platform_data = { 479 .name = "VPU5F", 480 .version = "0", 481 .irq = 60, 482 }; 483 484 static struct resource vpu_resources[] = { 485 [0] = { 486 .name = "VPU", 487 .start = 0xfe900000, 488 .end = 0xfe902807, 489 .flags = IORESOURCE_MEM, 490 }, 491 [1] = { 492 /* place holder for contiguous memory */ 493 }, 494 }; 495 496 static struct platform_device vpu_device = { 497 .name = "uio_pdrv_genirq", 498 .id = 0, 499 .dev = { 500 .platform_data = &vpu_platform_data, 501 }, 502 .resource = vpu_resources, 503 .num_resources = ARRAY_SIZE(vpu_resources), 504 }; 505 506 /* VEU0 */ 507 static struct uio_info veu0_platform_data = { 508 .name = "VEU3F0", 509 .version = "0", 510 .irq = 83, 511 }; 512 513 static struct resource veu0_resources[] = { 514 [0] = { 515 .name = "VEU3F0", 516 .start = 0xfe920000, 517 .end = 0xfe9200cb, 518 .flags = IORESOURCE_MEM, 519 }, 520 [1] = { 521 /* place holder for contiguous memory */ 522 }, 523 }; 524 525 static struct platform_device veu0_device = { 526 .name = "uio_pdrv_genirq", 527 .id = 1, 528 .dev = { 529 .platform_data = &veu0_platform_data, 530 }, 531 .resource = veu0_resources, 532 .num_resources = ARRAY_SIZE(veu0_resources), 533 }; 534 535 /* VEU1 */ 536 static struct uio_info veu1_platform_data = { 537 .name = "VEU3F1", 538 .version = "0", 539 .irq = 54, 540 }; 541 542 static struct resource veu1_resources[] = { 543 [0] = { 544 .name = "VEU3F1", 545 .start = 0xfe924000, 546 .end = 0xfe9240cb, 547 .flags = IORESOURCE_MEM, 548 }, 549 [1] = { 550 /* place holder for contiguous memory */ 551 }, 552 }; 553 554 static struct platform_device veu1_device = { 555 .name = "uio_pdrv_genirq", 556 .id = 2, 557 .dev = { 558 .platform_data = &veu1_platform_data, 559 }, 560 .resource = veu1_resources, 561 .num_resources = ARRAY_SIZE(veu1_resources), 562 }; 563 564 /* BEU0 */ 565 static struct uio_info beu0_platform_data = { 566 .name = "BEU0", 567 .version = "0", 568 .irq = evt2irq(0x8A0), 569 }; 570 571 static struct resource beu0_resources[] = { 572 [0] = { 573 .name = "BEU0", 574 .start = 0xfe930000, 575 .end = 0xfe933400, 576 .flags = IORESOURCE_MEM, 577 }, 578 [1] = { 579 /* place holder for contiguous memory */ 580 }, 581 }; 582 583 static struct platform_device beu0_device = { 584 .name = "uio_pdrv_genirq", 585 .id = 6, 586 .dev = { 587 .platform_data = &beu0_platform_data, 588 }, 589 .resource = beu0_resources, 590 .num_resources = ARRAY_SIZE(beu0_resources), 591 }; 592 593 /* BEU1 */ 594 static struct uio_info beu1_platform_data = { 595 .name = "BEU1", 596 .version = "0", 597 .irq = evt2irq(0xA00), 598 }; 599 600 static struct resource beu1_resources[] = { 601 [0] = { 602 .name = "BEU1", 603 .start = 0xfe940000, 604 .end = 0xfe943400, 605 .flags = IORESOURCE_MEM, 606 }, 607 [1] = { 608 /* place holder for contiguous memory */ 609 }, 610 }; 611 612 static struct platform_device beu1_device = { 613 .name = "uio_pdrv_genirq", 614 .id = 7, 615 .dev = { 616 .platform_data = &beu1_platform_data, 617 }, 618 .resource = beu1_resources, 619 .num_resources = ARRAY_SIZE(beu1_resources), 620 }; 621 622 static struct sh_timer_config cmt_platform_data = { 623 .channel_offset = 0x60, 624 .timer_bit = 5, 625 .clockevent_rating = 125, 626 .clocksource_rating = 200, 627 }; 628 629 static struct resource cmt_resources[] = { 630 [0] = { 631 .start = 0x044a0060, 632 .end = 0x044a006b, 633 .flags = IORESOURCE_MEM, 634 }, 635 [1] = { 636 .start = 104, 637 .flags = IORESOURCE_IRQ, 638 }, 639 }; 640 641 static struct platform_device cmt_device = { 642 .name = "sh_cmt", 643 .id = 0, 644 .dev = { 645 .platform_data = &cmt_platform_data, 646 }, 647 .resource = cmt_resources, 648 .num_resources = ARRAY_SIZE(cmt_resources), 649 }; 650 651 static struct sh_timer_config tmu0_platform_data = { 652 .channel_offset = 0x04, 653 .timer_bit = 0, 654 .clockevent_rating = 200, 655 }; 656 657 static struct resource tmu0_resources[] = { 658 [0] = { 659 .start = 0xffd80008, 660 .end = 0xffd80013, 661 .flags = IORESOURCE_MEM, 662 }, 663 [1] = { 664 .start = 16, 665 .flags = IORESOURCE_IRQ, 666 }, 667 }; 668 669 static struct platform_device tmu0_device = { 670 .name = "sh_tmu", 671 .id = 0, 672 .dev = { 673 .platform_data = &tmu0_platform_data, 674 }, 675 .resource = tmu0_resources, 676 .num_resources = ARRAY_SIZE(tmu0_resources), 677 }; 678 679 static struct sh_timer_config tmu1_platform_data = { 680 .channel_offset = 0x10, 681 .timer_bit = 1, 682 .clocksource_rating = 200, 683 }; 684 685 static struct resource tmu1_resources[] = { 686 [0] = { 687 .start = 0xffd80014, 688 .end = 0xffd8001f, 689 .flags = IORESOURCE_MEM, 690 }, 691 [1] = { 692 .start = 17, 693 .flags = IORESOURCE_IRQ, 694 }, 695 }; 696 697 static struct platform_device tmu1_device = { 698 .name = "sh_tmu", 699 .id = 1, 700 .dev = { 701 .platform_data = &tmu1_platform_data, 702 }, 703 .resource = tmu1_resources, 704 .num_resources = ARRAY_SIZE(tmu1_resources), 705 }; 706 707 static struct sh_timer_config tmu2_platform_data = { 708 .channel_offset = 0x1c, 709 .timer_bit = 2, 710 }; 711 712 static struct resource tmu2_resources[] = { 713 [0] = { 714 .start = 0xffd80020, 715 .end = 0xffd8002b, 716 .flags = IORESOURCE_MEM, 717 }, 718 [1] = { 719 .start = 18, 720 .flags = IORESOURCE_IRQ, 721 }, 722 }; 723 724 static struct platform_device tmu2_device = { 725 .name = "sh_tmu", 726 .id = 2, 727 .dev = { 728 .platform_data = &tmu2_platform_data, 729 }, 730 .resource = tmu2_resources, 731 .num_resources = ARRAY_SIZE(tmu2_resources), 732 }; 733 734 735 static struct sh_timer_config tmu3_platform_data = { 736 .channel_offset = 0x04, 737 .timer_bit = 0, 738 }; 739 740 static struct resource tmu3_resources[] = { 741 [0] = { 742 .start = 0xffd90008, 743 .end = 0xffd90013, 744 .flags = IORESOURCE_MEM, 745 }, 746 [1] = { 747 .start = 57, 748 .flags = IORESOURCE_IRQ, 749 }, 750 }; 751 752 static struct platform_device tmu3_device = { 753 .name = "sh_tmu", 754 .id = 3, 755 .dev = { 756 .platform_data = &tmu3_platform_data, 757 }, 758 .resource = tmu3_resources, 759 .num_resources = ARRAY_SIZE(tmu3_resources), 760 }; 761 762 static struct sh_timer_config tmu4_platform_data = { 763 .channel_offset = 0x10, 764 .timer_bit = 1, 765 }; 766 767 static struct resource tmu4_resources[] = { 768 [0] = { 769 .start = 0xffd90014, 770 .end = 0xffd9001f, 771 .flags = IORESOURCE_MEM, 772 }, 773 [1] = { 774 .start = 58, 775 .flags = IORESOURCE_IRQ, 776 }, 777 }; 778 779 static struct platform_device tmu4_device = { 780 .name = "sh_tmu", 781 .id = 4, 782 .dev = { 783 .platform_data = &tmu4_platform_data, 784 }, 785 .resource = tmu4_resources, 786 .num_resources = ARRAY_SIZE(tmu4_resources), 787 }; 788 789 static struct sh_timer_config tmu5_platform_data = { 790 .channel_offset = 0x1c, 791 .timer_bit = 2, 792 }; 793 794 static struct resource tmu5_resources[] = { 795 [0] = { 796 .start = 0xffd90020, 797 .end = 0xffd9002b, 798 .flags = IORESOURCE_MEM, 799 }, 800 [1] = { 801 .start = 57, 802 .flags = IORESOURCE_IRQ, 803 }, 804 }; 805 806 static struct platform_device tmu5_device = { 807 .name = "sh_tmu", 808 .id = 5, 809 .dev = { 810 .platform_data = &tmu5_platform_data, 811 }, 812 .resource = tmu5_resources, 813 .num_resources = ARRAY_SIZE(tmu5_resources), 814 }; 815 816 /* JPU */ 817 static struct uio_info jpu_platform_data = { 818 .name = "JPU", 819 .version = "0", 820 .irq = 27, 821 }; 822 823 static struct resource jpu_resources[] = { 824 [0] = { 825 .name = "JPU", 826 .start = 0xfe980000, 827 .end = 0xfe9902d3, 828 .flags = IORESOURCE_MEM, 829 }, 830 [1] = { 831 /* place holder for contiguous memory */ 832 }, 833 }; 834 835 static struct platform_device jpu_device = { 836 .name = "uio_pdrv_genirq", 837 .id = 3, 838 .dev = { 839 .platform_data = &jpu_platform_data, 840 }, 841 .resource = jpu_resources, 842 .num_resources = ARRAY_SIZE(jpu_resources), 843 }; 844 845 /* SPU2DSP0 */ 846 static struct uio_info spu0_platform_data = { 847 .name = "SPU2DSP0", 848 .version = "0", 849 .irq = 86, 850 }; 851 852 static struct resource spu0_resources[] = { 853 [0] = { 854 .name = "SPU2DSP0", 855 .start = 0xFE200000, 856 .end = 0xFE2FFFFF, 857 .flags = IORESOURCE_MEM, 858 }, 859 [1] = { 860 /* place holder for contiguous memory */ 861 }, 862 }; 863 864 static struct platform_device spu0_device = { 865 .name = "uio_pdrv_genirq", 866 .id = 4, 867 .dev = { 868 .platform_data = &spu0_platform_data, 869 }, 870 .resource = spu0_resources, 871 .num_resources = ARRAY_SIZE(spu0_resources), 872 }; 873 874 /* SPU2DSP1 */ 875 static struct uio_info spu1_platform_data = { 876 .name = "SPU2DSP1", 877 .version = "0", 878 .irq = 87, 879 }; 880 881 static struct resource spu1_resources[] = { 882 [0] = { 883 .name = "SPU2DSP1", 884 .start = 0xFE300000, 885 .end = 0xFE3FFFFF, 886 .flags = IORESOURCE_MEM, 887 }, 888 [1] = { 889 /* place holder for contiguous memory */ 890 }, 891 }; 892 893 static struct platform_device spu1_device = { 894 .name = "uio_pdrv_genirq", 895 .id = 5, 896 .dev = { 897 .platform_data = &spu1_platform_data, 898 }, 899 .resource = spu1_resources, 900 .num_resources = ARRAY_SIZE(spu1_resources), 901 }; 902 903 static struct platform_device *sh7724_devices[] __initdata = { 904 &scif0_device, 905 &scif1_device, 906 &scif2_device, 907 &scif3_device, 908 &scif4_device, 909 &scif5_device, 910 &cmt_device, 911 &tmu0_device, 912 &tmu1_device, 913 &tmu2_device, 914 &tmu3_device, 915 &tmu4_device, 916 &tmu5_device, 917 &dma0_device, 918 &dma1_device, 919 &rtc_device, 920 &iic0_device, 921 &iic1_device, 922 &vpu_device, 923 &veu0_device, 924 &veu1_device, 925 &beu0_device, 926 &beu1_device, 927 &jpu_device, 928 &spu0_device, 929 &spu1_device, 930 }; 931 932 static int __init sh7724_devices_setup(void) 933 { 934 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 935 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 936 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 937 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 938 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20); 939 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20); 940 941 return platform_add_devices(sh7724_devices, 942 ARRAY_SIZE(sh7724_devices)); 943 } 944 arch_initcall(sh7724_devices_setup); 945 946 static struct platform_device *sh7724_early_devices[] __initdata = { 947 &scif0_device, 948 &scif1_device, 949 &scif2_device, 950 &scif3_device, 951 &scif4_device, 952 &scif5_device, 953 &cmt_device, 954 &tmu0_device, 955 &tmu1_device, 956 &tmu2_device, 957 &tmu3_device, 958 &tmu4_device, 959 &tmu5_device, 960 }; 961 962 void __init plat_early_device_setup(void) 963 { 964 early_platform_add_devices(sh7724_early_devices, 965 ARRAY_SIZE(sh7724_early_devices)); 966 } 967 968 #define RAMCR_CACHE_L2FC 0x0002 969 #define RAMCR_CACHE_L2E 0x0001 970 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 971 972 void l2_cache_init(void) 973 { 974 /* Enable L2 cache */ 975 __raw_writel(L2_CACHE_ENABLE, RAMCR); 976 } 977 978 enum { 979 UNUSED = 0, 980 ENABLED, 981 DISABLED, 982 983 /* interrupt sources */ 984 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 985 HUDI, 986 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, 987 _2DG_TRI, _2DG_INI, _2DG_CEI, 988 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, 989 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, 990 SCIFA3, 991 VPU, 992 TPU, 993 CEU1, 994 BEU1, 995 USB0, USB1, 996 ATAPI, 997 RTC_ATI, RTC_PRI, RTC_CUI, 998 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, 999 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, 1000 KEYSC, 1001 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, 1002 VEU0, 1003 MSIOF_MSIOFI0, MSIOF_MSIOFI1, 1004 SPU_SPUI0, SPU_SPUI1, 1005 SCIFA4, 1006 ICB, 1007 ETHI, 1008 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 1009 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 1010 CMT, 1011 TSIF, 1012 FSI, 1013 SCIFA5, 1014 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 1015 IRDA, 1016 JPU, 1017 _2DDMAC, 1018 MMC_MMC2I, MMC_MMC3I, 1019 LCDC, 1020 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 1021 1022 /* interrupt groups */ 1023 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, 1024 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, 1025 }; 1026 1027 static struct intc_vect vectors[] __initdata = { 1028 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 1029 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 1030 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 1031 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 1032 1033 INTC_VECT(DMAC1A_DEI0, 0x700), 1034 INTC_VECT(DMAC1A_DEI1, 0x720), 1035 INTC_VECT(DMAC1A_DEI2, 0x740), 1036 INTC_VECT(DMAC1A_DEI3, 0x760), 1037 1038 INTC_VECT(_2DG_TRI, 0x780), 1039 INTC_VECT(_2DG_INI, 0x7A0), 1040 INTC_VECT(_2DG_CEI, 0x7C0), 1041 1042 INTC_VECT(DMAC0A_DEI0, 0x800), 1043 INTC_VECT(DMAC0A_DEI1, 0x820), 1044 INTC_VECT(DMAC0A_DEI2, 0x840), 1045 INTC_VECT(DMAC0A_DEI3, 0x860), 1046 1047 INTC_VECT(VIO_CEU0, 0x880), 1048 INTC_VECT(VIO_BEU0, 0x8A0), 1049 INTC_VECT(VIO_VEU1, 0x8C0), 1050 INTC_VECT(VIO_VOU, 0x8E0), 1051 1052 INTC_VECT(SCIFA3, 0x900), 1053 INTC_VECT(VPU, 0x980), 1054 INTC_VECT(TPU, 0x9A0), 1055 INTC_VECT(CEU1, 0x9E0), 1056 INTC_VECT(BEU1, 0xA00), 1057 INTC_VECT(USB0, 0xA20), 1058 INTC_VECT(USB1, 0xA40), 1059 INTC_VECT(ATAPI, 0xA60), 1060 1061 INTC_VECT(RTC_ATI, 0xA80), 1062 INTC_VECT(RTC_PRI, 0xAA0), 1063 INTC_VECT(RTC_CUI, 0xAC0), 1064 1065 INTC_VECT(DMAC1B_DEI4, 0xB00), 1066 INTC_VECT(DMAC1B_DEI5, 0xB20), 1067 INTC_VECT(DMAC1B_DADERR, 0xB40), 1068 1069 INTC_VECT(DMAC0B_DEI4, 0xB80), 1070 INTC_VECT(DMAC0B_DEI5, 0xBA0), 1071 INTC_VECT(DMAC0B_DADERR, 0xBC0), 1072 1073 INTC_VECT(KEYSC, 0xBE0), 1074 INTC_VECT(SCIF_SCIF0, 0xC00), 1075 INTC_VECT(SCIF_SCIF1, 0xC20), 1076 INTC_VECT(SCIF_SCIF2, 0xC40), 1077 INTC_VECT(VEU0, 0xC60), 1078 INTC_VECT(MSIOF_MSIOFI0, 0xC80), 1079 INTC_VECT(MSIOF_MSIOFI1, 0xCA0), 1080 INTC_VECT(SPU_SPUI0, 0xCC0), 1081 INTC_VECT(SPU_SPUI1, 0xCE0), 1082 INTC_VECT(SCIFA4, 0xD00), 1083 1084 INTC_VECT(ICB, 0xD20), 1085 INTC_VECT(ETHI, 0xD60), 1086 1087 INTC_VECT(I2C1_ALI, 0xD80), 1088 INTC_VECT(I2C1_TACKI, 0xDA0), 1089 INTC_VECT(I2C1_WAITI, 0xDC0), 1090 INTC_VECT(I2C1_DTEI, 0xDE0), 1091 1092 INTC_VECT(I2C0_ALI, 0xE00), 1093 INTC_VECT(I2C0_TACKI, 0xE20), 1094 INTC_VECT(I2C0_WAITI, 0xE40), 1095 INTC_VECT(I2C0_DTEI, 0xE60), 1096 1097 INTC_VECT(SDHI0, 0xE80), 1098 INTC_VECT(SDHI0, 0xEA0), 1099 INTC_VECT(SDHI0, 0xEC0), 1100 INTC_VECT(SDHI0, 0xEE0), 1101 1102 INTC_VECT(CMT, 0xF00), 1103 INTC_VECT(TSIF, 0xF20), 1104 INTC_VECT(FSI, 0xF80), 1105 INTC_VECT(SCIFA5, 0xFA0), 1106 1107 INTC_VECT(TMU0_TUNI0, 0x400), 1108 INTC_VECT(TMU0_TUNI1, 0x420), 1109 INTC_VECT(TMU0_TUNI2, 0x440), 1110 1111 INTC_VECT(IRDA, 0x480), 1112 1113 INTC_VECT(SDHI1, 0x4E0), 1114 INTC_VECT(SDHI1, 0x500), 1115 INTC_VECT(SDHI1, 0x520), 1116 1117 INTC_VECT(JPU, 0x560), 1118 INTC_VECT(_2DDMAC, 0x4A0), 1119 1120 INTC_VECT(MMC_MMC2I, 0x5A0), 1121 INTC_VECT(MMC_MMC3I, 0x5C0), 1122 1123 INTC_VECT(LCDC, 0xF40), 1124 1125 INTC_VECT(TMU1_TUNI0, 0x920), 1126 INTC_VECT(TMU1_TUNI1, 0x940), 1127 INTC_VECT(TMU1_TUNI2, 0x960), 1128 }; 1129 1130 static struct intc_group groups[] __initdata = { 1131 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), 1132 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), 1133 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), 1134 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), 1135 INTC_GROUP(USB, USB0, USB1), 1136 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 1137 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), 1138 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 1139 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 1140 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 1141 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 1142 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 1143 }; 1144 1145 static struct intc_mask_reg mask_registers[] __initdata = { 1146 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 1147 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 1148 0, ENABLED, ENABLED, ENABLED } }, 1149 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 1150 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 1151 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 1152 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 1153 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, 1154 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 1155 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, 1156 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, 1157 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 1158 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, 1159 JPU, 0, 0, LCDC } }, 1160 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 1161 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 1162 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 1163 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 1164 { 0, 0, ICB, SCIFA4, 1165 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 1166 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 1167 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 1168 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 1169 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 1170 { DISABLED, ENABLED, ENABLED, ENABLED, 1171 0, 0, SCIFA5, FSI } }, 1172 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 1173 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 1174 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 1175 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, 1176 0, RTC_CUI, RTC_PRI, RTC_ATI } }, 1177 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 1178 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, 1179 0, TPU, 0, TSIF } }, 1180 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 1181 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, 1182 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 1183 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1184 }; 1185 1186 static struct intc_prio_reg prio_registers[] __initdata = { 1187 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, 1188 TMU0_TUNI2, IRDA } }, 1189 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, 1190 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, 1191 TMU1_TUNI2, SPU } }, 1192 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, 1193 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, 1194 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, 1195 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, 1196 SCIF_SCIF2, VEU0 } }, 1197 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, 1198 I2C1, I2C0 } }, 1199 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, 1200 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, 1201 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, 1202 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, 1203 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 1204 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1205 }; 1206 1207 static struct intc_sense_reg sense_registers[] __initdata = { 1208 { 0xa414001c, 16, 2, /* ICR1 */ 1209 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1210 }; 1211 1212 static struct intc_mask_reg ack_registers[] __initdata = { 1213 { 0xa4140024, 0, 8, /* INTREQ00 */ 1214 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1215 }; 1216 1217 static struct intc_desc intc_desc __initdata = { 1218 .name = "sh7724", 1219 .force_enable = ENABLED, 1220 .force_disable = DISABLED, 1221 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 1222 prio_registers, sense_registers, ack_registers), 1223 }; 1224 1225 void __init plat_irq_setup(void) 1226 { 1227 register_intc_controller(&intc_desc); 1228 } 1229 1230 static struct { 1231 /* BSC */ 1232 unsigned long mmselr; 1233 unsigned long cs0bcr; 1234 unsigned long cs4bcr; 1235 unsigned long cs5abcr; 1236 unsigned long cs5bbcr; 1237 unsigned long cs6abcr; 1238 unsigned long cs6bbcr; 1239 unsigned long cs4wcr; 1240 unsigned long cs5awcr; 1241 unsigned long cs5bwcr; 1242 unsigned long cs6awcr; 1243 unsigned long cs6bwcr; 1244 /* INTC */ 1245 unsigned short ipra; 1246 unsigned short iprb; 1247 unsigned short iprc; 1248 unsigned short iprd; 1249 unsigned short ipre; 1250 unsigned short iprf; 1251 unsigned short iprg; 1252 unsigned short iprh; 1253 unsigned short ipri; 1254 unsigned short iprj; 1255 unsigned short iprk; 1256 unsigned short iprl; 1257 unsigned char imr0; 1258 unsigned char imr1; 1259 unsigned char imr2; 1260 unsigned char imr3; 1261 unsigned char imr4; 1262 unsigned char imr5; 1263 unsigned char imr6; 1264 unsigned char imr7; 1265 unsigned char imr8; 1266 unsigned char imr9; 1267 unsigned char imr10; 1268 unsigned char imr11; 1269 unsigned char imr12; 1270 /* RWDT */ 1271 unsigned short rwtcnt; 1272 unsigned short rwtcsr; 1273 /* CPG */ 1274 unsigned long irdaclk; 1275 unsigned long spuclk; 1276 } sh7724_rstandby_state; 1277 1278 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb, 1279 unsigned long flags, void *unused) 1280 { 1281 if (!(flags & SUSP_SH_RSTANDBY)) 1282 return NOTIFY_DONE; 1283 1284 /* BCR */ 1285 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ 1286 sh7724_rstandby_state.mmselr |= 0xa5a50000; 1287 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ 1288 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ 1289 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ 1290 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ 1291 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ 1292 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ 1293 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ 1294 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ 1295 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ 1296 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ 1297 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ 1298 1299 /* INTC */ 1300 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */ 1301 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */ 1302 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */ 1303 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */ 1304 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */ 1305 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */ 1306 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */ 1307 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */ 1308 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */ 1309 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */ 1310 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */ 1311 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */ 1312 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */ 1313 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */ 1314 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */ 1315 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */ 1316 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */ 1317 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */ 1318 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */ 1319 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */ 1320 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */ 1321 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */ 1322 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */ 1323 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */ 1324 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */ 1325 1326 /* RWDT */ 1327 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */ 1328 sh7724_rstandby_state.rwtcnt |= 0x5a00; 1329 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */ 1330 sh7724_rstandby_state.rwtcsr |= 0xa500; 1331 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004); 1332 1333 /* CPG */ 1334 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */ 1335 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */ 1336 1337 return NOTIFY_DONE; 1338 } 1339 1340 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb, 1341 unsigned long flags, void *unused) 1342 { 1343 if (!(flags & SUSP_SH_RSTANDBY)) 1344 return NOTIFY_DONE; 1345 1346 /* BCR */ 1347 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ 1348 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ 1349 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ 1350 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ 1351 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ 1352 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ 1353 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ 1354 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ 1355 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ 1356 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */ 1357 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */ 1358 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */ 1359 1360 /* INTC */ 1361 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */ 1362 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */ 1363 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */ 1364 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */ 1365 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */ 1366 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */ 1367 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */ 1368 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */ 1369 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */ 1370 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */ 1371 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */ 1372 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */ 1373 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ 1374 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ 1375 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ 1376 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ 1377 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ 1378 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ 1379 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ 1380 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ 1381 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ 1382 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ 1383 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */ 1384 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */ 1385 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */ 1386 1387 /* RWDT */ 1388 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */ 1389 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */ 1390 1391 /* CPG */ 1392 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */ 1393 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */ 1394 1395 return NOTIFY_DONE; 1396 } 1397 1398 static struct notifier_block sh7724_pre_sleep_notifier = { 1399 .notifier_call = sh7724_pre_sleep_notifier_call, 1400 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU), 1401 }; 1402 1403 static struct notifier_block sh7724_post_sleep_notifier = { 1404 .notifier_call = sh7724_post_sleep_notifier_call, 1405 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU), 1406 }; 1407 1408 static int __init sh7724_sleep_setup(void) 1409 { 1410 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list, 1411 &sh7724_pre_sleep_notifier); 1412 1413 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list, 1414 &sh7724_post_sleep_notifier); 1415 return 0; 1416 } 1417 arch_initcall(sh7724_sleep_setup); 1418 1419